True Random Number Research Articles

Probabilistic computing with voltage-controlled dynamics in magnetic tunnel junctions

Probabilistic (p-) computing is a physics-based approach to addressing computational problems which are difficult to solve by conventional von Neumann computers. A key requirement for p-computing is the realization of fast, compact, and energy-efficient probabilistic bits. Stochastic magnetic tunnel junctions (MTJs) with low energy barriers, where the relative dwell time in each state is controlled by current, have been proposed as a candidate to implement p-bits. This approach presents challenges due to the need for precise control of a small energy barrier across large numbers of MTJs, and due to the need for an analog control signal. Here we demonstrate an alternative p-bit design based on perpendicular MTJs that uses the voltage-controlled magnetic anisotropy (VCMA) effect to create the random state of a p-bit on demand. The MTJs are stable (i.e. have large energy barriers) in the absence of voltage, and VCMA-induced dynamics are used to generate random numbers in less than 10 ns/bit. We then show a compact method of implementing p-bits by using VC-MTJs without a bias current. As a demonstration of the feasibility of the proposed p-bits and high quality of the generated random numbers, we solve up to 40 bit integer factorization problems using experimental bit-streams generated by VC-MTJs. Our proposal can impact the development of p-computers, both by supporting a fully spintronic implementation of a p-bit, and alternatively, by enabling true random number generation at low cost for ultralow-power and compact p-computers implemented in complementary metal-oxide semiconductor chips.

Robust and Accessible True Random Number Generator Exploiting the Structural Frustration of Nematic Liquid Crystals

AbstractThe study proposes a highly credible true random number generator based on the structural frustration of nematic liquid crystals, which refers to the appearance of two energetically equivalent structures in a nematic system. Frustration is induced in a simple liquid crystal cell by applying an electric field and observing optical textures under crossed polarizers. A clockwise or counterclockwise spiral image appears on 630 separate circular electrodes under the electric field, and random binary sequences are obtained by assigning a digit of 0 or 1 to each image. These sequences pass the strict statistical randomness tests of the National Institute of Standards and Technology with a pass rate of 0.992 or higher for the ten applicable tests and exhibit excellent uniformity. Furthermore, a simple method is introduced to convert the binary results to random decimal numbers with only a minimal amount of data processing.

A new conservative chaotic system and its application in image encryption

A new n-dimensional conservative chaotic model is proposed to quickly realise a conservative chaotic system. The validity of this model is verified by generating a five-dimensional conservative chaotic system as an example. This system is dynamically analysed from the perspective of Lyapunov exponents (LEs), complexity and phase diagram, which prove its good chaotic properties. Compared with existing systems, the proposed system has a simple structure, large LEs, continuous chaotic ranges and high complexity. Additionally, the National Institute of Standards and Technology verified that the proposed system demonstrates good randomness and is implemented on a digital signal processor hardware platform. Subsequently, a new image encryption scheme that uses true random numbers, lattice-based public key cryptography and dynamic P- and S-boxes is presented based on the new system. The results show that the algorithm demonstrates the capability of the cryptosystem to achieve quality encryption while resisting quantum computer, statistical, differential and cutting attacks compared with other encryption algorithms.

A Lightweight True Random Number Generator for Root of Trust Applications

There are many schemes proposed to protect integrated circuits (ICs) against an unauthorized access and usage, or at least to mitigate security risks. They lay foundations for hardware roots of trust whose crucial security primitives are generators of truly random numbers. In particular, such generators are used to yield one-time challenges (nonces) supporting the IC authentication protocols employed to counteract potential threats such as untrusted users accessing ICs. However, IC vendors raise several concerns regarding the complexity of these solutions, both in terms of area overhead, the impact on the design flow, and testability. These concerns have motivated this work presenting a simple, yet effective, all-digital lightweight and self-testable random number generator to produce a nonce. It builds on a generic ring generator architecture, i.e., an area and time optimized version of a linear feedback shift register, driven by a multiple-output ring oscillator. A comprehensive evaluation, based on three statistical test suits from NIST and BSI, show feasibility and efficiency of the proposed scheme and are reported herein.

In-plane dominant anisotropy stochastic magnetic tunnel junction for probabilistic computing: A Fokker–Planck study

Recently there is considerable interest to realize efficient and low-cost true random number generators (RNGs) for practical applications. One important way is through the use of bistable magnetic tunnel junctions (MTJs). Here we study the magnetization dynamics of an MTJ, with a focus to realize efficient random bit generation under the assumption that the orientation dependence of the energy of the nanomagnet is described by two perpendicular in-plane anisotropies. We find that a high rate of random bit generation is achievable away from the pure easy-axis situation by tuning a single parameter Hz so that it is either (a) toward a barrierless-like single easy plane situation when Hz reduces to zero, or (b) toward a stronger easy plane situation when Hz becomes increasingly negative where transitions between low energy states are confined in the stronger easy plane that contains the saddle points. We find that the MTJs maintain their fast magnetization dynamical characteristics even in the presence of a magnetic field. Our findings provide a valuable guide to achieving efficient generation of probabilistic bits for applications in probabilistic computing.

A Peripheral-Free True Random Number Generator Based on Integrated Circuits Enabled by Atomically Thin Two-Dimensional Materials.

A true random number generator (TRNG) is essential to ensure information security for Internet of Things (IoT) edge devices. While pseudorandom number generators (PRNGs) have been instrumental, their deterministic nature limits their application in security-sensitive scenarios. In contrast, hardware-based TRNGs derived from physically unpredictable processes offer greater reliability. This study demonstrates a peripheral-free TRNG utilizing two cascaded three-stage inverters (TSIs) in conjunction with an XOR gate composed of monolayer molybdenum disulfide (MoS2) field-effect transistors (FETs) by exploiting the stochastic charge trapping and detrapping phenomena at and/or near the MoS2/dielectric interface. The entropy source passes the NIST SP800-90B tests with a minimum normalized entropy of 0.8780, while the generated bits pass the NIST SP800-22 randomness tests without any postprocessing. Moreover, the keys generated using these random bits are uncorrelated with near-ideal entropy, bit uniformity, and Hamming distances, exhibiting resilience against machine learning (ML) attacks, temperature variations, and supply bias fluctuations with a frugal energy expenditure of 30 pJ/bit. This approach offers an advantageous alternative to conventional silicon, memristive, and nanomaterial-based TRNGs as it obviates the need for extensive peripherals while harnessing the potential of atomically thin 2D materials in developing low-power TRNGs.

Optimizing free layer of Magnetic Tunnel Junction for true random number generator

True random number generators (TRNGs) should ideally generate lengthy chains of non-repeating, uncorrelated bit-streams that are efficient in terms of both energy and area. Current TRNG designs include source of randomness such as CMOS or non-volatile memory based devices with additional circuitry to improve the quality of randomness leading to power and area overhead. This paper addresses these issues by improving the randomness of the Spin-Orbit Torque (SOT)-Magnetic Tunnel Junction cell. Motivated by the observation that free layer thickness of Magnetic Tunnel Junction (MTJ) can be scaled to design a low-barrier device, the paper proposes a novel source of randomness called ΔSOT. This device is then used to design TRNG circuits that achieves high quality random telegraphic switching behavior without any additional circuitry making it suitable for ultra-low power applications. Evaluations show that ΔSOT-TRNG has significant reduction in energy (51%) and area (66%) compared to state-of-the-art MTJ based TRNG design. Furthermore, the work shows that the improved switching speed of the reduced barrier junction can results in 65% increase in throughput compared to MTJ based TRNG design.

Ultrafast Random Number Generation Based on Random Laser

True random numbers with high security originate from non-deterministic physical processes. Random laser with random feedback arising from multiple elastic scattering in a highly disordered structure is an ideal physical entropy source theoretically. In this work, a secure optical ultrafast random number generator based on random laser spectra was demonstrated. Unlike the usual method of recording laser intensity over time, the random laser spectrum under each pump pulse was recorded and converted into random numbers through post-processing. Approaches in three different dimensions—space, spectrum and time were used to increase the rate of random number generation. The randomness of resulting random bit streams was verified by the NIST statistics tests. Experimental results showed that an instantaneous bit rate of 810 terabits per second with off-line post-processing could be theoretically reached with an ideal experimental condition. This novel technique has big advantages in secure communications and promises to further increase the speed of random number generators to the lever of petabits per second or even higher.

Micromagnetic simulation for random magnetization switching process of a spin–orbit true random number generator

True random number generator (TRNG) is an important component for modern information security technologies. Among the candidates, TRNG with spin–orbit torque (SOT)-induced probabilistic magnetization switching is expected to be competitive for its advantages in anti-radiation, unlimited endurance, robust stability, and broad temperature range. However, specific mechanism of the randomness in SOT-induced magnetization switching are still not clear, which limits the demonstration of applicable SOT-TRNG. Here, we performed micromagnetic simulation of the SOT-induced probabilistic magnetization switching by using MuMax3. When various thermal noise seeds were introduced, not only stochastic precession trails within the current pulses, but also stochastic precession tendency after removing the current pulse were obtained, together resulting in random final magnetization states. Particularly, the consistency between mz orientations at the current withdraw moment and at the final stabilized magnetization state shows a positive correlation with the fluctuation range of mz during the current pulse duration, the latter of which narrows with the increasing of channel current density. Our work suggests the importance of thermal noise-related magnetization precession variations on the SOT-induced probabilistic magnetization switching, and suggesting the MuMax3 to be a practical tool for simulating the SOT-TRNG.

MRAM Devices to Design Ternary Addressable Physically Unclonable Functions

We introduce a novel approach to constructing ternary addressable physically unclonable functions (TAPUFs) using magnetoresistive random-access memory (MRAM) devices. TAPUFs use three states (1, 0, and X) to track unstable cells. The proposed TAPUF leverages the resistance properties of MRAM cells to produce unique digital fingerprints that can be effectively utilized in cryptographic protocols. We exploit the cell-to-cell variations in resistance values to generate reliable cryptographic keys and true random numbers, which can add protection against certain attacks. To evaluate the performance of the TAPUF, various tests were conducted, including assessments of inter-cell to intra-cell variation, inter-distance, bit error rate (BER), and temperature variation. These experiments were conducted using a low-power client device to replicate practical scenarios. The obtained results demonstrate that the proposed TAPUF exhibits exceptional scalability, energy efficiency, and reliability.

A chaos-metastability TRNG for natively flexible IGZO circuits

Modern technologies of truly flexible integrated circuits are usually based on large single-type transistors. If considered as a platform for Internet-of-Things (IoT) devices, they would require dedicated cryptographic solutions that could fit their limitations. In this article, we present an implementation of an efficient and fast-start true random number generator (TRNG) developed with a metal-oxide thin-film transistor (TFT) technology on a flexible substrate. This is our first full-custom TRNG implementation following the programmable logic ones. The architecture of the TRNG utilizes a chaotic circuit boosting an RS flip-flop leading to random oscillatory metastable behavior. The implementation is based on indium-gallium-zinc oxide (IGZO or InGaZnO) n-type TFT transistors with 0.8 × 5 μm channels. The solution delivers constant 66.7 kbit/s stream produced by 0.3 square millimeters of a flexible thin-film circuit using 200 μW of power. The randomness of the TRNG binary stream was verified by Diehard and NIST Suit tests.

DCDRO:A true random number generator based on dynamically configurable dual-output ring oscillator

As an essential component of modern encryption systems, a true random number generator (TRNG) has made significant contributions to information security. A configurable true random number generator with low hardware overhead and high throughput is presented in this paper. The structure utilizes an odd number of NAND gates and XOR gates to create a dynamically configurable dual-output ring oscillator. By increasing the phase noise in a short period, the time jitter range is expanded, thereby improving the randomness of the entropy source. Additionally, the XOR post-processing reduces the bias of the random sequence. The structure has undergone several tests and validations on the Xilinx Kintex-7, and the experimental results demonstrate that the proposed TRNG has strong robustness under varying environmental conditions, including different temperatures (0 °C–80 °C) and output voltages (0.8 V–1.2 V). It only consumes 28 LUTS and 5 DFFs in hardware resources and achieves a throughput of up to 200 Mb/s.

Practical security analysis of a continuous-variable source-independent quantum random number generator based on heterodyne detection.

Heterodyne-based continuous-variable source-independent quantum random number generator (CV-SI-QRNG) can produce true random numbers without any assumptions on source. However, practical implementations always contain imperfections, which will greatly influence the extractable randomness and even open loopholes for eavesdroppers to steal information about the final output. In this work, based on the theoretical model, we systematically analyzed the effects of imperfect implementations on the practical security of heterodyne-based CV-SI-QRNG. The influences of local oscillator (LO) fluctuation under imbalanced heterodyne detection are first analyzed. The simulation results show that the lower bound of extractable randomness will be overestimated without considering the influence of LO fluctuation, which will threaten the practical security of CV-SI-QRNG system. Moreover, we analyze the effects of the degree of imbalance and the magnitude of LO fluctuation on evaluating the extractable randomness. Finally, we investigate the impact of an imperfect phase modulator on the practical security of CV-SI-QRNG and find it will reduce the extractable randomness. Our analysis reveals that one should carefully consider the imperfections in the actual implementations of CV-SI-QRNGs.

Evaluation of True Random Number Sequences Generated by Utilizing Timing Jitters in Superconducting Integrated Circuits

A Hardware Random Number Generator (HRNG), which generates true random number sequences, is studied. In superconducting Single Flux Quantum (SFQ) circuitry, HRNGs that utilized timing jitters in trigger signals have been demonstrated. In this paper, we propose an HRNG with two oscillators to enhance stability against variation of oscillator frequencies. We investigate the characteristics of random numbers generated with the proposed HRNG not only by numerical simulation but also by experiments using Nb test circuits. In the numerical simulation, the probability of “1” in random number sequences has a local minimum of “1” output probability at conditions where fclk (the clock oscillator frequency) and fgate (the gate oscillator frequency) are approximately equal (fclk ≈ fgate ) for fclk ≤ 60 GHz. It is also found that pass rates for the FIPS140-2 random number tests are little affected by variations of fclk at fgate = 69.2 GHz. The random number generation rate for fclk = 60 GHz and fgate = 43 GHz reaches 3.98 GHz. In experimental measurements, random numbers of 1 Mbits generated by a test circuit pass the SP800-22 random number tests at fclk = 48.79 GHz and fgate = 19.81 GHz.

Testing and reliability enhancement of security primitives: Methodology and experimental validation

The test of security primitives is particularly strategic as any bias coming from the implementation or environment can wreak havoc on the security it is intended to provide. This paper presents how some security properties are tested on hardware security primitives including True Random Number Generation (TRNG), Physically Unclonable Function (PUF), and cryptographic modules. Moreover, we discuss how the sensors embedded to protect cryptographic modules against fault injection attacks should be calibrated over time to fulfill the requirement it was designed for. The testing we discuss in this paper is different from the conventional testing where we consider a fault model and generate test patterns via an ATPG to detect such faults. The test of TRNG and PUF to ensure a high level of security is mainly about the entropy assessment, which requires specific statistical tests. The security against side-channel analysis (SCA) of cryptographic primitives, like the substitution box in symmetric cryptography, is generally ensured by masking. However, the hardware implementation of masking can be damaged by glitches, which create leakages on sensitive variables. Accordingly, a test method is to search for nets of the cryptographic netlist, which are vulnerable to glitches. Finally, the Digital Sensor (DS) is an efficient primitive to detect disturbances and raise alarms in the case of fault injection attack (FIA). The dimensioning of this primitive requires a precise test to take into account the environmental variations including aging.This paper extends on a conference paper presented at DFTS’21 by the same co-authors, where the test methodology for three critical security primitives is presented. In addition, in this paper, we add experimental validation to show how such testing methodology is applied in practice.

A RRAM-Based True Random Number Generator with 2T1R Architecture for Hardware Security Applications.

Resistance random access memory (RRAM) based true random number generator (TRNG) has great potential to be applied to hardware security owing to its intrinsic switching variability. Especially the high resistance state (HRS) variation is usually taken as the entropy source of RRAM-based TRNG. However, the small HRS variation of RRAM may be introduced owing to fabrication process fluctuations, which may lead to error bits and be vulnerable to noise interference. In this work, we propose an RRAM-based TRNG with a 2T1R architecture scheme, which can effectively distinguish the resistance values of HRS with an accuracy of 1.5 kΩ. As a result, the error bits can be corrected to a certain extent while the noise is suppressed. Finally, a 2T1R RRAM-based TRNG macro is simulated and verified using the 28 nm CMOS process, which suggests its potential for hardware security applications.

Birds of the Same Feather Flock Together: A Dual-Mode Circuit Candidate for Strong PUF-TRNG Functionalities

Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are two highly useful hardware primitives to build up the root-of-trust for embedded devices in Internet-of-Things and Cyber-Physical System applications. These applications demand the primitives be lightweight, yet flexible. However, PUFs are designed to offer <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">repetitive and instance-specific</i> randomness, whereas TRNGs are expected to be <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">invariably</i> random. A challenging but thought-provoking problem from a hardware designer's perspective would be to design a circuit that serves the purpose of both PUF and TRNG depending on the exact requirement of the application. Here, we present a dual-mode PUF-TRNG design that utilises two different hardware-intrinsic properties, i.e. oscillatory metastability of Transition Effect Ring Oscillator (TERO) cell and propagation delay of a buffer within the cell to achieve this goal. A 48.62% reduction in area is accomplished due to the integration in comparison to separate instances of standalone PUFs/ TRNG designs, built from Programmable Delay Line (PDL) based Arbiter PUFs (APUFs) and TERO-TRNG. Our final design has a hardware footprint of 618 Look-Up Tables (LUTs) and 447 Flip-Flops (FFs). Furthermore, experimental analysis of the state-of-the-art modelling attacks, reliability attacks on the proposed PUF design shows a prediction accuracy of 55.37% and 50.14% respectively for 5.2M Challenge Response Pairs (CRPs). Additionally, the TRNG passes evaluation through National Institute of Standards and Technology (NIST) Special Publication (SP) 800-22 and German Federal Office for Information Security (BSI) Application Notes and Interpretation of the Scheme (AIS)-31 tests.

A 200 kb/s 36 µw True Random Number Generator Based on Dual Oscillators for IOT Security Application

As a module of the internet of things (IOT) information security system, the true random number generator (TRNG) plays an important role in overall performance. In this paper, a low-power TRNG based on dual oscillators is proposed. Two high-frequency cross-coupled oscillators are used to generate high-jitter clock signals, and then the SR latch with power supply below standard power supply voltage is adopted to process the oscillator output to maintain its metastability and increase jitter. The circuit is realized by an SMIC 180 nm 1P6M mixed-signal process. The experimental results show that when power supply voltage is 1.8 V, the circuit outputs a random number bit rate of 200 kb/s, the core area is 0.0039 mm2, and the power consumption is only 36 µw. The output random sequences can pass the NIST SP 800-22 test.

Attack Resilient True Random Number Generators Using Ferroelectric-Enhanced Stochasticity in 2D Transistor.

By harnessing the physically unclonable properties, true random number generators (TRNGs) offer significant promises to alleviate security concerns by generating random bitstreams that are cryptographically secured. However, fundamental challenges remain as conventional hardware often requires complex circuitry design, showing a predictable pattern that is susceptible to machine learning attacks. Here, a low-power self-corrected TRNG is presented by exploiting the stochastic ferroelectric switching and charge trapping in molybdenum disulfide (MoS2 ) ferroelectric field-effect transistors (Fe-FET) based on hafnium oxide complex. The proposed TRNG exhibits enhanced stochastic variability with near-ideal entropy of ≈1.0, Hamming distance of ≈50%, independent autocorrelation function, and reliable endurance cycle against temperature variations. Furthermore, its unpredictable feature is systematically examined by machine learning attacks, namely the predictive regression model and the long-short-term-memory (LSTM) approach, where nondeterministic predictions can be concluded. Moreover, the generated cryptographic keys from the circuitry successfully pass the National Institute of Standards and Technology (NIST) 800-20 statistical test suite. The potential of integrating ferroelectric and 2D materials is highlighted for advanced data encryption, offering a novel alternative to generate truly random numbers.

An Energy Efficient and High Performance Modified Trng based Two Phase Multi Bit Per Cycle Ring Oscillator for IoT Applications

The modified TRNG (true random number generator) is mainly focused due to minimize the power wasted by the superfluous oscillations at higher frequency operations. To boost fan-out condition, random bits are collected from both phases of the slow ROs (Ring oscillators), and the fast RO is only engaged during the brief transition time difference between two slow ROs that are symmetrically built. In order to lower the power consumption of the suggested design, the slow jittery ROs are implemented utilising current starved inverters (CSI) biassed in the weak inversion zone. By decreasing the transistors' drain current and oscillation frequency, their jitter amplitudes are made more pronounced. The quickest three-stage RO quantizes the narrow jittery pulse produced by the differential pair of slow ROs. By counting the number of oscillatory cycles of the quick RO, a gigahertz dynamic toggled D flip-flop counter may be used to extract two random bits from each phase of the jittery ROs. The proposed TRNG is fabricated in a standard 45 nm using 1V supply of CMOS process.