Triode Region Research Articles

A 0.73 mW low power 9.6 GHz LC voltage-controlled oscillator achieves constant KVCO and −189.2 FOM

This article introduces a novel approach of LC voltage-controlled oscillator (VCO) to overcome the challenges present in the Phase-locked loop (PLL) in high-frequency applications and proposes a 9.6 GHz VCO based on gm-boosted structure. By utilizing a transformer and gain variation calibration technique, the proposed VCO reduces the losses caused by MOSFET’s operation in triode region, thereby improving phase noise. And KVCO remains relatively constant, fluctuating up and down by approximately 5 MHz around 100 MHz/V, which is suitable to be used in phase-locked-loops (PLL). The oscillator is fabricated in 22 nm CMOS process occupying 0.25 mm × 0.55 mm area and consuming 0.73 mW from 0.5 V supply voltage. The measured phase noise achieves −114.3 dBc/Hz at 1 MHz offset with a carrier frequency of 4.75 GHz, and the figure of merit (FoM) is −189.2 dBc/Hz. The results clearly demonstrate that the proposed design could work under low power consumption and achieve constant KVCO, making it well suitable for high-frequency PLL applications.

Design and Simulation of VCO for RF Transceivers with Low Power, Low Phase Noise and Wider Tuning Range using Silterra 130nm CMOS Technology

The performance of low-power transceivers is required to meet stringent specifications for an advanced wireless radio frequency (RF) application. The design topology in this paper is simulated to meet the specifications and operation of VCO for low power, low phase noise and wide tuning range in complementary metal oxide semiconductor (CMOS) 130nm technology for RF transceivers. The relationship between the phase noise, power consumption and frequency turning range is fully analyzed to further improve the performance of the voltage-controlled oscillator (VCO). The architecture of the VCO employs two sets of symmetrical cross-couple split NMOS and PMOS with biased current sources operating in the triode region, and a resonator tank that achieves the desired low phase noise performance of about -110 dB/Hz at a tuning range of 4.1 to 4.5 GHz with a supply of 0.9 V. The control of the DC bias point reduces the conduction angle, which improves the current efficiency, power consumption and phase noise. The topology generates sufficient –gm for the oscillator incorporation to mitigate the start-up issue of the VCO. At the center frequency of 4.38 GHz, the VCO serves as a promising solution for improving low power and low phase for wireless communication systems and RF transceiver applications. The design consumes a very low power of 0.138 mW, achieves a phase noise of -110.53 dBc/Hz at 1 MHz offset, and a figure of merit (FoM) of -191.90 dBc/Hz.

Conclusive Model-Fit Current–Voltage Characteristic Curves with Kink Effects

Current–voltage characteristic curves of NFinFET are presented and fitted with modified current–voltage (I-V) formulas, where the modified term in the triode region is demonstrated to be indispensable. In the as-known I-V formula, important parameters need to be determined to make both the measured data and the fitting data as close as possible. These parameters include kN (associated with the sizes of the transistor and mobility), λ (associated with early voltage), and Vth (the threshold voltage). The differences between the measured data and the fitting data vary with the applied source–drain bias, proving that the mobility of the carriers is not consistently constant. On the other hand, a modified formula, called the kink effect factor, is negatively or positively added, simulating solitary heat waves or lattice vibration, which disturb the propagation of carriers and thus influence the source–drain current (IDS). The new statistical standard deviations (δ) are then found to be effectively suppressed as the kink effect is taken into account.

Multi-neuron connection using multi-terminal floating–gate memristor for unsupervised learning

Multi-terminal memristor and memtransistor (MT-MEMs) has successfully performed complex functions of heterosynaptic plasticity in synapse. However, theses MT-MEMs lack the ability to emulate membrane potential of neuron in multiple neuronal connections. Here, we demonstrate multi-neuron connection using a multi-terminal floating-gate memristor (MT-FGMEM). The variable Fermi level (EF) in graphene allows charging and discharging of MT-FGMEM using horizontally distant multiple electrodes. Our MT-FGMEM demonstrates high on/off ratio over 105 at 1000 s retention about ~10,000 times higher than other MT-MEMs. The linear behavior between current (ID) and floating gate potential (VFG) in triode region of MT-FGMEM allows for accurate spike integration at the neuron membrane. The MT-FGMEM fully mimics the temporal and spatial summation of multi-neuron connections based on leaky-integrate-and-fire (LIF) functionality. Our artificial neuron (150 pJ) significantly reduces the energy consumption by 100,000 times compared to conventional neurons based on silicon integrated circuits (11.7 μJ). By integrating neurons and synapses using MT-FGMEMs, a spiking neurosynaptic training and classification of directional lines functioned in visual area one (V1) is successfully emulated based on neuron’s LIF and synapse’s spike-timing-dependent plasticity (STDP) functions. Simulation of unsupervised learning based on our artificial neuron and synapse achieves a learning accuracy of 83.08% on the unlabeled MNIST handwritten dataset.

An area-efficient 1.96 nA 0.55 V 96 ppm/°C self-biased current reference using active resistor temperature coefficient compensation

This paper presents a simple scheme for a nano-ampere supply and temperature-stabilized current reference based on the well-known Beta multiplier circuit. Under the control of the proposed active resistor temperature coefficient compensation (TCC) circuit, the threshold voltage of the traditional active resistor in the triode region can be reduced and the temperature coefficient (TC) can be adjusted. The proposed current reference circuit was implemented using standard VTH (SVT) MOS devices and included active resistors (MΩ) to achieve area efficiency. The power consumption of the current reference generator designed using a 180 nm CMOS process was 9.2 nW at a supply voltage of 0.55 V. Monte-Carlo simulation results showed that the reference current was 1.96nA, temperature coefficient was 96 ppm/°C over a temperature range of 0–100 °C, and line sensitivity was 0.2 %/V for supply voltages ranging from 0.55 to 1.8 V. The active area was only 0.003 mm2.

A 585.9 µW Complementary VCO with an LC Head-and-Tail Filtering Achieving 196.7 dBc/Hz FoM

This paper reports a PMOS-NMOS Complementary LC voltage-biased oscillator with dual-second harmonic filtering tanks. It features 2 LC networks integrated each at the head and tail of the oscillator to concurrently resonate at twice the oscillating frequency (fLO ), forming two high-impedance paths to prevent the PMOS and NMOS –g m differential pairs from loading the main LC resonator when the transistors are driven into the triode region. This improves the voltage and current efficiency of the oscillator. Furthermore, the gate-to-source voltages of the two –g m differential pairs are reshaped to reduce their phase noise contributions. Simulated in 65 nm CMOS, the proposed oscillator with 4.64–5.64 GHz (17.68%) tunability exhibits a power consumption ranging 585.9–655.4 µW while offering a phase noise performance of −139–141.5 dBc/Hz at the 10 MHz offset. The corresponding FoM is 196.2–196.7 dBc/Hz.

Resistor-Less Capacitor-Controlled Single VDIBA-Based Third-Order Quadrature Sinusoidal Oscillator

This paper presents a new voltage-mode (VM) third-order quadrature sinusoidal oscillator (TOQSO) employing a single voltage differencing inverting buffered amplifier (VDIBA) along with three grounded capacitors (GCs) (suitable for IC implementation and also for parasitic absorption) and two NMOS transistors (operated in triode region). The condition of oscillation (CO) and frequency of oscillation (FO) of the presented circuit are self-regulating, i.e. CO can be regulated electronically by transconductance and by varying capacitors, and the FO can be tuned. Non-ideal analysis of the presented TOQSO circuit has been carried out and the results have been compared with ideal ones. Sensitivities of FO with respect to active and passive components have been evaluated and found to be less and also the presented oscillator configuration has low power dissipation and low total harmonic distortions (THD). The feasibility of the presented circuit has been validated using high-performance tunable CMOS VDIBA with a low supply voltage ±0.6 V. Experimental results have also been corroborated using VDIBA, implemented with commercially available ICs MAX435 and AD830.

Analytical model of the drain current in amorphous silicon junction field effect transistors

This paper presents an analytical model of a hydrogenated amorphous silicon (a-Si:H) junction field effect transistor (JFET) based on a p-type/intrinsic/n-type stacked structure. The p-doped layer is connected to the transistor gate electrode, while the n-layer acts as the device channel. The analysis shows the effect of the geometrical and physical parameters of the intrinsic and n-doped layers on the transistor characteristics. In particular, the intrinsic layer thickness plays a central role in determining the depletion region of the n-channel and, as a consequence, the device threshold voltage. The drain current behavior achieved with a modeled parametric analysis is in very good agreement with the experimental drain current measured on fabricated JFET, both in triode and pinch-off regions. This demonstrates the model feasibility as an effective tool to design thin film electronic circuit as a sensor signal amplifier based on a-Si:H p-i-n junction.

An integrated 0.0625–4 GHz quadrature-output fractional-N frequency synthesizer for software-defined radios

This paper presents a compact 0.0625–4 GHz fractional-N frequency synthesizer with quadrature phase output for software-defined radios (SDRs). Four voltage controlled oscillators (VCOs) and six cascaded dividers are used for wideband operation. Second harmonic filtering and high frequency noise suppression techniques are applied in VCO for phase noise optimization. Inverter switch and cascade switch buffers are combined for channel selection enhancement and output amplitude improvement. A large output voltage dynamic range with minimum current variation and mismatch is achieved by enabling transistors to work in triode region in charge pump. Implemented in a 55 nm CMOS process, the synthesizer demonstrates continuous frequency coverage from 62.5 to 4000 MHz with orthogonal output signals greater than 2 dBm while consuming 125 mW of power and provides the phase noise performance of −96.3/-127.7 dBc/Hz at 10 kHz/1 MHz offsets under a 2 GHz carrier. The chip area including all the pads and IOs is 3.34 mm2.

Design and Optimization of 2.1 mW ULP Doherty Power Amplifier with Interstage Capacitances Using 65 nm CMOS Technology

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.

An Improved Large-Signal Equivalent Circuit Model for Partially Depleted Silicon-on-Insulator MOSFET

In this article, a nonlinear capacitance model for a large-signal compact model of partially depleted (PD) silicon-on-insulator (SOI) transistors is proposed. When the transistors are operated in the saturation and triode region, the gate-source capacitance ( C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> ) and the gate-drain capacitance ( C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) change with the gate-source voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) nonlinearly. C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> will emerge a significant compression phenomenon in the triode region. This capacitance model adds a hyperbolic tangent function to the conventional model's function to characterize this phenomenon. Besides, the nonlinear drain current model is obtained on the basis of a unified empirical model. To validate this improved large-signal equivalent circuit model, two different transistors are manufactured in a commercial 180-nm body-contact (BC) PD-SOI process. On-wafer measurement is implemented to obtain the experimental data. Then the calculated results of the model are compared with the measurement data. The relative root-mean-square-error (RRMSE) is less than 6.59% for output power, 9.03% for power-added efficiency (PAE), and 2.72% for the gain respectively.

Topology Variations of an Amplifier-based MOS Analog Neural Network Implementation and Weights Optimization

Neural networks are achieving state-of-the-art performance in many applications, from speech recognition to computer vision. A neuron in a multi-layer network needs to multiply each input by its weight, sum the results and perform an activation function. This paper is an extended version of the article in which we present an implementation of an amplifier-based MOS analog neuron and the optimization of the synaptic weights using in-loop circuit simulations. In addition to the base topology, we present two variations of the original conference paper topology to reduce area and power. MOS transistors operating in the triode region are used as variable resistors to convert the input and weight voltage to proportional input current. To test the analog neuron in full networks, an automatic generator is developed to produce a netlist based on the number of neurons on each layer, inputs, and weights. Simulation results using a CMOS 180 nm technology for all topologies demonstrate the neuron proper transfer function and its functionality while trained in test datasets.

Li memristor-based MOSFET synapse for linear I–V characteristic and processing analog input neuromorphic system

In this research, we propose a method that can significantly improve the linearity of current–voltage characteristics (L–IV) of synapse devices. Considering that analog input data are dependent on the L–IV, synapse devices having non-linear current–voltage characteristics can result in drastic conductance variations during inference operations. It means that the L–IV is one of the key parameters in the synapse device. To improve the L–IV, a triode region of a metal oxide semiconductor field effect transistor (MOSFET) was utilized with a Li-ion-based memristor as a gate voltage divider, which results in gradual channel conductance changes (analog synaptic weights). The channel conductance of the MOSFET can be selectively controlled based on Li-ion intercalation and de-intercalation. A notably improved L–IV and analog synaptic weights were achieved, which enhanced the MNIST data set recognition accuracy from 35.8% to 92.03%.

A 28-GHz High Linearity Up-Conversion Mixer Using Second-Harmonic Injection Technique in 28-nm CMOS Technology

A 28-GHz high linearity active up-conversion mixer using 28-nm CMOS is presented in this letter. To enhance the modulated output power level under high-order modulation with IM3 improvement in the high IF input power region, the second-order intermodulation (IM2) signal injection technique is adopted. The positive third-order intermodulation (IM3) signal is generated by mixing the IM2 signal and IF input signal with transistors in the transconductance stage biasing in triode region. Therefore, by combining these opposite IM3 signal at the output of transconductance stage, the IM3 distortion can be alleviated. Besides, the proposed mixer achieves an IM3 distortion improvement in a wide IF power range. The measurement results demonstrate conversion gain (CG) of −6.4 dB and output 1-dB compression point (OP1 dB) of −2.2 dBm with 19 mW. The two-tone measurement results exhibit 10.2 dBm output third-order intercept point (OIP3). Furthermore, with the modulation measured results using single-carrier 256-QAM signal, the proposed mixer also exhibits a distinguished output power enhancement when the linearizer turns on. To the best of the author’s knowledge, this design is the first demonstration and implemented of an IM2 signal injection technique in millimeter-wave frequency, which also improves the output power level of the high-order modulation measurement.

Low-Voltage CMOS Circuits for Analog VLSI Programmable Neural Networks.(Dept.E)

This paper presents an overview of designing an analog VLSI system used for handwritten recognition; namely a programmable neural network in linear as well as subthreshold CMOS technology. Synaptic weights are designed in the triode region. In addition, the processing element (PE) and the Tanh, activation function are designed in subthreshold region. Such subthreshold CMOS technology has some interesting features, such as high integration density, exponential transfer characteristics and low-power consumption. The proposed system is realized in a standard 0.8um CMOS technology and operated with a ± 1V power supply.

Effects of Tensile Strain on Dynamic and Static Inverters Using Amorphous Indium-Gallium-Zinc-Oxide TFTs

The dynamic inverter using amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) is revealed to be more robust to tensile strain than the static inverter that is most widely used in TFT circuits. The results with the inverters can be reasonably extended to NAND or NOR gates, because all of them are commonly composed of pull-up and pull-down networks. The experimental results after tensile bending up to 20 000 times with a bending radius of 1.5 mm show that AVOH and AVOL in the dynamic inverter decrease to 85% and 0% of those in the static inverter, respectively. Also, while the power consumption of the static inverter increases by 36%, which is tens of μA, the dynamic inverter maintains low-power consumption, which is tens of nA. It is also worth noting that ratioed design and TFT operation in the saturation region make the circuit more sensitive to tensile strain than ratio-less design and TFT operation in the triode region.

A 120 mV Supply, Triode-Regulated Femto-Watt CMOS Voltage Reference Design

This brief presents the design and sizing of a femto-watt voltage reference based on the temperature compensation of N-type and P-type standard transistors. A short-channel dimension transistor working in triode region is added between the source and gate terminals of the traditional self-bias structure, which demonstrates efficient low-power and low-voltage operations. The circuit design was carried out in a 180 nm process. Post-layout simulation results verified the proper circuit operation and produced a reference voltage of 65.7 mV. With a minimum supply voltage of 120 mV, the circuit consumes 252 fW at room temperature, has mean and best temperature coefficients (TCs) of 89.81 ppm/°C and 10.61 ppm/°C, respectively, from -40 to 120°C, and presents a power supply rejection ratio (PSRR) of -61 dB.

Recent Advances on Linear Low-Dropout Regulators

This brief revises the recent design trends of linear low-dropout regulators. The design issues and advantages of analog LDOs (ALDO) are discussed. High-performance operation and high rejection to supply noise when delivering large current values is a major advantage of the ALDO, but transient response when transitioning from standby operation to full load is a major issue; the main limitation is the slow charging/discharging of the large gate's capacitor of the pass transistor. This issue is more critical when designing full-on chip ALDOs, where large load capacitors are not available. Digital LDOs (DLDO) employ digital controllers that drive the segmented pass transistor, in most of the cases operate in triode region. The digital nature of the DLDO scales with the technology, but its rejection to supply noise is limited. Mixed-mode LDOs take advantage of the properties of both ALDO and DLDOs. Transient is managed by the agile DLDO and steady state operation is mainly handled by the clock glitch free ALDO. In this brief, all three architectures are revisited.

Design of a low-noise, high-linearity, readout ASIC for CdZnTe-based gamma-ray spectrometers

The presented work is dedicated to designing a readout ASIC used in CdZnTe-based gamma-ray spectrometers for radionuclide identification. In order to achieve high linearity in a large dynamic range, an active resistor is utilized. Since the active resistor induces high noise, a CR−(RC)2 slow shaper with two different stages is proposed to suppress the noise. The integrating resistors in the first stage are implemented by transistors operating in triode region, while the active resistor is utilized in the second stage. A prototype chip with eight channels has been designed and fabricated in a standard commercial 1P6M 0.18 μm CMOS process. The measured nonlinear error is less than 1% with the input charge ranging from −1.4 fC to −56 fC, owning to the proposed slow shaper. Measured ENC is about 180 e− at input capacitance of 0 F with a slope of 7.7 e−/pF.

Current-Mode Signal Enhancement in the Ion-Selective Field Effect Transistor (ISFET) in the Presence of Drift and Hysteresis

The accuracy of the ion-selctive field effect transistor (ISFET) is limited by errors ascribed to drift and hysteresis. In this work operation of the ISFET as a stand-alone pH sensor operating in the current mode is demonstrated, the dependence of drift on pH is characterized and modeled, and the relationship between drift and hysteresis is investigated. Also, a post-processing method for extraction of the ISFET current signal in the presence of drift and hysteresis is formally developed. This method, which is based on sampling the drain current over relatively short time intervals, is verified experimentally in the presence of drift and hysteresis by monitoring step changes in pH using a Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> -gate ISFET biased in the triode region with the pH of the solution cycled up and down over a seven-unit range. The corrective algorithm was also demonstrated by extracting the measuring signal using an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -gate ISFET operating in the current mode to monitor pH variations ranging from 4 to 10. The theoretical basis of the proposed method is validated by developing the concept of signal-to-drift ratio as a figure of merit for the resolution of pH-sensitive ISFETs. The signal-to-drift ratio is shown to increase in proportion to the ISFET transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) suggesting that the optimization of g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> can improve the resolution of pH readings. SPICE simulations based on the measured drift data for the Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sub> -gate ISFET indicated an approximately 0.1pH unit improvement in the accuracy of the ISFET for a two-fold increase in the aspect ratio of the channel (W/L).