An Improved Large-Signal Equivalent Circuit Model for Partially Depleted Silicon-on-Insulator MOSFET

Abstract

In this article, a nonlinear capacitance model for a large-signal compact model of partially depleted (PD) silicon-on-insulator (SOI) transistors is proposed. When the transistors are operated in the saturation and triode region, the gate-source capacitance ( C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> ) and the gate-drain capacitance ( C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ) change with the gate-source voltage ( V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> ) nonlinearly. C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gs</sub> will emerge a significant compression phenomenon in the triode region. This capacitance model adds a hyperbolic tangent function to the conventional model's function to characterize this phenomenon. Besides, the nonlinear drain current model is obtained on the basis of a unified empirical model. To validate this improved large-signal equivalent circuit model, two different transistors are manufactured in a commercial 180-nm body-contact (BC) PD-SOI process. On-wafer measurement is implemented to obtain the experimental data. Then the calculated results of the model are compared with the measurement data. The relative root-mean-square-error (RRMSE) is less than 6.59% for output power, 9.03% for power-added efficiency (PAE), and 2.72% for the gain respectively.