Abstract
This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.
Highlights
We are living in a modern world where everyone has lesser time to recharge their handy devices along with usage of a larger number of applications including healthcare, smart offices, and homes [1]
Is research simulates the idea of designing an ultra-low power (ULP) power amplifier with 65 nm CMOS technology. e calculations have been shown in a very simple manner, making it easier to understand for a designer
Numerous methods are available in past research studies where equivalent lumped parameters have been designed using bipolar devices, but CMOS designs are still preferred as these are relatively cheap as compared to bipolar transistors [5,6,7]
Summary
We are living in a modern world where everyone has lesser time to recharge their handy devices along with usage of a larger number of applications including healthcare, smart offices, and homes [1]. Both the main amplifier and the peaking amplifier are supposed to load Zo. Various designs have been proposed earlier where both equal and unequal power divider techniques were used to calculate the input impedance of transmission lines. Since the equal power divider model has been implemented for both main and peaking amplifiers.
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