Tri-gate Transistors Research Articles

Decananometer Surrounding Gate Transistor (SGT) Scalability by Using an Intrinsically-Doped Body and Gate Work Function Engineering

This paper shows that the Surrounding Gate Transistor (SGT) can be scaled down to decananometer gate lengths by using an intrinsically-doped body and gate work function engineering. Strong gate controllability is an essential characteristics of the SGT. However, by using an intrinsically-doped body, the SGT can realize a higher carrier mobility and stronger gate controllability of the silicon body. Then, in order to adjust the threshold voltage, it is necessary to adopt gate work function engineering in which a metal or metal silicide gate is used. Using a three-dimensional (3D) device simulator, we analyze the short-channel effects and current characteristics of the SGT. We compare the device characteristics of the SGT to those of the Tri-gate transistor and Double-Gate (DG) MOSFET. When the silicon pillar diameter (or silicon body thickness) is 10nm, the gate length is 20nm, and the oxide thickness is 1 nm, the SGT shows a subthreshold swing of 63 mV/dec and a DIBL of -17 mV, whereas the Tri-gate transistor and the DG MOSFET show a subthreshold swing of 71 mV/dec and 77 mV/dec, respectively, and a DIBL of -47 mV and -75 mV, respectively. By adjusting the value of the gate work function, we define the off current at V G = 0 V and V D = 1V. When the off current is set at 1 pA/μm, the SGT can realize a high on current of 1020μA/μm at V G = 1V and V D = V. Moreover, the on current of the SGT is 21% larger than that of the Tri-gate transistor and 52% larger than that of the DG MOSFET. Therefore, the SGT can be scaled reliably toward the decananometer gate length for high-speed and low-power ULSI.

Influence of crystal orientation and body doping on trigate transistor performance

This work characterizes long channel trigate transistors with respect to the systematic influence of crystal orientation and body doping on performance issues like mobility and V th adjustment. A fin orientation of 〈1 0 0〉 is found favourable for n-channel, 〈1 1 0〉 for p-channel transistors. Experiment shows that body doping is suitable to taylor V th, but low doping levels are preferable to reduce V th variations. The applicability of these long channel results to short-channel transistors down to 20 nm gate length is demonstrated and good performance is obtained.

Quantum Interference in Fully Depleted Tri-Gate Quantum-Wire Transistors—The Role of Inelastic Scattering

Within the next decade, it is predicted that we will reach the limits of silicon scaling as it is currently defined. Of the new devices under investigation, one of the most promising is the tri-gate quantum-wire transistor. In this paper, we study the role quantum interference plays in the operation of this device both in the ballistic and quasi-ballistic regimes. We find that, in the ballistic case, the electrons propagating in the system tend to form vortices in their motion when subjected to moderate drain biases. These vortices form in both the source and drain of the device when the proper conditions are satisfied. Further, we observe fluctuations in the conductance of the device, which leads to fluctuations in resultant drain current due to interactions with the channel and dopant ions. When inelastic scattering is considered, the formation of the vortices is suppressed and the spread in threshold voltage fluctuations is reduced. However, the conductance fluctuations remain in the drain current once the drain voltage reaches larger values.

High performance fully-depleted tri-gate CMOS transistors

Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The transistors show near-ideal subthreshold gradient and excellent DIBL behavior, and have drive current characteristics greater than any non-planar devices reported so far, for correctly-targeted threshold voltages. The tri-gate devices also demonstrate full depletion at silicon body dimensions approximately 1.5 - 2 times greater than either single gate SOI or non-planar double-gate SOI for similar gate lengths, indicating that these devices are easier to fabricate using the conventional fabrication tools. Comparing tri-gate transistors to conventional bulk CMOS device at the same technology node, these non-planar devices are found to be competitive with similarly-sized bulk CMOS transistors. Furthermore, three-dimensional (3-D) simulations of tri-gate transistors with transistor gate lengths down to 30 nm show that the 30 nm tri-gate device remains fully depleted, with near-ideal subthreshold swing and excellent short channel characteristics, suggesting that the tri-gate transistor could pose a viable alternative to bulk transistors in the near future.

TRACE—traceability and reliability assuring computerized environment : Koji Ohtoriet al. Proceedings of the 21st Symposium on Reliability and Maintainability, Japan, 25 (June 1991)

At short gate lengths, narrow multiple-gate FETs (MuGFETs) are known to offer superior short channel effect (SCE) control than their bulk Si counterpart [Doyle BS et al. High performance fully-depleted tri-gate CMOS transistors. IEEE Electron Dev Lett 2003;24(4):263–5, van Dal MJH et al. Highly manufacturable FinFETs with sub-10 nm fin width and high aspect ratio fabricated with immersion lithography. In: VLSI Symp Tech Dig; 2007. p. 110–1 [1], [2]]. In addition, their undoped channels allow a substantial reduction of the threshold voltage (VT) mismatch, which makes the MuGFET an excellent candidate for replacing planar MOSFETs in SRAM structures. However, as the Si fin width (Wfin) and gate length (Lg) are down-scaled in order to improve the SCE control and current drive, respectively, the gate work function and access resistance (RSD) engineering become more challenging.In this paper, two approaches for optimizing the performance of narrow MuGFETs are reported and analysed: the first one relies on the thickness of their Plasma-Enhanced-ALD (PE-ALD) TiN gate electrode. It is demonstrated that very thin PE-ALD TiN gate electrodes allow improved SCE control and enhanced performance in nMOS MuGFETs. The second approach relies on non-amorphizing ion (boron) implantations for both extension and HDD implantations. A substantial RSD reduction is demonstrated for pMOS MuGFETs with Si fin widths down to 10 nm.