Trench Power MOSFET Research Articles

A novel high-performance junctionless 4H-SiC trench MOSFET with improved switching characteristics

A high-performance novel 4H-SiC trench power MOSFET employing the junctionless concept is proposed in this work. The presented design is modeled and investigated numerically by Devedit and Atlas TCAD tools, where the advantages of the junctionless concept are used to maximize the performance of the trench structure. This new structure helps lowering the input and reverse transfer capacitances of the trench power MOSFET compared to the conventional structures. The proposed device shows a lower high frequency (HF) Figure of Merits (FoM) value of 1078 mΩ.pF as compared to the conventional counterpart (4600 mΩ.pF), with a relative improvement of 76.5%. Moreover, a superior agreement between the breakdown voltage and the specific on-resistance has been revealed by a higher FoM (BV2/Ron = 2580 MV/mΩ.cm−2) in comparison to the conventional power MOSFET (860 MV/mΩ.cm−2). In addition, the proposed design proves to support a higher critical electric field at the gate edge (E = 3.93 MV/cm) in comparison to that of its conventional counterpart (E = 3.7 MV/cm). The substantial outcomes of this study pairing improvements in switching, blocking and conducting electrical performances, forcefully suggest this cost-effective design as a potential candidate in developing low-cost and high-performance 4H-SiC power MOSFETS.

Strain Engineering in Si Split-Gate Trench Power MOSFETs by Partial Oxidation of Polysilicon Electrodes

Performance improvement of Si split-gate trench power MOSFETs due to conventional scaling is approaching a physical and economical limit. Strain engineering, however, enables enhanced device characteristics without the need for further shrinkage as a result of an increased charge carrier mobility in monocrystalline Si. In this work, thermally grown SiO <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathbf {2}}$ </tex-math></inline-formula> functional strain layers are introduced into a state-of-the-art Si trench power MOSFET by partial oxidation of the source and gate electrode. The influence of the additional SiO2 layers on the strain distribution in monocrystalline Si is described by the thermomechanical (TM) strain simulation and the resulting device properties are assessed by means of detailed electrical analysis. For the strain-modified devices, the simulation shows higher longitudinal tensile strains in the direction of current flow and stronger out-of-plane compressive strains perpendicular to it, which have a beneficial effect on the electron mobility. The electrical characterization revealed improved ON-state resistances at gate voltages of 4.5 V ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ON}4.5$ </tex-math></inline-formula> ) and 10 V ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ON}10$ </tex-math></inline-formula> ) of up to 16.8% and 13.8%, respectively, while the breakdown voltage did not change. In the presence of the SiO2 layer in the gate electrode, the threshold voltage was reduced, which also contributed to the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{ON}$ </tex-math></inline-formula> improvement. The functional strain layer in the gate electrode mainly influences the mobility in the channel, while it primarily alters the mobility in the drift region when introduced into the source electrode. However, the modification of mechanical strain in the channel area shows less impact on the overall device performance compared to the drift region.

Improving dynamic performance for split-gate trench power MOSFETs using variable vertical doping profile

In this paper, a split-gate trench power MOSFET (SGT) with a variable vertical doped (VVD) drift region is proposed. The VVD SGT MOSFET features ultra-low gate-drain charge (QGD) and low switching losses. Due to the introduction of variable vertical doping, the concentration of the drift region near the source is relatively low. The depletion layer outside the trench of the new structure widens towards the drain during depletion spreading, effectively reducing the depletion layer capacitance and thus greatly reducing the gate-drain capacitance (CGD). The significant reduction of QGD and total switching losses is confirmed by simulation. Compared with the conventional split-gate trench MOSFET, the dynamic figure of merit RON × QGD = 22.60 mΩ nC and turn-off loss of the proposed VVD SGT MOSFET are reduced by 42% and 37%, respectively. Moreover, the proposed structure also demonstrates an improvement in the reverse recovery performance.

Nanobeam electron diffraction strain mapping in monocrystalline silicon of modern trench power MOSFETs

Despite a decisive influence of residual strains in Si on its electronic properties and mechanical stability, strain distributions in vertical power transistors are still not fully investigated and understood. In this work, transmission electron microscopy (TEM) nanobeam electron diffraction (NBED) and finite element (FE) modeling were applied to reveal cross-sectional residual strain distributions in monocrystalline Si of a modern trench power MOSFET. Scanning NBED was realized in a region of interest with lateral and vertical dimensions of 0.69 μm and 1.38 μm, respectively, with a spatial resolution of 5.4 nm and a high precision better than 0.05%. The acquired results are interpreted in terms of device structure as well as process flow and are compared with the FE simulation. Complex strain distributions for the vertical, lateral and shear strain components are shown, which are not only dependent on structure and geometry but also influenced by the doping profile in Si. The comparison with the FE strain simulation shows good agreement especially for the vertical and shear strain components. However, it also reveals a limitation of the FE strain simulation with regard to the influence of doping on the Si lattice strain.

Comprehensive Investigation on Electrical Properties of Split-Gate Trench Power MOSFETs Under Mechanical Strains

In this article, we have comprehensively investigated the electrical properties of split-gate trench (SGT) power MOSFETs under mechanical strains. The static and dynamic electrical properties of SGT power MOSFETs under both uniaxial and biaxial strains are examined thoroughly. It is found that both uniaxial and biaxial compressive strains improve the drain current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{d}$ </tex-math></inline-formula> ), while uniaxial and biaxial tensile strains do the opposite. The influence of strain is correlated with drain voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{d}$ </tex-math></inline-formula> ), and biaxial strains are slightly more effective than uniaxial strains. The mechanical strains do not change the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\mathrm {th}}}$ </tex-math></inline-formula> ), breakdown voltage (BV), capacitances, and switching characteristics. The piezoresistance coefficients of the SGT power MOSFETs are evaluated. It is also proved that both biaxial and uniaxial compressive strains can effectively decrease the figure-of-merit (FOM) of SGT power MOSFETs.

New Process Integration of Sequential Phosphorus-Doped Silicon for Trench Field Plate Power MOSFETs

In advanced field plate trench power MOSFETs (FP-MOSFETs), narrow and deep trench causes lots of challenges for process integration. Especially, process optimization for silicon in trench is the most crucial. Sequential phosphorus doping process is expected to form decent silicon electrodes in narrow and deep trenches. Therefore, we studied new process optimization of FP-MOSFETs with sequential phosphorus-doped silicon method, compared with “conventional” phosphorus diffusion method. We succeeded in reducing processing variations in field plates and decreasing wafer warpage by processing phosphorus-doped silicon without activation annealing. Inserting 800 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C annealing before 1000 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C annealing contributed no voids in silicon field plates and gates. In addition, good electrical characteristics was demonstrated with the optimized process.

High Temperature Reverse Bias (HTRB) &amp; Temperature Humidity Bias (THB) Reliability Failure Mechanisms and Improvements in Trench Power MOSFET and IGBT

High Temperature Reverse Bias (HTRB) reliability failure is found to be caused by huge amount of undesirable hydrogen proton (H+) ions from packaging resin or external environment, while Temperature Humidity Bias (THB) reliability failure is known to be caused by moisture accumulation. A commonly known method of improving HTRB is by increasing phosphorus concentration in the PMD layer to enhance device gettering capability against H+. However, this is usually achieved at the expense of THB reliability as excessive phosphorus on the PMD surface gives rise to moisture accumulation and caused THB failure. In this paper, we performed a series of experiments to uncover two elements in PMD that are responsible to getter H+, which are Phosphorus-Oxygen-Hole-Center (POHC) and dangling bonds. We also discussed 2 possible ways to boost these H+ gettering elements to improve HTRB reliability without the adverse impact on THB reliability: Utilization of Plasma Enhanced Chemical Vapor Deposition (PECVD) Phospho-Tetraethyl-Orthosilicate (PTEOS) in PMD layer to replace the commonly used Atmospheric Pressure Chemical Vapor Deposition (APCVD) or Sub Atmospheric Chemical Vapor Deposition (SACVD) Boro-Phospho-Tetraethyl-Orthosilicate (BPTEOS) and the introduction of Tetraethyl-Orthosilicate (TEOS) capping layer on PMD layer. Both methods have proven to greatly alleviate HTRB and THB reliability marginality problems.

On-Resistance Limit Estimation of 100 V-class Field-Plate Trench Power MOSFETs Optimized Oxide Thickness

The on-resistance limit of 100 V-class Field-Plate (FP) trench power MOSFETs was analyzed by TCAD simulation. In the previous works, the lateral pitch narrowing effect to reduce the on-resistance has been studied from the viewpoint of charge compensate concept. This work focused on optimization of FP oxide thickness, which affects both the breakdown voltage and the stress induced electron mobility enhancement. The simulation results show that thin oxide structure is desired for low on-resistance design due to lateral pitch narrowing, although thick oxide enhances the increase of the electron mobility. However, the on-resistance reduction by lateral pitch narrowing is limited by increase of the drift layer thickness for maintain the breakdown voltage. As a limit value, the on-resistance of 24.7 $\text{m}\Omega \cdot $ mm2 at the breakdown voltage of 114 V was estimated and corresponds to 13%-24% improvement of Figure-of-Merit, which is VB2.5/Ron, compared with the previous works of two step and multiple step oxide structures.

High performance selective buried double gate power MOSFET

In this letter, we propose a dual laterally aligned poly-silicon selective buried gates power MOSFET (SBGP-MOSFET). The proposed structure significantly improves the ON resistance (Ron)-breakdown voltage tradeoff, reduces gate-drain capacitance (CGD) and eliminates the formation of parasitic n–p–n transistor in comparison to the conventional vertical trench power MOSFET. The two buried gates provide a large separation between the gate and drain thus reduces the gate-drain coupling, gate-drain capacitance (Cgd) and switching losses. A two dimensional simulation study shows that the proposed SBGP-MOSFET achieves a significant reduction in ON resistance, 48.33% reduction in Qgd and ∼13% increase in the breakdown voltage in comparison to the conventional device.

Charge Pumping of Low-Voltage Silicon Trench Powers MOSFETs

Interface- and border-traps at the Si-SiO2 interface are investigated in trench power MOSFETs. We show that the popular charge pumping method is not limited to conventional lateral devices but can also be applied to these more complex structures. A new approach for the localization of defects is presented, using devices with two or more differently doped areas adjacent to the Si-SiO2 interface. Based on those doping profile variations, different areas of the interface can be assigned to particular intervals of the measured charge pumping signal. By varying the geometrical aspect ratios and the areas of the investigated devices, we demonstrate that the interface- and border-trap density on the edges of the structures is significantly higher than in the active area. Finally, challenges arising in the measurement setup are discussed.

A novel fabrication of TDMOSFETs using two-step trench etching and twice self-alignment technique

ABSTRACTA new fabrication method employing two-step trench etching and twice self-alignment technique was developed to obtain high cell density trench power MOSFETs by using only three mask steps. This method was implemented to increase cell density, to decrease on-resistance and to improve leakage current characteristics. The trench DMOSFETs with 1.6 μm cell pitch and 140 Mcell/in2 cell density were fabricated. The specific on-resistance of the device is about 0.48 mΩ˖cm2 with the breakdown voltage of 43 V.

Shielded Gate SiC Trench Power MOSFET with Ultra-Low Switching Loss

A shielded gate trench silicon carbide (SiC) metal oxide semiconductor field effect transistor (SG-TMOS) is proposed and investigated by simulation in this paper. The impact of shielded gate design in SG-TMOS on Miller charge (Qgd) as well as conduction resistance (Ron) are comprehensively discussed, showing a tradeoff between Qgd and Ron. Furthermore, the Huang’s Figure of Merit (HFOM) of the SG-TMOS with reasonable design of SG is reduced more than 20%, compared with the conventional trench MOSFET (C-TMOS). Therefore, the proposed SG-TMOS is a competitive next generation device structure for ultra-high switching speed SiC MOSFET.

The Trench Power MOSFET—Part II: Application Specific VDMOS, LDMOS, Packaging, and Reliability

The technological development of application specific VDMOS and lateral trench power MOSFETs is described. Unlike general-purpose trench vertical DMOS, application specific trench DMOS comprise devices merged or optimized for a specific function or characteristic. Examples include the bidirectional lithium ion battery disconnect switch, the airbag squib driver with safety redundancy, the antilock breaking systems solenoid driver with repeated avalanche operation, and various forms of synchronous rectifiers (including integrated Schottky and pseudo-Schottky operation). Trench lateral DMOS include all implant quasi-vertical, lateral trench, and lateral trench charge balanced devices. Trench power MOSFET packaging addresses multichip surface mount, DrMOS, low inductance, and clip lead packages.

The Trench Power MOSFET: Part I—History, Technology, and Prospects

The historical and technological development of the ubiquitous trench power MOSFET (or vertical trench VDMOS) is described. Overcoming the deficiencies of VMOS and planar VDMOS, trench VDMOS innovations include pioneering efforts in reactive ion etching and oxidation of the silicon trench gate, polysilicon fill and recessed etchback, unit cell and distributed voltage clamping to protect the trench gate, and scaling active cells to high densities using deep submicron fabrication. Thereafter, gate–drain engineered trench VDMOS improved high-frequency switching capability with lower gate charge utilizing nonuniform gate oxides, field shaping, and charge balancing (superjunction, RSO) methods. The recent adaptation of trench gates in wide bandgap unipolar devices is also described.

Detailed Study on Dynamic Characteristics of a High-Performance SGT-MOSFET With Under-the-Trench Floating P-Pillar

We proposed a 150 V shielded-gate trench (SGT) power MOSFET with floating P-pillars under the trench and studied its static and dynamic characteristics, especially the transient capacitance and dynamic ${\mathrm {R}}_{{\mathrm {ds}}({\mathrm {on}})}$ at high switching frequency. TCAD simulation demonstrated over 33% ${\mathrm {R}}_{{\mathrm {ds}}({\mathrm {on}})}$ reduction compared with regular SGT-MOSFET. Up to MHz switching frequency, simulation indicates almost no ${\mathrm {R}}_{{\mathrm {ds}}({\mathrm {on}})}$ increase in this device, meaning negligible dynamic ${\mathrm {R}}_{{\mathrm {ds}}({\mathrm {on}})}$ penalty. On the other hand, elevated ${\mathrm {C}}_{{\mathrm {oss}}}$ is observed within a particular ${\mathrm {V}}_{{\mathrm {ds}}}$ range (40–90 V) as switching frequency increases, which translates to $\text{Q}_{{\mathrm {oss}}}$ penalty. We investigated the underlying physical process for this ${\mathrm {Q}}_{{\mathrm {oss}}}$ change, and attributed it to the hole pilings in the undepleted region of the P-pillar. The overall parameters of this device, including ${\mathrm {R}}_{{\mathrm {ds}}({\mathrm {on}})}$ and ${\mathrm {R}}_{{\mathrm {ds}}({\mathrm {on}})} \ast {\mathrm {Q}}_{{\mathrm {oss}}}$ , are superior to regular SGT-MOSFET and are close to superjunction MOSFET, which is more expensive and challenging in manufacturing. Although a 150 V MOSFET is used as our study vehicle, the analyses and conclusions apply to any power devices that employ the proposed device architecture.

Optimal Design of Trench Power MOSFET for Mobile Application

This research analyzed the electrical characteristics of an 80 V optimal trench power MOSFET (metal oxide field effect transistor) for mobile applications. The power MOSFET is a fast switching device in fields with low voltage(<100 V) such as mobile application. Moreover, the power MOSFET is a major carrier device that is not minor carrier accumulation when the device is turned off. We performed process and device simulation using TCAD tools such as MEDICI and TSUPREM. The electrical characteristics of the proposed trench gate power MOSFET such as breakdown voltage and on resistance were compared with those of the conventional power MOSFET. Consequently, we obtained breakdown voltage of 100 V and low on resistance of 130 mΩ. The proposed power MOSFET will be used as a switch in batteries of mobile phones and note books.

Modeling and Simulation of Power MOSFET Using Orcad-Pspice

This paper provides a macromodel in Pspice (Personal Simulation Program with Integrated Circuit Emphasis) for a trench power MOSFET rated at 70V over a temperature range of -55°C to 175°C. The Pspice macromodel was built using device parameters extracted through experiment. The static behavior of the trench power MOSFET is simulated and compared to the measured data to show the accuracy of the Pspice model. The temperature dependent behavior was simulated and analyzed.

A methodology for projecting SiO2 thick gate oxide reliability on trench power MOSFETs and its application on MOSFETs VGS rating

In this work, a methodology based on the E-model for the reliability projection of a thick (>20nm) SiO2 gate oxide on a vertical trench power MOSFET, is presented. Experimental results suggest that a Logic Level (LL) trench MOSFET with 35nm of gate oxide can be rated at VGS=+12V if one assumes continuous DC Gate-Source bias of VGS=+12V at T=175°C for 10years at a defect level of 1 Part Per Million (PPM). We will demonstrate that if we take into account MOSFET device lifetime as dictated by the Automotive Electronics Council (AEC Q101) mission profile, then devices can be rated higher to VGS=+14.7V at T=175°C for the same PPM level (1PPM). The application of the methodology for establishing the oxide thickness, tox, for any required voltage rating, is discussed.

A low specific on-resistance power trench MOSFET with a buried-interface-drain

A novel trench power MOSFET with a buried-interface-drain (BID MOSFET) is proposed in this paper. The drain n+ region of BID MOSFET extends to the surface of p− substrate and is buried along the interface of the substrate–layer and epitaxy-layer, which shortens the motion-path in the high-resistance n− drift region for the carriers, and therefore, exhibits a lower specific on-resistance (Ron,sp) and a higher figure-of-merit. The influences of structure parameters on the device performances are investigated. An ultralow Ron,sp of 0.85mΩcm2 is obtained with a breakdown voltage (VB) of 133V. BID MOSFET is compared with several previous-proposed trench MOSFETs, and a significantly optimized dependence of Ron,sp on VB is obtained.

Charge deposition model for investigating SE-microdose effect in trench power MOSFETs

It was demonstrated that heavy ions can induce large current—voltage (I–V) characteristics shift in commercial trench power MOSFETs, named single event microdose effect (SE-microdose effect). A model is presented to describe this effect. This model calculates the charge deposition by a single heavy ion hitting oxide and the subsequent charge transport under an electric field. Holes deposited at the SiO2/Si interface by a Xe ion are calculated by using this model. The calculated results were then used in Sentaurus TCAD software to simulate a trench power MOSFET's I–V curve shift after a Xe ion has hit it. The simulation results are consistent with the related experiment's data. In the end, several factors which affect the SE-microdose effect in trench power MOSFETs are investigated by using this model.