Abstract
In advanced field plate trench power MOSFETs (FP-MOSFETs), narrow and deep trench causes lots of challenges for process integration. Especially, process optimization for silicon in trench is the most crucial. Sequential phosphorus doping process is expected to form decent silicon electrodes in narrow and deep trenches. Therefore, we studied new process optimization of FP-MOSFETs with sequential phosphorus-doped silicon method, compared with “conventional” phosphorus diffusion method. We succeeded in reducing processing variations in field plates and decreasing wafer warpage by processing phosphorus-doped silicon without activation annealing. Inserting 800 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C annealing before 1000 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C annealing contributed no voids in silicon field plates and gates. In addition, good electrical characteristics was demonstrated with the optimized process.
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