High performance selective buried double gate power MOSFET

Abstract

In this letter, we propose a dual laterally aligned poly-silicon selective buried gates power MOSFET (SBGP-MOSFET). The proposed structure significantly improves the ON resistance (Ron)-breakdown voltage tradeoff, reduces gate-drain capacitance (CGD) and eliminates the formation of parasitic n–p–n transistor in comparison to the conventional vertical trench power MOSFET. The two buried gates provide a large separation between the gate and drain thus reduces the gate-drain coupling, gate-drain capacitance (Cgd) and switching losses. A two dimensional simulation study shows that the proposed SBGP-MOSFET achieves a significant reduction in ON resistance, 48.33% reduction in Qgd and ∼13% increase in the breakdown voltage in comparison to the conventional device.