Vertical MOSFET with buried gate

Abstract

The authors are investigating an SPE method, using the low-pressure chemical vapor deposition (LPCVD) system, that is utilized in ordinary Si LSI processes. A vertical MOSFET with a unique structure was devised by applying this method. The device assumes a vertical power MOSFET and features in the buried gate. By driving the buried gate in parallel with the ordinary gate, the drain current is increased. This is due to two effects. First, the effect of the channel formed by the buried gate. Second, the effect of the storage layer formed in the low-density n region below the buried gate, which attracts the drain current uniformly. A lateral SOI MOSFET is constructed and is evaluated on the same Si substrate as the vertical MOSFET. The purpose is to evaluate the circuit elements for an intelligent power MOS. The MOS operation is verified for both nMOS and pMOS. The off-state leak current is less than 2 × 10−12 A. © 1998 Scripta Technica. Electron Comm Jpn Pt 2, 80(9): 19–25, 1997