Trench Gate MOSFET Research Articles

High temperature bias-stress-induced instability in power trench-gated MOSFETs

We report on the high-temperature reverse-bias (HTRB) stress reliability of trench-gated n-channel metal-oxide-silicon field-effect transistors (n-UMOSFETs). The degradation induced by the HTRB is examined using changes in transistor parameters, optical microscopy, and scanning electron microscopy. The HTRB causes degradations in the threshold voltage and drain leakage of the n-UMOSFET and these degradations are particularly large when the stress is applied in a humid ambient. The observations were interpreted in terms of water molecule diffusion into the gate oxide through passivation cracks in the edge termination of the n-UMOSFET during HTRB in a humid ambient. The water molecules catalyze proton (H+) generation through electric-field assisted interactions and hole injection into the gate oxide at the bottom of the trench. Also, H+ is observed to be very stable in the gate oxide and to migrate between the gate-oxide and oxide–Si interfaces driven by an applied gate-voltage. It is proposed that the employed HTRB configuration and level give rise to negative-bias temperature instability (NBTI) in a parasitic p-channel MOSFET structure occurring in the trench base of the n-UMOSFET, and that NBTI is a serious reliability concern in power UMOSFETs subjected to stress in a moist ambient.

Performance evaluation of a lateral trench-gate power MOSFET on InGaAs

In this paper, an integrable lateral trench-gate metal-oxide-semiconductor (LTGMOS), a power MOSFET on In0.53Ga0.47As is presented. The device consists of two separate trenches built in the drift region in which two gates are placed on both sides of the P-body region. The trench-gate structure not only enhances the drain current due to parallel conduction of two channels but also causes the reduced-surface-field effect in the device resulting significant improvement in the device performance. Two-dimensional numerical simulations have been performed to analyse and compare the performance of the proposed device with that of the conventional lateral MOSFET. The LTGMOS provides 2.3 times higher output current, 29 % decrease in threshold voltage, 42 % reduction in on-resistance, 47 % improvement in peak transconductance, two times higher breakdown voltage, and 5.8 times improvement in the figure-of-merit over the conventional device for the same cell pitch.

Fabrication of Superjunction Trench Gate Power MOSFETs Using BSG-Doped Deep Trench of p-Pillar

In this paper, we propose a superjunction trench gate MOSFET (SJ TGMOSFET) fabricated through a simple p pillar forming process using deep trench and boron silicate glass doping process technology to reduce the process complexity. Throughout the various boron doping experiments, as well as the process simulations, we optimize the process conditions related with the p pillar depth, lateral boron doping concentration, and diffusion temperature. Compared with a conventional TGMOSFET, the potential of the SJ TGMOSFET is more uniformly distributed and widely spread in the bulk region of the n drift layer due to the trenched p-pillar. The measured breakdown voltage of the SJ TGMOSFET is at least 28% more than that of a conventional device.

Single-Event Burnout Hardening of Power UMOSFETs With Optimized Structure

This paper gives and explains the simulation results of single-event burnout (SEB) hardening in a power metal-oxide semiconductor field-effect transistor U-Shape Metal Oxide Semiconductor Field Effect Transistor (trench-gate MOSFET). It includes p+ plug enlargement and adds a buffer layer that is between the epitaxial layer and substrate. These two hardening solutions are compared and the optimized structure that can prevent SEB is given. The single event gate-rupture (SEGR) threshold voltages in different linear energy transfers are also compared with SEB results. In addition, the simulation results show that the change of gate bias can influence the occurrence of SEGR, and the natural radiation environment at cryogenic temperatures is also considered.

Research of Single-Event Burnout in Power UMOSFETs

This brief presents 2-D numerical simulation results of single-event burnout (SEB) in power UMOSFETs (trench-gate MOSFET) and investigates hardening solutions to SEB such as carrier lifetime reduction, emitter doping decrease, and p+ plug modification. We find that the linear energy transfer (LET) does not have an important influence on the occurrence of SEB. In addition, we present the effect of a varied ion strike position, and the result is that the position in the middle of the neck is easier to SEB than the other positions. In addition, the single-event gate rupture (SEGR) threshold voltages in different LETs are given in order to compare with SEB.

New trench gate power MOSFET with high breakdown voltage and reduced on-resistance using a SiGe zone in drift region

High breakdown voltage and reduced on-resistance are desired characteristics in power MOSFETs. In order to obtain an excellent performance of Trench Gate Power MOSFET, we have proposed a new structure in which a SiGe zone is incorporated in the drift region to reduce on-resistance. Also, the buried oxide is considered in the drift region that surrounds the SiGe zone to increase breakdown voltage. The proposed structure is called a SiGe Zone Trench Gate MOSFET (SZ-TG). Our simulation with two dimensional simulator shows that by reducing an electric field and controlling the effects of parasitic BJT transistor in the SZ-TG structure, we can expand power applications of trench gate power structures.

Polysilicon Spacer Gate Technique to Reduce Gate Charge of a Trench Power MOSFET

We propose a new trench gate power MOSFET with poly-Si spacers formed in the trench to work as gate material. This approach reduces the total gate charge and gate-to-drain capacitive coupling without affecting any other device performance parameter. Using 2-D numerical simulation on a ~25-V trench gate MOSFET, we have shown that using a 50-nm-wide spacer gate in a 1×1 μm trench may give >; 40% reduction in the gate-to-drain charge compared with the conventional device. The proposed technique has been shown to be better than the other techniques proposed earlier for reducing gate charge as it does not affect the gate control of the accumulation region charge or any other performance parameter, e.g., breakdown voltage, and can be implemented along with any of the existing techniques.

A new shallow trench and planar gate MOSFET structure based on VDMOS technology

This paper proposes a new shallow trench and planar gate MOSFET (TPMOS) structure based on VDMOS technology, in which the shallow trench is located at the center of the n− drift region between the cells under a planar polysilicon gate. Compared with the conventional VDMOS, the proposed TPMOS device not only improves obviously the trade-off relation between on-resistance and breakdown voltage, and reduces the dependence of on-resistance and breakdown voltage on gate length, but also the manufacture process is compatible with that of the VDMOS without a shallow trench, thus the proposed TPMOS can offer more freedom in device design and fabrication.

Comparative study of the static and switching characteristics of SiC and Si MOSFETs

SiC power devices with low loss and fast switching capability have been developing. This study experimentally characterizes trench gate and planar gate SiC MOSFETs, and discusses the difference to conventional Si MOSFET in terms of static and dynamic performance. First, the static current-voltage (I-V) characteristics are evaluated to assess conduction loss. Next, the bias voltage dependencies of terminal capacitance (C-V) are characterized to clarify differences stemming from device configuration. Turn-off switchings for non-inductive resistive loads are examined, and the result are evaluated by associating measured C-V characteristics.

Reliability of planar, Super-Junction and trench low voltage power MOSFETs

A strong demand of even more compact and reliable devices has powered in the last years the development of advanced power MOSFET structures. Among them, the planar STripFET™ has been introduced as an alternative to conventional trench gate MOSFET in low voltage (<60 V) applications. Moreover low voltage Super-Junction devices are also under development. In this paper a conventional trench gate MOSFET is compared in terms of reliability with a STripFET™ and a Super-Junction device. The comparison is accomplished through a reliability model taking advantage from a dynamic analysis of the temperature distribution over the metal source surface in an effort to correlate electric working conditions to thermo-mechanical stresses.

Improvement of Ron under AC Operation of Floating Island and Thick Bottom Oxide Trench Gate MOSFET (FITMOS)

A MOSFET structure called a FITMOS (Floating Island and Thick Bottom Oxide Trench Gate MOSFET) that exhibits a record low loss in the 60V breakdown voltage (BVdss) range has been successfully developed. The following improvements achieved progress in the characteristic of FITMOS. (1) At the time of AC operation, the charges in the floating P islands that are a feature of the floating type device become greater, thereby increasing the on-resistance (Ron) due to the JFET effect. This issue was solved by forming passive hole gates in the end walls of the trenches. The Ron under AC operation is equivalent to the Ron under DC operation. This paper clarified the influence of the passive hole gate diffusion layer shape and the impurity concentration to BVdss and AC operation. (2) The trade-off of BVdss and Ron has been improved by making the floating island into an elliptical form. A BVdss of 83V and a specific on-resistance (RonA) of 36mΩmm2 were obtained.

Improvement of AC characteristics of FITMOS

The AC characteristics of a FITMOS (Floating Island and Thick bottom oxide trench gate MOSfet) with passive hole gate structures are investigated under limiting conditions of high voltage, high temperature and long trench length. The origin of time delay in the switching operation is discussed based on the experimental results and new device structures applicable to the high voltage and high temperature operation are proposed. No additional switching delay is observed in the new structure. Furthermore, degradation in the drain-source breakdown characteristic, as well as the characteristics for the unclamped inductive switch test, is observed.

A New Buried-Oxide-In-Drift-Region Trench MOSFET With Improved Breakdown Voltage

In this letter, we propose a new trench-gate power MOSFET with buried oxide in its drift region that shows an improvement in the breakdown performance as compared to the conventional trench device due to a reduction in the vertical electric field. In addition, the proposed device shows about linear relation between the BV and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> as compared to the 2.5th power relation in the conventional device.

A Stepped Oxide Hetero-Material Gate Trench Power MOSFET for Improved Performance

In this brief, we propose a new stepped oxide hetero-material trench power MOSFET with three sections in the trench gate (an N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> poly gate sandwiched between two P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> poly gates) and having different gate oxide thicknesses (increasing from source side to drain side). The different gate oxide thickness serves the purpose of simultaneously achieving the following: 1) a good gate control on the channel charge and 2) a lesser gate-to-drain capacitance. As a result, we obtain higher transconductance as well as reduced switching delays, making the proposed device suitable for both RF amplification and high-speed switching applications. In addition, the sandwiched gate with different work-function gate materials modifies the electric field profile in the channel, resulting in an improved breakdown voltage. By using 2-D simulations, we have shown that the proposed device structure exhibits about 32% enhancement in breakdown voltage, 25% reduction in switching delays, 20% enhancement in peak transconductance, and 10% reduction in figure of merit (product of ON-resistance and gate charge) as compared to the conventional trench-gate MOSFET.

Investigation of Power MOSFET with Strained SiGe Channel

Two trench-gated power MOSFETs using strained SiGe channel are proposed to further reduce specific on-state resistance. The first is a multiple SiGe and Si layer structure for N-channel MOSFET. A 30nm Si0.85Ge0.15 layer and a 50nm Silicon layer are grown by RPCVD alternatively to achieve sufficient channel length which is longer than critical thickness before the trench etches. The second method is to form the strained SiGe layer along the trench sidewall for P-channel MOSFET. A single Si0.85Ge0.15 layer of 30nm thick is grown after the trench etches. It is expected that the channel mobility in the vertical direction will be increased by up to 40% and 60% for electrons and holes respectively compared to conventional silicon device with same structure and doping profile. The on-state resistance is predicted to be reduced by 12% and 20% for N-channel and P-channel MOSFET accordingly.

A New Strained-Silicon Channel Trench-Gate Power MOSFET: Design and Analysis

In this brief, we propose a new trench power MOSFET with strained-Si channel that provides lower on-resistance than the conventional trench MOSFET. Using a 20% Ge mole fraction in the Si1- Gex body with a compositionally graded Si1 - xGex buffer in the drift region enables us to create strain in the channel along with graded strain in the accumulation region. As a result, the proposed structure exhibits 40% enhancement in current drivability,28% reduction in the on-resistance, and 72% improvement in peak transconductance at the cost of only 12% reduction in the breakdown voltage when compared to the conventional trench-gate MOSFET. Furthermore, the graded strained accumulation region supports the confinement of carriers near the trench sidewalls, improving the field distribution in the mesa structure useful for a better damage immunity during inductive switching.

Normally-off 4H-SiC trench-gate MOSFETs with high mobility

A new 4H-SiC trench-gate MOSFET structure with epitaxial buried channel for accumulation-mode operation, has been designed and fabricated, aiming at improving channel electron mobility. Coupled with improved fabrication processes, the MOSFET structure eliminates the need of high dose N+ source implantation. High dose N+ implantation requires high-temperature (⩾1550°C) activation annealing and tends to cause substantial surface roughness, which degrades MOSFET threshold voltage stability and gate oxide reliability. The buried channel is implemented without epitaxial regrowth or accumulation channel implantation. Fabricated MOSFETs subject to ohmic contact rapid thermal annealing at 850°C for 5min exhibit a high peak field-effect mobility (μFE) of 95cm2/Vs at room temperature (25°C) and 255cm2/Vs at 200°C with stable normally-off operation from 25°C to 200°C. The dependence of channel mobility and threshold voltage on the buried channel depth is investigated and the optimum range of channel depth is reported.

The formation of trench-gate power MOSFETs with a SiGe channel region

The fabrication of trench-gate power MOSFETs with a SiGe channel region has been proposed to further improve the device performance. A larger Ge mole fraction of Si1−xGex may cause a smaller on-state resistance but more degradation of the blocking voltage. A proper Ge mole fraction of 0.2 may be available, implementing a device with a blocking voltage of 30 V and a specific on-state resistance of about 0.70 Ω cm. On the other hand, a gradually changed Ge mole fraction of the Si1−xGex channel region may be employed to enhance the electric field in the channel region, and a specific on-state resistance of about 0.68 Ω cm can be achieved. Moreover, for this device with a SiGe channel region, a thin n-SiGe layer may be used in the drain near the channel region. This scheme can even yield a specific on-state resistance of only about 0.66 Ω cm which is 10% smaller than that caused by a conventional Si-channel device with the same process parameters.

Fabrication of trench-gate power MOSFETs by using a dual doped body region

Fabrication of trench-gate power MOSFETs by using a dual doped body region has been proposed to further improve the device performance. For the usual scheme that employs a uniform doped body region, a device with a blocking voltage larger than 30 V and a specific on-state resistance of about 1.0 Ω cm can be obtained via the proper choice of trench depth, epitaxial thickness, and body doping concentration. On the other hand, a dual doped body region is produced by dual high-energy and low-energy implantation of boron dopant. By this scheme, a device with a blocking voltage larger than 30 V and a specific on-state resistance of about 0.8 Ω cm can be further achieved. Hence, with reducing the cell pitch size to be below 2 μm, this device fabrication scheme should be promising and practical for achieving a specific on-resistance smaller than 0.1 mΩ cm 2 and a blocking voltage higher than 30 V.

High-density trench gate DMOSFETs with trench contact structure

A novel process technique for fabricating trench gate DMOSFETs using the two-step trench technique and trench contact structure is realised to obtain higher cell density and lower on-resistance. Using this process technique, a remarkably increased trench gate DMOSFET with a cell pitch of 1.6 µm and a channel density of 130 Mcell/in2 are obtained. The fabricated device has a low specific on-resistance of 0.28 mΩ · cm2 with a blocking voltage of 43 V, which is about 23 % lower than that of the device fabricated by the previous method.