Trench Gate MOSFET Research Articles

A novel double-trench SiC SBD-embedded MOSFET with improved figure-of-merit and short-circuit ruggedness

A novel 1.2-kV double-trench SiC MOSFET with stepped Schottky barrier diode (SBD) (DTSS-MOS) has been proposed and studied. The proposed device employs a deep gate trench filled with high-K dielectric and a shallow source trench with stepped SBD to modulate the electric field distribution, causing a higher figure-of-merit (FOM). After optimizing the structural parameters, the FOM of the DTSS-MOS improves by 266 % and 47 % compared to the planar-gate MOSFET (PG-MOS) and the trench-gate MOSFET (TG-MOS), respectively. Meanwhile, due to its lower specific on-resistance (Ron,sp), the DTSS-MOS exhibits an outstanding high-frequency figure of merit (HFFOM). Furthermore, the shallow source trench incorporates the stepped SBD, allowing the P-well region and P+ shielding layer to effectively reduce the electron flowing path in the SBD region, thereby lowering the temperature and enhancing the short-circuit withstand time (SCWT). The SCWT of the DTSS-MOS is increased by 75 % and 133 % compared with PG-MOS and TG-MOS, respectively. Additionally, a feasible process flow for the DTSS-MOS is provided.

Design strategy and working principle of GaN vertical trench gate MOSFETs with p-type shielding rings

Shielding ring (SR) structures are widely employed beneath the gate trench of vertical trench gate MOSFETs for the purpose of enhancing the gate oxide reliability and avoiding premature breakdown. To facilitate an in-depth understanding of the vertical power MOSFETs with p-type SRs (SR-MOSFETs), we numerically investigated the influence of the key parameters on the static characteristics of GaN-based vertical power SR-MOSFETs by TCAD simulation. We comprehensively elucidated the reach-through and non-reach through behaviors in the SR structures with different thicknesses, widths, and p-doping concentrations. We also illustrated the quasi-saturation effect by analyzing the 2D electron distribution and current density at the pinch-off point. With the same off-state voltage levels as conventional vertical MOSFETs, the SR-MOSFETs feature reduced on-state resistance and improved switching performance, which can provide theoretical guidance towards the development of high performance vertical gallium nitride power MOSFETs.

Mg activation anneal of the p-GaN body in trench gate MOSFETs and its effect on channel mobility and threshold voltage stability

This work addresses the impact of the Mg activation anneal step and the resulting acceptor concentration on the channel mobility and VT stability of vertical MOSFETs. Increasing the annealing time with N2 only ambient and the annealing temperature with O2 in the ambient is shown to be effective in increasing the channel acceptor concentration. When the effective acceptor concentration is increased, the mobility is degraded due to a transition in the main scattering mechanism from Coulomb to surface roughness scattering. Degradation of the on-state current and maximum transconductance at high operating temperatures was linked to bulk mobility degradation of the drift layer due to lattice scattering. The two Mg activation annealing conditions considered here show different trends with regard to the threshold voltage stability, while N2 only ambient did not impact this parameter, including O2 increased threshold voltage instability. It is shown that increasing the Mg chemical concentration in the p-GaN layer degrades channel mobility and threshold voltage stability, irrespectively of the effective acceptor concentration, providing evidence for degradation of the channel/dielectric interface characteristics with higher Mg chemical concentration. This study shows that it is possible to achieve very low threshold voltage hysteresis and high channel mobility by reducing the Mg chemical concentration while maintaining high effective acceptor concentration. These results provide key insights for the development of vertical GaN FETs.

Investigation of the time dependent gate dielectric stability in SiC MOSFETs with planar and trench gate structures

In this work, the time-dependent dielectric breakdown (TDDB) analysis is performed to understand the gate oxide reliability in SiC MOSFETs with two different structures, i.e., planar and trench gate structures. We have discovered different gate leakage current behaviors between the SiC MOSFETs with planar gate (Sample A) and trench gate (Sample B) during the forward gate bias stress. Notably, the slight increase of the gate current during the stress and the negative activation energy (Ea = −0.07 eV) observed in Sample A suggest that the hole generation caused by the impact ionization can be occurred during the forward gate TDDB tests. Furthermore, the SiC MOSFETs with trench gate structure (Sample B) exhibit the operation voltage of 55.7 V (exponential law) and 57.3 V (power law) for the 0.001 % failure of 30 years under 175 °C, indicating that SiC trench gate MOSFETs with enough thick gate dielectric (87.1 nm (bottom) and 77.9 nm (sidewall)) can have the promising forward gate TDDB stability.

The Electrical Characteristics of 1200 V Trench Gate MOSFET Based on SiC

The Electrical Characteristics of 1200 V Trench Gate MOSFET Based on SiC

Demonstration of SiC Trench Gate MOSFETs with Narrow Cell Pitch Using Source Self-Aligned Process

The SiC trench gate MOSFET with narrow cell pitch is demonstrated using a process in which the n+ source is self-aligned to the trench gate. A minimum cell pitch of 1.6 μm, which is difficult to achieve using the conventional device structure, is easily fabricated by applying a deep n+ source and a buried interlayer dielectric structure. The cell pitch reduction indicates a beneficial trend that contributes to a decrease in the specific on-resistance and an increase in the breakdown voltage. The process and structure are promising for further improving SiC power device characteristics.

Numerical demonstration of SiC trench MOSFET with integrated heterojunction diode for enhanced performance

In this paper, a novel SiC trench-gate MOSFET with integrated heterojunction diode (HD-TG-MOS) is proposed and studied according to TCAD simulations. The n-type polysilicon/n-type SiC HD is introduced into the groove by the direct contact between the polysilicon and semiconductor. As a result, significant improvements of device performance in the first and third quadrants are observed as compared to the conventional SiC trench-gate MOSFET (C-TG-MOS). Better yet, aided by the extremely low barrier height across the heterojunction, the knee voltage reduces to only 0.5 V with comparison of that of ∼2.7 V for the body diode, when used for reverse freewheeling. These promotions make SiC HD-TG-MOS more advantageous for HF power conversion applications. In addition, another cell architecture variant adopting a similar concept is presented, and the according process implementation is addressed as well from viewpoint of manufacture.

Simulation study on single-event burnout reliability of 4H-SiC trench gate MOSFET with combined P-buried layer

In this article, the purpose of this numerical study is to investigate the rated 3.3-kV SiC power gate trench MOSFET structure with ground and float p-buried layer (DGF-MOS). The simulation results show the introduction of ground and float p-buried layer and upper drift layer optimized breakdown voltage (BV) the specific on-resistance (Ron,sp), and gate drain charge (Qgd,sp), thus the figure of merit (BV2/Ron,sp) is improved by 130 % and the figure of merit (Ron,sp × Qgd,sp) is reduced 173 % compared with the conventional SiC power gate trench MOSFET (CT-MOS). Additionally, the single-event burnout (SEB) simulation results show that the critical degradation threshold of CT-MOS structure is 900 V at LET = 0.5 pC/μm. The robustness of the DGF-MOS structure design to heavy ions was simulated. The results show that the maximum temperature peaks around the gate trench and substrate junction of the DGF-MOS structure could both be effectively suppressed due to the decrease in electric field peak. Consequently, the DGF-MOS structure showed a severe denaturation threshold of 1500 V, which was 66.6 % higher than that of the CT-MOS structure.

An Optimized Vertical GaN Parallel Split Gate Trench MOSFET Device Structure for Improved Switching Performance

This work proposes a vertical gallium nitride (GaN) parallel split gate trench MOSFET (PSGT-MOSFET) device architecture suitable for power conversion applications. Wherein two parallel gates, and a field plate are introduced vertically on the sidewalls and connected, respectively, to the gate and source. Technology computer-aided design (TCAD) simulator was used in the design process to achieve a specific on-resistance as low as 0.79 mΩ.cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for the device, which has the capacity of blocking voltages up to 600 V. The peak electric field of the PSGT-MOSFET could well be lowered to 2.95 MV/cm, which is about 17% lower than that of a conventional trench gate MOSFET (TG-MOSFET) near the trench corner with help of suitable design and optimization of trench depth, drift doping, and field plate thickness. The TCAD simulation shows that the higher drift doping on the device performance of PSGT-MOSFET produces ~2× lower switching losses when compared with a similarly rated conventional TG-MOSFET device.

Effect of P+ Source Pattern in 4H-SiC Trench-Gate MOSFETs on Low Specific On-Resistance

Novel 1.7-kV 4H-SiC trench-gate MOSFETs (TMOSFETs) with a grid pattern and a smaller specific on-resistance are proposed and demonstrated via numerical simulations. The proposed TMOSFETs provide a reduced cell pitch compared with TMOSFETs with square and stripe patterns. Although TMOSFETs with a grid pattern reduce the channel area by approximately 10%, the cell density is increased by approximately 35%. Consequently, the specific on-resistance of the grid pattern is less than that of the square and stripe patterns. The forward blocking characteristics of the grid pattern are increased by the reduced impact ionization rate at the P/N junction. As a result, the figure-of-merit (FOM) of the grid pattern is increased by approximately 33%.

Investigation of a 4H-SiC Trench MOSFET with Back-Side Super Junction.

In this paper, a 4H-SiC trench gate MOSFET, featuring a super junction layer located on the drain-region side, is presented to enhance the breakdown voltage and the figures of merit (FOM). The proposed structure is investigated and compared with the conventional structure with a 2D numerical simulator—ATLAS. The investigation results have demonstrated that the breakdown voltage in the proposed structure is enhanced by 21.2%, and the FOM is improved by 39.6%. In addition, the proposed structure has an increased short-circuit capability.

Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate (SG), and p-type pillar (p-pillar) surrounded thick oxide shielding region (GSDP-TMOS) is investigated by Silvaco TCAD simulations. The source-connected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge (Q gd,sp) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage (BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance (R on,sp) becomes smaller. In the end, comparing with the bottom p+ shielded trench MOSFET (GP-TMOS), the Baliga figure of merit (BFOM, BV 2/R on,sp) is increased by 169.6%, and the high-frequency figure of merit (HF-FOM, R on,sp × Q gd,sp) is improved by 310%, respectively.

Effects of the stepped sidewall morphology on the ON-state performance for vertical GaN trench-gate MOSFETs

Vertical GaN trench-gate MOSFETs with ∼130 nm stepped sidewalls in the p-GaN channel layer are studied and two significant influences have been observed compared to the devices with smooth sidewalls. The first effect is the degraded channel mobility of 14.6 cm2 (V·s)−1 to 4.5 cm2 (V·s)−1 which can be attributed to the increased probability of surface acoustic phonons scattering under inversion conditions. Another impact is that only when a drain voltage (V DS) is applied over 30 V can the devices switch on. It can be speculated that the stepped sidewall has a horizontal channel and the transverse electric field is inadequate to drive the electrons at low V DS. According to the investigation, when devices need to be switched at a high V DS, the stepped sidewall morphology should be taken into consideration.

Gate Bias Dependence of V TH Degradation in Planar and Trench SiC MOSFETs Under Repetitive Short Circuit Tests

The reliability of SiC MOSFETs under harsh operating conditions, such as short circuit (SC) stress, remains a major concern. In this article, a dedicated aging platform is developed to study the degradation of SiC planar- and trench-gate MOSFETs under repetitive SC conditions. The static characteristics of the devices are monitored in real-time during the test. Depending on the gate bias used in the experiments, a bidirectional <inline-formula> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift in both types of devices is observed, yet with a different degradation rate. The underlying degradation mechanisms investigated by device simulation reveal that the damaged region in the SiC planar-gate MOSFET is located near the channel area, while at the trench corner in the SiC trench-gate MOSFET. These research outcomes enable better understanding of the degradation mechanisms of different SiC MOSFET structures and possible ruggedness improvements in the future.

High performance 4H-SiC MOSFET with deep source trench

In this study, we investigated a 4H-SiC deep source trench metal-oxide semiconductor field-effect transistor (DST-MOSFET) using technology computer-aided design numerical simulations. The proposed DST-MOSFET comprises a P-pillar formed along with the DST and a side P+ shielding region (SPR), which replaces the gate trench bottom SPR. Owing to the superjunction generated by the P-pillar and N-drift region, the static characteristics of the DST-MOSFET were superior to those of the trench gate MOSFET (UMOSFET) and double-trench MOSFET (DT-MOSFET). The specific on-resistance and Baliga’s figure of merit of DST-MOSFET improved by 9% and 104%, respectively, in comparison with those of UMOSFET; and by 37% and 64%, respectively, compared to those of DT-MOSFET. Additionally, the SPR reduced the gate-to-drain capacitance of the DST-MOSFET and improved the switching characteristics. Consequently, the total switching energy loss of the proposed DST-MOSFET reduced by 63% and 47% in comparison with those of the UMOSFET and DT-MOSFET, respectively.

Analysis of Electrical Characteristics in 4H-SiC Trench-Gate MOSFETs with Grounded Bottom Protection p-Well Using Analytical Modeling

A new analytical model to analyze and optimize the electrical characteristics of 4H-SiC trench-gate metal-oxide-semiconductor field-effect transistors (TMOSFETs) with a grounded bottom protection p-well (BPW) was proposed. The optimal BPW doping concentration (NBPW) was extracted by analytical modeling and a numerical technology computer-aided design (TCAD) simulation, in order to analyze the breakdown mechanisms for SiC TMOSFETs using BPW, while considering the electric field distribution at the edge of the trench gate. Our results showed that the optimal NBPW obtained by analytical modeling was almost identical to the simulation results. In addition, the reverse transfer capacitance (Cgd) values obtained from the analytical model correspond with the results of the TCAD simulation by approximately 86%; therefore, this model can predict the switching characteristics of the effect BPW regions.

Impact of Terrestrial Neutrons on the Reliability of SiC VD-MOSFET Technologies

Accelerated terrestrial neutron irradiations were performed on different commercial SiC power MOSFETs with planar, trench, and double-trench architectures. The results were used to calculate the failure cross sections and the failure-in-time (FIT) rates at sea level. Enhanced gate and drain leakage were observed in some devices which did not exhibit a destructive failure during the exposure. In particular, a different mechanism was observed for planar and trench gate MOSFETs, the first showing a partial gate rupture with a leakage path mostly between the drain and the gate, similar to what was previously observed with heavy ions, while the second exhibiting a complete gate rupture. The observed failure mechanisms and the postirradiation gate stress (PIGS) tests are discussed for different technologies.

Iron loss evaluation of magnetic materials excited by a SiC inverter with a Schottky barrier diode wall-integrated trench MOSFET

This study examines the impact of the different diode characteristics on the magnetic hysteretic and iron loss properties of a conventional non-oriented (NO) silicon steel sheet core under silicon carbide (SiC) inverter excitation. We compared the magnetic properties of the magnetic core excited by the inverter using the developed Schottky barrier diode (SBD) wall-integrated trench MOSFET (SWITCH–MOS), which has a low on-voltage Von diode, with those excited by the inverter using a conventional U-shaped trench gate MOSFET (UMOS), which has a body PiN diode with high Von. This study shows for the first time that the shape of the minor loop and iron loss properties depends strongly on only the diode characteristics in the inverter. The iron loss of magnetic materials excited by the SWITCH–MOS inverter with the low-Von diode (i.e., the built-in SBD) was less than that in the case of using the conventional UMOS with a high-Von diode (i.e., the body PiN diode). That is, the SWITCH–MOS with built-in SBD can reduce not only the switching loss, but also the iron loss in magnetic materials such as motor cores.

Impact of SiC Switch–MOS for Thermal Impedance Evaluation of Power Module

In this paper, thermal impedances of Silicon carbide (SiC) power module assembled with a Schottky Barrier Diode (SBD)–wall–integrated trench MOSFET (SWITCH–MOS) and a conventional trench gate MOSFET (UMOS) are measured. Then they are compared to show the advantage of SWITCH–MOS for thermal impedance measurement. SiC power device is attracting attention as a candidate for future power device, since it can be operated at higher current density and higher switching speed than conventional silicon (Si) power device. The power module packaging technology for SiC power device should have low thermal impedance (both transient and steady state thermal resistance) to bring out a potential ability of the device. Thermal design often has difference from measurement due to various modeling errors such as power device heat generation, module structure, interfacial thermal resistance, and cooling environment. Therefore, accurate thermal impedance measurement is an essential technology. However, the thermal impedance measurement of SiC power modules has the significant issue due to the instability of the body diode built into the SiC–MOSFET. The thermal impedance is the junction temperature rise per heat generation amount of the device. The temperature dependence of the knee voltage of the body diode is used to measure the junction temperature of the MOSFET. Since the knee voltage of SiC–MOSFET changes depending on the gate voltage, a high negative gate bias was necessary to avoid this effect. However, the negative gate bias stress may cause serious device damage such as threshold shift. The SWITCH–MOS which has SBD built in near the MOSFET channel is expected to stabilize the junction temperature measurement and avoid the risk of device deterioration. Figure 1 shows the cross–sectional schematic of the SWITCH–MOS and the conventional UMOS. The SBD are formed on the trench sidewall in SWITCH-MOS, and the device structure is almost same to the UMOS. The temperature is detected by the PiN diode for the UMOS and by the SBD for the SWITCH–MOS. Both of them measure the temperature inside of the MOSFET cell. The appearance of the test module is shown in Fig. 2. Each type of the test module is composed of the SiC die (SWITCH–MOS, UMOS, and SBD), an SiN–AMC insulating circuit substrate and an Al baseplate. The components are attached each other using AuGe solder. The junction temperature is measured from the built–in voltage of the body diode in response to a constant current flowing from the source to the drain. In the case of the UMOS, the gate bias of −18 V is applied. The gate bias is zero for the SWITCH–MOS. The thermal impedance of each test module was measured by static mode (Fig. 3). Then, the thermal structure function was calculated by transient thermal analysis (Fig. 4). Both the thermal impedance and the structure function for the SWITCH–MOS and UMOS were in good agreement. Since the SWITCH–MOS does not need negative gate bias, the threshold shift issue does not occur in principle. In addition, it is possible to perform a transient thermal testing with a large current for a long time. Because the forward degradation does not occur even if a large current is applied to the SBD in the SWITCH–MOS. The SBD built into the SWITCH–MOS makes it easier and more accurate to measure the junction temperature of the SiC–MOSFET. The thermal impedance measurement using SWITCH-MOS not only allows the precise thermal modeling of SiC power modules to be performed, but also has the potential to be applied to the calibration of the thermal design and the evaluation of thermal properties inside of the package structure. Figure 1

Vertical GaN Reverse Trench-Gate Power MOSFET and DC-DC Converter

A vertical GaN reverse trench-gate power MOSFET (RT-MOSFET) device is proposed. This Vertical RT-MOSFET features the negative incline of broaden-trench sidewalls at the bottom of the gate. Numerical device simulations using TCAD have been carried out for device and circuit performance study and analysis. The device performance like transfer characteristics, on-state, off-state characteristics, capacitance–voltage characteristics is observed. The simulation results are shown in comparison to the conventional such as perpendicular trench-gate (UT), and trapezoidal trench-gate (VT)-MOSFET devices. The RT-MOSFET has a ~ 9% and ~ 20% reduced on-state resistance (Ron), ~ 6% and ~ 10% enhanced electrical breakdown voltage (Vbr), and ~ 21% and ~ 46% superior Baliga's figure of merits ( $${V}_{br}^{2}/{R}_{on})$$ compared to UT-MOSFET and VT-MOSFET, respectively. Next, we obtain lower energy loss using TCAD Mixed-mode simulation for DC-DC boost converter circuit performance with different voltage. The RT-MOSFET saves ~ 30% and ~ 76% energy loss at 100 V, ~ 43%, and ~ 75% energy loss at 200 V and ~ 54% and ~ 87% energy loss at 400 V during DC-DC converter application compared to UT-MOSFET and VT-MOSFET, respectively.