Abstract
A novel 1.2-kV double-trench SiC MOSFET with stepped Schottky barrier diode (SBD) (DTSS-MOS) has been proposed and studied. The proposed device employs a deep gate trench filled with high-K dielectric and a shallow source trench with stepped SBD to modulate the electric field distribution, causing a higher figure-of-merit (FOM). After optimizing the structural parameters, the FOM of the DTSS-MOS improves by 266 % and 47 % compared to the planar-gate MOSFET (PG-MOS) and the trench-gate MOSFET (TG-MOS), respectively. Meanwhile, due to its lower specific on-resistance (Ron,sp), the DTSS-MOS exhibits an outstanding high-frequency figure of merit (HFFOM). Furthermore, the shallow source trench incorporates the stepped SBD, allowing the P-well region and P+ shielding layer to effectively reduce the electron flowing path in the SBD region, thereby lowering the temperature and enhancing the short-circuit withstand time (SCWT). The SCWT of the DTSS-MOS is increased by 75 % and 133 % compared with PG-MOS and TG-MOS, respectively. Additionally, a feasible process flow for the DTSS-MOS is provided.
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