Trench Etching Research Articles

A SiC Microstructured Neutron Detector Based on Deep Trench Etching Process

A SiC Microstructured Neutron Detector Based on Deep Trench Etching Process

A Model of Wafer Warpage for Trench Field‐Plate Power MOSFETs

A new wafer warpage model is proposed for the full process design of trench field‐plate (FP) power metal‐oxide‐semiconductor fileld‐effect transitors (MOSFETs) using large‐sized wafer. Trench FP power MOSFETs feature a deep trench and thick oxide at the wafer surface. Wafer warpage occurs due to the stress imbalance between the front and back sides of the wafer. This warpage leads to significant problems with transport errors in manufacturing equipment. This issue is expected to become even more crucial as lateral pitch narrowing is employed to reduce on‐resistance. In this study, two methods are compared to estimate the warpage of a 200 mm diameter Si‐wafer after trench etching and oxidation process. The mechanical stress generated by the oxidation process in several cell units is calculated using a 3D simulation. In the first approach, wafer warpage is converted from the displacement of the cell units. In the second approach, wafer warpage is estimated based on the surface film stress, which is calculated in the 3D simulation. The second approach shows good agreement with experimental results and is applicable to the 300 mm diameter Si process. This method yields more accurate measurements than the method using displacement.

Deep-reactive ion etching of silicon nanowire arrays at cryogenic temperatures

The pursuit of sculpting materials at increasingly smaller and deeper scales remains a persistent subject in the field of micro- and nanofabrication. Anisotropic deep-reactive ion etching of silicon at cryogenic temperatures (cryo-DRIE) was investigated for fabricating arrays of vertically aligned Si nanowires (NWs) of a large range of dimensions from micrometers down to 30 nm in diameter, combined with commonly used wafer-scale lithography techniques based on optical, electron-beam, nanoimprint, and nanosphere/colloidal masking. Large selectivity of ∼100 to 120 and almost 700 was found with resists and chromium hard masks, respectively. This remarkable selectivity enables the successful transfer of patterned geometries while preserving spatial resolution to a significant extent. Depending on the requirements by applications, various shapes, profiles, and aspect ratios were achieved by varying process parameters synchronously or asynchronously. High aspect ratios of up to 100 comparable to the best result by metal-assisted wet-chemical etching and sub-μm trenches by DRIE were obtained with NW diameter of 200 nm, at an etch rate of ∼4 μm/min without being collapsed. At the same time, low surface roughness values were maintained on the NW top, sidewall, and bottom surface of ∼0.3, ∼13, and ∼2 nm, respectively, as well as high pattern fidelity and integrity, which were measured using angle-resolved Fourier microscopy, combined atomic force, and scanning electron microscopy on selected NWs. This work establishes the foundation in the controllable development of Si nanoarchitectures, especially at sub-100 nm structures, for energy-harvesting and storage, damage-free optoelectronics, quantum, photovoltaics, and biomedical devices.

Voltage waveform tailoring for high aspect ratio plasma etching of SiO2 using Ar/CF4/O2 mixtures: Consequences of low fundamental frequency biases

The use of non-sinusoidal waveforms in low pressure capacitively coupled plasmas intended for microelectronics fabrication has the goal of customizing ion and electron energy and angular distributions to the wafer. One such non-sinusoidal waveform uses the sum of consecutive harmonics of a fundamental sinusoidal frequency, f0, having a variable phase offset between the fundamental and even harmonics. In this paper, we discuss results from a computational investigation of the relation between ion energy and DC self-bias when varying the fundamental frequency f0 for capacitively coupled plasmas sustained in Ar/CF4/O2 and how those trends translate to a high aspect ratio etching of trenches in SiO2. The fundamental frequency, f0, was varied from 1 to 10 MHz and the relative phase from 0° to 180°. Two distinct regimes were identified. Average ion energy onto the wafer is strongly correlated with the DC self-bias at high f0, with there being a maximum at φ = 0° and minimum at φ = 180°. In the low frequency regime, this correlation is weak. Average ion energy onto the wafer is instead dominated by dynamic transients in the applied voltage waveforms, with a maximum at φ = 180° and minimum at φ = 0°. The trends in ion energy translate to etch properties. In both, the high and low frequency regimes, higher ion energies translate to higher etch rates and generally preferable final features, though behaving differently with phase angle.

Polarization enhanced two-dimensional hole gas in III-nitride heterostructures for cryogenically operated GaN-based p-channel field effect transistors

In this work, AlN polarization-enhancement interlayer (AlN-PEL) is adopted to enhance two-dimensional hole gas (2DHG) density in a p-GaN/AlN-PEL(∼2 nm)/AlGaN(<6 nm)/GaN heterostructure, aiming at monolithic integration of p/n-channel field effect transistors (p-FETs) on GaN-on-Si substrate. Owing to the strong built-in polarization of the AlN-PEL, high density 2DHG over 2.3 × 1013 cm−2 with good immunity to thermal freeze out effect is realized. Assisted by a two-step gate trench etching process, enhancement-mode (E-mode) buried-channel GaN p-FETs with temperature independent ON-resistance RON, and ON/OFF current ratio ION/IOFF (>108), have been fabricated. The fabricated p-FETs also deliver thermally stable subthreshold swing as well as threshold voltage Vth, and smaller Vth shift than that of p-FETs without the AlN-PEL, which is primarily due to enhanced 2DHG confinement by the AlN-PEL. The proposed structure is an attractive platform for monolithic integration of GaN-based logic and power devices for cryogenic applications as low as 10 K.

Toward Band n78 Shear Bulk Acoustic Resonators Using Crystalline Y-Cut Lithium Niobate Films With Spurious Suppression

This work presents the study of suspended Y-cut Lithium Niobate shear bulk acoustic resonators for wide band filter applications in the frequency range of 3.5-4.5GHz. The resonators consist of a Lithium Niobate film with Aluminum top interdigitated electrodes (IDE) and floating bottom metal plate. Through vertical electric field excitation, shear bulk acoustic waves are generated in each unit cell of the device functioning as a quasi-independent resonator. Measured devices at 3.7GHz having large relative resonance-antiresonance bandwidth of 16.7% (750MHz), with 2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathrm{\Omega }$</tex-math> </inline-formula> impedance at resonance are presented. Suppression of higher order lateral harmonics through etching of trenches in the Lithium Niobate and geometric optimization is discussed.2022-0205

Bias-supply timing tailored to the aspect ratio dependence of silicon trench etching in Ar plasma with alternately injected C4F8 and SF6

In semiconductor device fabrication, the feature profiles of a high-aspect-ratio (HAR) Si trench is needed to be controlled considering aspect-ratio-dependent etching (ARDE). This is achieved by a cyclic process in which Ar plasma is sustained while C4F8 and SF6 are alternately injected and a short-period supply of a substrate bias is provided. Presently, the transient behaviors of gaseous and surface reactions are dynamically revealed by measuring the plasma parameters using a surface wave probe and optical emission spectroscopy. When the etched surface is fluorinated during the cycle, an ARDE-free Si-trench feature profile can be fabricated by controlling the bias-supply timing.

A self-aligned Ga2O3 heterojunction barrier Schottky power diode

We report an alignment-free gallium oxide (Ga2O3) heterojunction barrier Schottky (HJBS) power diode, which utilizes the self-assembled Ni nanostructures as in situ masks for the trench etching of Ga2O3 and the subsequent selective-area filling of p-type NiO. By increasing the trench depth to 200 nm, the relevant HJBS diode exhibits improved reverse blocking capabilities including the reduced leakage current density of 10−8 A/cm2 (at a reverse bias of 100 V) and the enhanced breakdown voltage of 748 V, while maintaining the forward biasing characteristics similar to the Schottky barrier diode (SBD). The variation of turn-on voltage and the reverse breakdown features indicate the conversion of the HJBS diodes characteristics from Ni/Ga2O3 SBD to the NiO/Ga2O3 p-n heterojunction diode. The electrical field simulations and experimental facts imply that the remarkable lateral pinch-off effect in the 200-nm trenched diodes shields the electric field in the depletion region underneath the Ni/Ga2O3 Schottky contact. This work provides a straightforward strategy to simplify the fabrication process of Ga2O3-based HJBS diodes with both promising forward and reverse performances.

Asynchronously Pulsed Plasma for High Aspect Ratio Nanoscale Si Trench Etch Process

The fabrication of high aspect ratio Si trenches has been becoming difficult due to the decrease in critical dimension (CD) to deep nanoscale. Especially, aspect ratio dependent etching (ARDE), which decreases the etch rate as the pattern width gets smaller, makes process uniformity get worse. In this study, the effects of bias pulsing parameters during asynchronous pulsing, which alternatively applies the source power and bias power, as well as the effect of additive gas such as CF4 and C4F8 on the nanoscale Si trench etch characteristics during Cl2/Ar plasma etching were investigated. It was found that the bias pulsing parameters during the asynchronous pulsing, such as bias pulse duty ratio and bias pulse delay time, can affect the etch characteristics such as etch rate, etch selectivity, and ARDE by changing the ion dose and ion energy during the etching. However, the variation of bias pulse parameters during the asynchronous pulsing did not change the etch profile noticeably, and it showed bowed Si trench etch profiles. To improve the etch profile, the addition of fluorocarbon gas such as CF4 and C4F8 was required, and by using C4F8 instead of CF4, more anisotropic Si etch profile without sidewall bowing could be obtained due to the improved sidewall passivation by a fluorocarbon layer even though it degraded etch selectivity and ARDE. Therefore, it is believed that by controlling the bias pulsing parameters with additive gas, nanoscale Si trench etch characteristics can be more easily controlled.

Realization of independent contacts in barrier-separated InAs/GaSb quantum wells

InAs/GaSb double quantum wells separated by a 100 Å AlSb middle barrier are grown by molecular beam epitaxy. We report a nanofabrication technique that utilizes the surface Fermi level pinning position in InAs [Efs(InAs)] for realizing independent electric contacts to each well. In particular, separate Ohmic contacts to the upper InAs quantum well are achieved by selectively etching down to the InAs, while contacts to the lower GaSb quantum well are obtained by the depletion method. For the latter, the upper InAs quantum well is locally pinched off by top etched trenches capped with a remaining 2–3 nm InAs layer. As a result of a relatively low Efs(InAs), applying a negative bias gate potential will create a conducting hole channel in GaSb and, hence, a separate Ohmic contact to the lower quantum well. This method is demonstrated with experiment and the support of a self-consistent band bending calculation. A number of experiments on separately probing Coulomb and tunnel-coupled InAs/GaSb systems now become accessible.

Improving Detection Efficiency of Silicon Carbide Neutron Detector Using Double Trench

In this article, we propose a double-trench-type silicon carbide (SiC) neutron detector and model it using the concept of a unit cell on the GEANT4 platform. When the low-level discriminator (LLD) value was fixed at 300 keV, the structural parameters of this double-trench-type SiC neutron detector were optimized to maximize the intrinsic detection efficiency. Compared with the single trench type, the double-trench-type SiC neutron detector can significantly improve the neutron intrinsic detection efficiency within a limited trench depth, which was especially suitable for the current technological status that SiC materials can only be used for shallow trench etching. Apart from optimizing the structural parameters, the energy deposition spectra in the SiC detector region by the generated secondary charged particles upon thermal neutron interaction in neutron conversion materials ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{{10}}\text{B}$ </tex-math></inline-formula> and 6LiF) have also been estimated. It can be found that the double-trench-type SiC neutron detector counts significantly increased in the low-energy range, while the counts in the high-energy range are only slightly decreased. This is also the essential reason why the intrinsic detection efficiency of the double-trench-type SiC neutron detector was significantly improved compared to the single-trench-type SiC neutron detector.

Switchable thermal waveguides in GaAs based devices

The modulation of light within microscopic devices is the key to designing versatile and powerful photonic integrated circuits (PICs). Contemporary techniques are able to generate a wide range of waveguiding and waveforming elements. They are implemented by the etching of trenches, laser induced waveguide writing, and many other techniques. However, most of the fabricated structures feature a static waveguiding behavior that remains unaltered after processing the devices. In this work, we demonstrate the simulation, design, and experimental behavior of truly switchable microscopic waveguides. We demonstrate the presence of waveguiding and forming elements by localized heating, leading to a tunable refractive index profile in GaAs based devices. We give insights into the microscopic behavior by multi-physics simulations in the mechanical, thermal, and optical domains. This approach opens the way to further possibilities in the design of PICs and useful modifications within existing diode laser and amplifier setups.

Упругое рассеяние атома рутения на атомах Si и O в диапазоне относительных кинетических энергий 2-200 eV

Interconnector technologies of a new generation involve use of ruthenium. The high cost of experimental study of sputtering and etching of trenches in Ru leads to the need to optimize it by modeling, requiring knowledge of the cross sections of elementary processes of interaction of plasma particles with Ru. In this work, the binary interatomic potentials of Ru-Ru and Ru-Si pairs, tested by molecular dynamics method, and the Ru-O one calculated using the multi reference configurational interaction MRCI/AV5Z were used to calculate the elastic scattering cross sections of the atomic pairs in the energy range typical for plasma etching chambers.

Elastic scattering of ruthenium atoms from Si and O atoms in the range of relative kinetic energies of 2-200 eV

Interconnector technologies of a new generation involve the use of ruthenium. The high cost of experimental study of sputtering and etching of trenches in Ru leads to the need to optimize it by modeling that requires knowledge of the cross sections of elementary processes of interaction of plasma particles with Ru. In this work, the binary interatomic potentials of Ru-Ru and Ru-Si pairs tested by the molecular dynamics method, and the Ru-O one calculated by the method of multi-reference configurational interaction MRCI/AV5Z were used to calculate the elastic scattering cross sections of the atomic pairs in the energy range typical of plasma etching chambers. Keywords: ruthenium, elastic scattering, cross sections, sputtering, binary potential.

Rate optimization of atomic layer etching process of silicon

With the shrink of critical dimensions of semiconductor devices to a few nanometers, atomic layer etching (ALE) has become an important technique to achieve single-atom resolution. The ALE can divide plasma etching into two self-limiting reaction processes: passivation process and etching process, allowing for the sequential removal of material atomic layer by layer. Therefore, it encounters the problem of low etch rate. In this work, the variation in surface substance coverage during the passivation process and the etching process are investigated numerically to optimize both the passivation duration and the etching duration. A coupled model integrating a two-dimensional inductively coupled plasma discharge chamber model, a one-dimensional sheath model, and a three-dimensional etching trench model is developed and used to investigate the optimal time for one single cycle ALE of silicon through the use of Ar/Cl&lt;sub&gt;2&lt;/sub&gt; gases under the condition of Ar inductively coupled plasma discharge. The results indicate that during the passivation stage, the surface coverage of SiCl and SiCl&lt;sub&gt;2&lt;/sub&gt; initially increase with time going by and then decrease, while the surface coverage of SiCl&lt;sub&gt;3&lt;/sub&gt; continuously increases, and eventually, the surface coverage of these three species stabilize. When the surface is predominantly covered by SiCl&lt;sub&gt;2&lt;/sub&gt;, it is the optimal time to trigger the etching process, which induces a relatively favorable surface state and a relatively short etching time. Comparing with typical ALE etching techniques, the time of our optimal ALE single cycle is shortened by about 33.89%. The ALE cycle time (etching rate) exhibits a linear relationship with the aspect ratio. Additionally, the duration of the passivation process and etching process increase linearly with the aspect ratio or etch depth increasing. Moreover, as the etch depth increases, the effect of the passivation process on the ALE rate becomes more significant than that of the etching process.

Simulation of hybrid silicon nitride/polymer Mach-Zehnder optical modulator beyond 170 GHz

In this paper, a hybrid Mach-Zehnder optical modulator is proposed based on silicon nitride/organic polymer waveguides, which is expected to break through the performance bottleneck of the silicon-based optical modulator by exploiting the low-loss optical transmission property of silicon nitride waveguides and the excellent modulation performance of organic polymers. For reduction of the optical loss and ease of photonic packaging, perfectly vertical silicon nitride bidirectional grating couplers are utilized for both input/output optical coupling and power splitting/combining. Thus, a Mach-Zehnder interferometer can be constructed with a back-to-back configuration of such grating couplers. With grating apodization, the coupler can achieve a simulated coupling efficiency of 70%. To bridge the silicon nitride waveguides and the polymer waveguides, a longitudinal adiabatic mode-spot converter with a transmission efficiency of 99.2% was designed. In this paper, high-β donor-π bridge-accepter molecule YLD-124 combined with HD-BB-OH as the host polymer is utilized for a design example. The polymer waveguides with inverted ridge structure can be realized through the processes of silica cladding etching, spin coating or microfluidic trench filling of polymer. Following this design, we numerically demonstrate a hybrid silicon nitride-polymer Mach-Zehnder modulator with modulation efficiency of 1.57 Vcm and Electric-Optical bandwidth of 174 GHz. The total insertion loss is less than 5.74 dB, including two grating coupler losses of about 3.08 dB.

Method for Keyhole-Free High-Aspect-Ratio Trench Refill by LPCVD.

In micro-machined micro-electromechanical systems (MEMS), refilled high-aspect-ratio trench structures are used for different applications. However, these trenches often show keyholes, which have an impact on the performance of the devices. In this paper, explanations are given on keyhole formation, and a method is presented for etching positively-tapered high-aspect ratio trenches with an optimised trench entrance to prevent keyhole formation. The trench etch is performed by a two-step Bosch-based process, in which the cycle time, platen power, and process pressure during the etch step of the Bosch cycle are studied to adjust the dimensions of the scallops and their location in the trench sidewall, which control the taper of the trench sidewall. It is demonstrated that the amount of chemical flux, being adjusted by the cycle time of the etch step in the Bosch cycle, relates the scallop height to the sidewall profile angle. The required positive tapering of 88° to 89° for a keyhole-free structure after a trench refill by low-pressure chemical vapour deposition is achieved by lowering the time of the etch step.

Study on the Transformation of Si Trench Profile With Low Pressure of SF₆/O₂ Containing Plasmas

The reason for the change of trench sidewall profile under low pressure of SF6/O2 containing plasma was explored by studying the trench morphology under different etching conditions. The result shows that the Si undercut decreases with the decreasing of pressure and the uniformity will become better. However, the sidewall of the trench presents a negatively tapered under low pressure. The reasons for different profile of trench are explored by the thickness of sidewall protective layer for the first time. The TEM results show that the trench sidewall forms a protective film with a thickness of about 100Å. The thickness of the oxide layer decreases from top to bottom. And the EDX results show that the main elements of the protective film are Si and O. Due to the decrease of oxide thickness, the width of trench bottom will become larger and larger, resulting in negatively tapered morphology. It is worth noting that the profile of trench changes to positively tapered again under the condition of low ratio of SF6/O2. Based on this, an optimized trench etching process is proposed and the etch rate is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.15{\mu }\text{m}$ </tex-math></inline-formula> /min and the selectivity to the oxide mask is 14.

(Invited) Vertical Gallium Nitride Mosfets for Electric Drivetrains

Wide-bandgap semiconductors have a significant advantage over conventional Si-based electronics by leveraging materials properties to achieve higher breakdown voltage, lower on-resistance, and high-frequency operation. For electric vehicle drivetrains, this translates to higher efficiency and power density, resulting in more miles driven per charge. This move towards wide-bandgap power electronics is necessary to achieve the U.S. Department of Energy (DOE) power electronics density target of 100 kW/L.Vertical gallium nitride-based power devices are expected to exceed Si and even SiC-based systems with the promise of increased performance and power density. Compared to lateral GaN devices, a vertical topology promotes more efficient scaling towards high-power applications, where both high voltage and high current are necessary. This talk describes our team’s effort towards developing vertical GaN MOSFETs. The results of Sandia’s first-generation device demonstrator serve as a milestone in the path of producing devices rated for 1200-V and 100-A operation.The vertical GaN trench MOSFET is unique compared to Si- or SiC-alternatives in that the doped layers comprising the source and body regions are grown by epitaxy rather than formed by ion implantation. Challenges with selective-area doping in GaN add additional complexity to the design of a trench MOSFET. In addition, the lack of a high-quality native oxide in GaN means that the gate dielectric must be deposited rather than thermally grown. The devices produced at Sandia rely on atomic-layer-deposited thin films for the gate dielectric (primarily Al2O3 or SiO2). First-generation results demonstrate devices capable of 400 mA/mm drain current, 108 on/off ratio, and a positive threshold voltage near 8 V. More recently, devices capable of blocking 500 V in the off-state have been demonstrated. Device failure in the off-state results from high fields in the gate dielectric, which can be minimized by reducing the trench etch depth or by increasing the voltage rating of the drift region. However, further shielding of the gate dielectric to achieve substantially higher off-state voltages requires significant changes to the device architecture which are reliant on selective-area doping. In addition, device-killing defects either from the starting substrate, the epitaxy, or defects introduced during processing limit yield for large-area devices and present a substantial obstacle to scale devices for high-current operation. Hence, methods for reducing cell pitch and increasing packing density are highly valued. In this talk, we will discuss the path forward for achieving higher breakdown voltages and high-current operation using GaN-specific strategies to achieve better performing devices, as well as some of the challenges for vertical GaN development. This work provides a foundational platform for developing next-generation power electronics that employ wide bandgap, gallium nitride semiconductors. This work was supported by the Electric Drivetrain Consortium managed by Susan Rogers of DOE’s Vehicle Technologies Office. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. Figure 1

Accumulation-Mode Device: Experimental of LDMOS With Folded Drift Region Achieving Ultralow Specific ON Resistance

In order to reduce the specific ON resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{R}_{\mathbf {{ \mathrm{\scriptscriptstyle ON}},sp}}$ </tex-math></inline-formula> ) of power device in the drift region, the folded accumulation lateral double-diffused MOSFET (FALDMOS) is manufactured and analyzed in this article. The drift region of the FALDMOS is etched to form the folded surface, which is similar to the FinFET structure. The oxide inside the trench optimizes the electric field in the drift region, so the doping concentration can be increased while maintaining the breakdown voltage (BV). In addition, the trench increases the area of the drift region covered by the extended gate electrode, which can introduce more accumulated electrons when the device is turned on. The increased doping concentration and accumulated electrons work together to substantially increase the conductivity of the drift region, thereby obtaining ultralow <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ </tex-math></inline-formula> . Furthermore, the folded accumulation LDMOS with split gate (FSLDMOS) is proposed to solve the phenomenon that the BV of the FALDMOS cannot be improved by increasing the drift length with the fixed oxide thickness. The polysilicon above the drift region is etched apart to form an extended gate and a split electrode. The electric field concentration near the drain can be alleviated by adjusting the bias on the split electrode. The FALDMOS and FSLDMOS are manufactured by the 0.35- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD technology and the key processes, such as trench etching and polysilicon filling, are shown. The experimental results show that <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{R}_{ \mathrm{\scriptscriptstyle ON},sp}$ </tex-math></inline-formula> of the FALDMOS is only 9.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> mm2, while that the conventional LDMOS is 36.2 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> mm2, which is reduced by 74.3% with the same BV of 36 V. Moreover, the current density of FALDMOS is five times higher than that of the conventional LDMOS in the same areas. The BV of the FSLDMOS is improved by 66% compared with FALDMOS.