Trench Etching Research Articles

Reverse-Conducting IGBT Using MEMS Technology on the Wafer Back Side

In this paper, we present a 600-V reverse conducting insulated gate bipolar transistor (RC-IGBT) for soft and hard switching applications, such as general purpose inverters. The newly developed RC-IGBT uses the deep reactive-ion etching trench technology without the thin wafer process technology. Therefore, a freewheeling diode (FWD) is monolithically integrated in an IGBT chip. The proposed RC-IGBT operates as an IGBT in forward conducting mode and as an FWD in reverse conducting mode. Also, to avoid the destructive failure of the gate oxide under the surge current and abnormal conditions, a protective Zener diode is successfully integrated in the gate electrode without compromising the operation performance of the IGBT.

Deep reactive ion etching of sub-micrometer trenches with ultra high aspect ratio

This paper focuses on deep reactive ion etching (DRIE) of sub-micrometer features. Very high aspect ratios up to 160:1 on trenches of 250nm have been achieved using the Bosch process and up to 120:1 on trenches of 35nm using a cryogenic process. The proposed etch recipes are specifically optimized for sub-micrometer features, and are not compatible with feature sizes in the tens of micrometer range. Based on analyzing data from our experiments and from literature, we show that a previously reported two-parameter empirical logarithmic law accurately describes the dependency of aspect ratio on trench width over a wide range of widths and etch parameters, including the sub-micrometer regime. We also propose a new figure of merit (FOM) that describes the ultimate aspect ratio achievable for any given etching process. This FOM also allows comparison of different aspect ratio performances, while taking into account in the same time, the dimension of the trench for which this performance is attained.

Investigation of plasma etch damage to porous oxycarbosilane ultra low-k dielectric

There has been much interest recently in porous oxycarbosilane (POCS)-based materials as the ultra-low k dielectric (ULK) in back-end-of-line (BEOL) applications due to their superior mechanical properties compared to traditional organosilicate-based ULK materials at equivalent porosity and dielectric constant. While it is well known that plasma etching and strip processes can cause significant damage to ULK materials in general, little has been reported about the effect of plasma damage to POCS as the ULK material. We investigated the effect of changing the gas discharge chemistry and substrate bias in the dielectric trench etch and also the subsequent effect of the cap-open etch on plasma damage to POCS during BEOL integration. Large differences in surface roughness and damage behaviour were observed by changing the fluorocarbon depositing conditions. These damage behaviour trends will be discussed and potential rationalizations offered based on the formation of pits and craters at the etch front that lead to surface roughness and microtrenching.

Applying Uniform Design of Experiment in Tri-Layer-Based Trench Etch for EM Lifetime Performance Enhancement

In this paper, we studied the improvement of EM lifetime distribution including both intrinsic lifetime extension and the reduction of earlier failure percentage by applying a uniform design of experiments (UDE) to organic under layer (OUL) step. UDE is an experimental approach that is capable of distributing experiments evenly within experimental space, especially when a large number of experimental levels are required. In our case, the experiments were carried out with a six variable design table of OUL step’s important parameters including pressure, power, gas flow rate and over-etch percentage. Factor level varies from four to six for each variable based on previous silicon wafer learning. The optimal OUL condition was identified among the EM performance of 18 UDE pi-runs by means of statistically scientific analysis. The predicted condition was validated and shows the current-best EM performance from the point of view of EM lifetime and the earlier failure percentage.

Review of Plasma-Based Etch Treatment in Dielectric Etch Processes

This work mainly focuses on the post-etch treatment (PET) in dielectric etch processes from contact etch, trench etch to all-in-one etch. PET step is optimized not only to efficiently remove the byproducts formed on the sidewall/bottom of contact/via hole during etch proceses but also to eliminate the surface corrosion of the etched metal comprising feature. Besides, we also leveraged PET to repair low-k damage and prevent the formation of mositure on film surface by modifing film from hydrophilic to hydrophobic, especially for low-k/ultra low-k dielectric processes. Results show the actual effect of PET in terms of reliability performance highly relies on the specific etch recipe, wet clean condition and substrate material in back end of line (BEOL). We also addressed the pre-etch treatment to effectively reduce the impact of photo-resist scumming in contact etch. In brief, plasma-based etch treatment is imperative to extend the tightened process window margin.

Strain Transfer Analysis of Surface-Bonded MEMS Strain Sensors

The transmission of strain fields in adhesively bonded MEMS strain sensors is analyzed. In strain sensors that are attached to host structures using adhesive layers such as epoxy, complete strain transfer to the sensor is hindered due to the influence of the adhesive layer on the transfer. This paper presents an analytical model, validated by finite element method simulation, to provide insight and accurate formulation for strain transfer mechanism for bonded sensors. A shear-lag parameter has been introduced to account for the component geometry and properties. The model is capable of predicting the strain transmission ratio through a sensor gauge factor, and it clearly establishes the effects of the flexibility, length, and thickness of the adhesive layer and MEMS sensor substrate. Finally, modifications to sensor substrates, by the implementation of micromachined tapered edges and trench etching, are proposed in order to increase the strain transmission ratio. It has been found, for the selected case study, that the sensor sensitivity could be enhanced by up to 30%. This work on bonding analysis is applicable for performance prediction and calibration in sensor systems design.

Effect of Damage Removal Treatment after Trench Etching on the Reliability of Trench MOSFET

Guaranteeing the reliability of gate oxides is one of the most important topics to realize regarding the SiC power MOSFET. In the case of trench MOSFET, since the gate oxides are formed on the trench sidewall, the damage and roughness on the trench sidewall can affect the lifetime of the gate oxides. Generally speaking, damage removal treatment is processed after trench dry etching in most cases. In Si processes, sacrificial oxidation, H2 anneal and CDE (Chemical Dry Etching) are adopted commonly. In the case of SiC processes, sacrificial oxidation, H2 anneal, and SiH4/Ar anneal have been reported. Neverthless CDE which applied to SiC trench MOSFET has few precedents. We clarified the effect of CDE as a damage removal process. CDE has the effect of flattening the trench sidewall, and CDE makes the lifetime of gate oxides improve. CDE is an effective process for the reliability of SiC trench MOSFET.

Reliability of through-silicon-vias (TSVs) with benzocyclobutene liners

Through-silicon-vias (TSVs) using benzocyclobutene (BCB) as insulation layers (liners) are developed and the reliability related issues with regard to mechanical and electrical aspects are investigated. The BCB TSVs are fabricated using deep etching of annular trenches on a substrate, BCB cladding forming in the deep trenches, selective etching of the silicon posts in BCB claddings, and electroplating of copper plugs. The insulation capability and the configuration stability of BCB liners are evaluated by performing a thermal shock test and comparing the leakage currents before and after thermal shock. The results show that the BCB insulation capability does not change distinctly after thermal shock. Auger electronic spectroscopy (AES) is used to characterize copper diffusion through BCB thin films after high temperature treatment, and it is found that BCB is able to prevent copper diffusion at temperatures as high as 350°C. Finite element analysis is performed to understand the thermal stress behaviors of BCB TSVs, and the simulation results show that BCB liners are able to reduce the thermal induced stresses in substrates, but increase the axial thermal expansion of copper plugs.

Bonding Structure of Model Fluorocarbon Polymer Residue Determined by Functional Group Specific Chemical Derivatization

The incorporation of porous low-k (k = 2.0) interlayer dielectrics (ILD) in BEOL (back-end-of-line) interconnects to reduce RC time delays continues to pose major integration challenges. Typically, low dielectric constants are achieved by replacing Si‐O bonds with Si‐C bonds to create nanoscale porosity in the silicon oxide dielectric matrix. 1 Porosity induced lowering of mechanical strength in carbondoped silicon oxide (CDO) makes them more susceptible to damage caused by common patterning processes such as fluorocarbon-based reactive ion etching (RIE). 1 Characterization of the post-RIE etch fluorocarbon polymer residues is essential because incomplete removal can cause problems with subsequent layers such as poor adhesion and coverage, fluoride contamination and poor electrical contact. 2 Electron and optical spectroscopy, electron microscopy, scanning probe microscopy and other probing tools have been used to identify and characterize model post-etch residues deposited on blanket Si substratesorcheckerboardpatternedwafersoflargedimensions. 3‐7 However, an improved understanding of chemical bonding structure of these fluoropolymer coatings is needed to facilitate more efficient process integration between trench etch and post-etch clean for small patterned features. In this study, the chemical bonding structure of model fluorocarbon polymer (MFP) residues deposited on a patterned CDO trench nanostructurewasdeterminedusingFouriertransforminfrared(FTIR) spectroscopy, X-ray photoelectron spectroscopy (XPS) and scanning electron microscopy (SEM). The MFP residues (6‐28 nm) were deposited on 90 nm low-k dielectric lines using fabrication processes closely mimicking actual manufacturing conditions. Enabled by precise background cancellation, FTIR revealed detailed chemical bondingcompositionoftheMFPresidues.Functionalgroupspecificchemistry in conjunction with IR and XPS analyses showed that MFP residue consisted of amorphous fluorinated polymers with significant branching, C=C bonds and C=O functional groups. The chemical bonding composition of deposited fluorocarbon layers can be modified by altering the plasma chemistry which can potentially lead to a more clean-efficient plasma etching process.

Laser-induced front side etching of CaF2 crystals with KrF excimer laser

The laser-induced front side etching (LIFE) of amorphous materials like fused silica was manifold studied and the LIFE process was sufficient optimized for the fabrication of well-defined etching trenches with a very low surface roughness. The LIFE process is an indirect laser-induced ablation process, the – for the used laser wavelength – transparent substrate was covered by a highly absorbing material and the absorbing process causes a transfer of the laser energy into the substrate and, finally, to an ablation process of the substrate surface.However, the structuring of crystalline materials like CaF2 is a great challenge for the LIFE process. The properties of CaF2(111) and CaF2(001) surfaces etched by KrF excimer laser pulses (pulse duration Δtp=25ns, wavelength λ=248nm) were analysed by white light interferometry (WLI) as well as scanning electron microscopy (SEM). The surface morphologies of laser etched CaF2 surfaces depend on the laser parameters and on the crystal orientation and are frequently characterized by microcracks and flake spallation. The most probable reasons therefore are laser-induced thermal stress or laser-induced shock waves.

Surface states in the optical spectra of two-dimensional photonic crystals with various surface terminations

Reflection and transmission spectra of two-dimensional photonic crystal slabs, fabricated by photoelectrochemical etching of deep macropores and trenches in Si, are investigated theoretically and experimentally. It is shown that the presence of an unstructured silicon interfacial layer between the air and the photonic crystal structure can give rise to surface (Tamm) states within the TE and TM photonic stop bands. In the presence of roughness of inner surfaces of air pores, the surface states show up as dips within the stop bands in the reflection spectrum. The calculated electromagnetic near-field distribution demonstrates the vortices between the upper pores at the frequency of the surface mode. The experimental reflection and transmission spectra are in a good agreement with theoretical calculations performed by the Fourier modal method in the scattering matrix form.

Narrow Linewidth Single-Mode Slotted Fabry–Pérot Laser Using Deep Etched Trenches

We report the design and experimental results of a narrow linewidth single-mode slotted Fabry-Pérot laser by using deep etched trenches. Good performances in lasing threshold, side-mode suppression ratio, and linewidth are obtained. The deep trench is effective in reducing the cavity loss compared to the previously investigated shallow etched slots, resulting in a lower threshold and a narrower linewidth (down to ~80 kHz). Since no grating and multiple epitaxial growth are required, such a simple, compact, and monolithic semiconductor laser with narrow linewidth may have potential applications in coherent communication systems.

A novel trench gate MOSFET with a multiple-layered gate oxide for high-reliability operation

Gate dielectrics in trench structures for trench gate metal oxide semiconductor field-effect transistor (MOSFET) power devices are very important to realize excellent characteristics. In this paper we describe multiple-layer gate dielectrics for trench gate MOSFETs with both thermal and chemical vapor deposition (CVD) gate oxides that exhibit excellent gate oxide properties and surface roughness. Through various trench etching experiments for better surface conditions in the trench, the optimum etching gas chemistry and etch conditions were found. The destruction of gate dielectric in trench gate MOSFET occurs at the top and the bottom trench corner edges. The structure of the gate electrode is pulled out with the polysilicon layer which is buried in the trench. Thus, high electric field operation is inevitable at the gate between source diffusion and the gate polysilicon. Moreover, the trench corner oxide suffers from the high electric field. We propose a multiple-gate dielectric structure of a thermal oxide and CVD oxide for highly reliable operation of the device. This enables trench surface smoothing and low thermal stress at the trench corners and provides the oxide thickness uniformity, giving superior device characteristics of high breakdown voltage and low leakage current. These improvements are caused by the excellent quality of the gate oxide and the good thickness uniformity that is formed at the inner trench with a specific geometrical factor.

A dry wafer-reconstitution process with zero insertion force by embedded alignment guide tabs

We demonstrate embedding of chiplets into wafers to bypass the monolithic integration challenges of combining micro-mechanical devices with active circuitry. Dry alignment is provided by passive guide tabs, which are created through polysilicon refill of frontside etched trenches. The guide tabs are compatible with further processing on the wafer. Precision chiplets are created by through-wafer etching. After chiplet drop-in, optical detection provides feedback of chiplet jamming, and horizontal driving of the chiplets finishes the zero insertion force assembly process. We demonstrate less than 2.5 µm of chiplet to substrate alignment error. Theoretical scaling of alignment accuracy reaches numbers comparable to photolithography, allowing high density interconnects for heterogeneous integration without precision manipulators.

The Critical Role of Dielectric Trench Etch in Enhancing Cu/low-k Dielectric Reliability for Advanced CMOS Technologies

In this work, we focused on the via-first approach and studied the impacts of trench etch on the electrical reliability of copper interconnects in terms of electro migration (EM), stress migration (SM), time dependent dielectric breakdown (TDDB) and chip package interaction (CPI). The huge micro-trench formed during trench etch could lead to the inter-layer voltage break-down, thus triggering CPI failure. Polymer and bombardment have been well managed in trench etch to solve this issue without degrading TDDB performance. Besides, post-etch treatment (PET) has been proven effective and critical in enhancing EM, SM and TDDB performance but it direct extension to M1 etch need reassess for the sake of trench etch recipe and substrate difference.

A Study of Dry Etching Process for Sigma-Shaped Si Recess

The fabrication of sigma-shaped silicon recess normally consists of dry etch process to shape the silicon trench and post etch treatment to form the sigma-shaped cavity within bulk silicon substrate. Here we are dedicated to the optimization of silicon recess dry etch process and its effect on the final sigma-shaped SiGe physical performance. Results show the isotropic ratio of horizontal over vertical direction could be doubled. This caters much larger process window for the desired strain introduction at the hetero-junction of SiGe/Si. Besides, the corresponding dry etching solutions are also disclosed from the point of view of tip depth adjustment and tip horizontal pull-back control. Both physical indexes could be independently controlled to deliver the required sigma-shaped Si recess trench.

Kinetics Investigation of RIE Lag Phenomenon by GaAs ICP Etching

In this paper, according to the relationships of the etch-rate with the FWs from 2μm to 100μm and of the etch-rate changes with etch-time for a particular FW, obtained by our experiments, a possible etching process model were proposed. When the etch-time was relatively short, it was the reaction limited process. With the etch-time going on, the fresh reactive gas was difficult to get through the etching trench to the fresh reaction interface, the etch-rate decreased, which was called the residual removing limited process. Our mathematic fitting results proved the above etching model and pointed that for the reaction limited process, the etch depth linearly increase with the etch time. While it got into the residual removing limited process, the etch-rate decreased.

Epitaxial Growth of 3C-SiC onto Silicon Substrate by VLS Transport Using CVD-Grown 3C-SiC Seeding Layer

The crystal growth of 3C-SiC onto silicon substrate by Vapour-Liquid-Solid (VLS) transport has been investigated. In the studied growth configuration, propane feeds a SiGe liquid phase contained in 10 µm-deep etched trenches on the Si substrate. Before SiGe deposition, the substrate surface and the trench walls were coated with a thin (100 - 200 nm) CVD-grown 3C-SiC seeding layer. For the VLS growth, the temperature was increased up to 1280°C, above the SiGe alloy melting point, at which point propane was added to start VLS growth. X-ray diffraction shows that some SiC is grown epitaxially onto the CVD seeding layer. However, cross-section SEM observations have evidenced that SiC has grown as trapezoidal islands and not as an uniform layer. Backscattered electron images also clearly show a deep penetration of germanium into the substrate through the SiC seeding layer. This penetration was found to be strongly reduced when increasing the seeding layer thickness from 100 to 200 nm.

Etch Process Optimization and Electrical Improvement in TiN Hard Mask Ultra-Low K Interconnection

ABSTRACTAs critical dimensions decrease, key dimension-related dielectric etch challenges emerge, including via and trench uniformity and etch depth profile. The transition to ultra-low-k films such as BDIII (Black Diamond; k=2.55) dielectrics requires consideration of film sensitivity to compositional modification, polymer interactions at pores, and the effect of diffusion. Use of N2/O2 plasma at 60 ˚C to modify the M1 trench profile has been demonstrated to lower the RC delay by 14% as compared to traditional CO2 plasmas at 60˚C. Use of a DHF solution to clean the etching residue in the dual damascene structure results in >97% yield with a tight range of via chain resistance.

Elaboration of high aspect ratio monocrystalline silicon suspended nanobridges by low temperature alkaline treatment of dry etched trenches

This paper describes the elaboration of high aspect ratio (250), high linear density (500 cm−1) suspended silicon nanobridges into low concentrated alkaline solutions. Trenches were first etched into silicon using the deep reactive ion etching STiGer process. These structures were immersed into low concentrated potassium hydroxide (KOH) or tetramethylammonium hydroxide (TMAH) solutions. The behaviors of KOH and TMAH as silicon trenches etching agents (kinetic and quality of etching) were studied to optimize the silicon nanowires (SiNWs) formation and the elaboration of the suspended structures. The limits of the SiNWs thickness in these conditions were also discussed.