Trench Devices Research Articles

Characterization of TSV-Induced Loss and Substrate Noise Coupling in Advanced Three-Dimensional CMOS SOI Technology

Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps ( μC4's) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is demonstrated up to 40 GHz. In addition to a buried oxide layer, a highly doped N+ epilayer used for deep trench devices in 22-nm CMOS SOI is considered in full-wave electromagnetic simulations. Equivalent circuit models are extracted to assess the impact of noise coupling on active circuit performance. A noise mitigation technique of using CMOS process compatible buried interface contacts is proposed and studied. Simulation results demonstrate that a low-impedance ground return path can be readily created for effective substrate noise reduction in 3-D IC design.

SiC Trench Devices with Ultra Low Ron

SiC devices have the potential to reduce energy losses in high power applications. However SiC devices have yet to achieve ideal performance levels. This paper presents SiC diodes and MOSFETs with advanced trench structures. These devices succeeded in improving performance by reduction of the internal electric field. Trench Schottky diodes are able to reduce forward voltage drop and double-trench MOSFETs show extremely low on-resistance.

SiC Trench Devices with Ultra Low Ron

not Available.

Highly confined and continuous single-mode operation of self-align photonic crystal oxide VCSEL

In this letter, we report on single-mode operation of originally multi-mode oxide VCSEL by using etched photonic crystal air holes and unique trench structure. The device fabrication utilized conventional photolithography; with simplified lithography step of self-aligning the photonic crystal and trench structures to the laser aperture for efficient and vigorous device processing. The fabricated photonic crystal VCSEL with trench device exhibits a single-mode output power of 0.7 mW, threshold current of 3.5 mA, slope efficiency of 0.10 W/A, and continuous single-mode output spectra at wide operating current range. The results are compared with conventional multi-mode oxide VCSEL of similar device geometry. In addition, theoretical analysis is presented for developing further understanding of the photonic crystal VCSEL.

Characteristics of 3D Micro-Structured Semiconductor High Efficiency Neutron Detectors

Silicon diodes with large aspect ratio perforated micro-structures backfilled with <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> LiF show a dramatic increase in neutron detection efficiency beyond that of conventional thin-film coated planar devices. Described in the following are advancements in the technology with increased perforation depths. Perforated silicon diodes with three different etched micro-structure patterns were tested for neutron counting efficiency. The etched micro-structure patterns consisted of circular holes, straight trenches, and continuous sinusoidal waves, with each pattern etched 200 mum deep. Normal incident neutron counting efficiencies were determined to be 9.7%, 12.6%, and 16.2% for circular hole, straight trench, and sinusoidal devices, respectively, at a reverse bias of 3 volts. The perforated neutron detectors demonstrate limited sensitivity to high-energy photon irradiation with a <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sup> Co gamma-ray source. This work is part of on-going research to develop solid-state semiconductor neutron detectors with high detection efficiencies and uniform angular responses.

Enhanced Proton and Neutron Induced Degradation and Its Impact on Hardness Assurance Testing

It is shown that protons and neutrons can induce enhanced degradation in power MOSFETs, including both trench and planar geometry devices. Specifically, large shifts in current-voltage characteristics can be observed at extremely low proton total dose levels (as low as ~ 2 rad(SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )). These shifts can induce significant increases in device ldquooffrdquo state leakage current. Neutron irradiations show similar degradation at equivalent fluence levels, even though neutrons do not deposit dose due to direct ionization. These data suggest that the mechanism responsible for the enhanced degradation is a microdose effect associated with secondary particles produced through nuclear interactions between protons and neutrons and the materials in integrated circuits. The secondary particles deposit enough charge in the gate oxide to induce a parasitic drain to source leakage path in the transistor. Although the results are demonstrated here for only trench and planar geometry power MOSFETs, microdose effects can impact the radiation response of other integrated circuit types. Hardness assurances issues implications are discussed.

A novel single gate MOS controlled current saturated thyristor

A novel single gate MOS controlled current saturation thyristor (MCST) device is proposed. In the on-state the MCST operates in thyristor-like mode at low anode voltage and enters the IGBT-like mode automatically with increasing anode voltage, offering a low on-state voltage drop and current saturation capability. Simulation results based on 6.5 kV trench devices indicate the turn-off energy loss of the MCST is reduced by over 35% compared to the IGBT. The saturation current density of the MCST is strongly dependent on the on-set voltage of the p/sup +/ buffer/n-well junction, leading to its excellent safe operation area (SOA) and making it suitable for high power applications.

Transient 3D heat flow analysis for integrated circuit devices using the transmission line matrix method on a quad tree mesh

This paper presents a 3D transmission line matrix (TLM) implementation for the solution of transient heat flow in integrated semiconductor devices. The implementation uses a rectangular discontinuous mesh to allow for local mesh refinement. This approach is based on a quad tree meshing technique which can have a complex geometry using blocks of varying sizes. Each such block can have a maximum of two adjacent blocks on any vertical side and a maximum of four blocks on the top or bottom.The TLM implementation is based on a physical extraction of a resistance and capacitance network and then the creation of the appropriate TLM matrix. The formulation allows for temperature-dependent material parameters and a non-uniform time stepping.The simulator is first tested using a 2D example of a heat source in a rectangular region. Using this example the numerical error is determined and found to be less than 0.4%. Next, non-linearities are included, and a number of non-uniform time stepping algorithms are tested. Then, a 3D problem is also compared to an analytical solution and again the error is very small. Finally, an example of a full solution of heat flow in a realistic Si trench device is presented.

A 3D thermal simulation tool for integrated devices-Atar

This paper presents a novel three-dimensional (3D) thermal simulation tool for semiconductor integrated devices. The simulator is used to automatically generate an accurate 3D physical model of the device to be simulated from layout information. The simulator produces an appropriate mesh of the device based on a rectangular block structure. The mesh is automatically created such that a fine mesh is produced around heat generation regions, but a moderate number of blocks are used for the entire device. This paper first confirms that the simulator produces an accurate solution to the nonlinear differential equation describing the heat flow. Then model generation from three example technologies (silicon trench, GaAs mesa structures, silicon on insulator) is presented. The potential of the simulator to quickly and easily explore the effect of layout and process variations is illustrated, with the simulation of a two-transistor GaAs power cell as a large example. The program incorporates a transient solver based on a transmission line matrix (TLM) implementation using a physical extraction of a resistance and capacitance network. The formulation allows for temperature dependent material parameters and a nonuniform time stepping. An example of a full transient solution of heat flow in a realistic Si trench device is presented.