Tree Multiplier Research Articles

High Speed and Efficient Wallace Tree Multiplier for Dsp Applications

Multiplier is one of the key and fundamental block in the many applications such as DSP, signal processing etc. In numerous occasions multipliers plays a prominent role to decide the system performance. Out of the several multipliers wallace tree multiplier is one of reliable and occupies the minimal space in digital applications. This work describes the designing of the high performance 8 bit wallace tree multiplier using compressor technique. The multiplier were simulated and estimated its performance using the Vivado.

Design of Parity Preserving Reversible DIF-FFT using 90nm Technology

Reduction of power consumption is the major goal in modern circuit design. Reversible logic gate do not lose any information & thus have zero power dissipation. In all signal processing applications, the most important computation involved is Fast Fourier Transform (FFT). For the fault tolerance computation parity preserving logic can be used .The authors present an efficient parity preserving reversible DIF-FFT using 90nm technology. The implementation involves the design of DIF-FFT with reversible P2RG along with Fredkin gate over different combinations of adders (Carry look ahead adder (CLA), Carry save adders (CSA), Carry skip adder (CSK) & Ripple carry adder (RCA)) & multipliers (Array Multiplier (AM), Carry Save Multiplier (CM), Parallel Multiplier (PM), Wallace Tree Multiplier (WM)). DIF-FFT Architectures of different combinations were coded using Verilog & the same was simulated by Modelsim 6.3f. Parameters such as Hardware Device utilization & Power analysis were done using Quartus II 9.0 with respect to Stratix II device which works on 90nm technology. It was found that DIF-FFT Architecture designed using CSA & CM uses lesser resource utilization whereas architecture designed using CSA & AM has lesser Power dissipation by 72% & 81% respectively.

Efficient design of QCA based hybrid multiplier using clock zone based crossover

Quantum-dot cellular automata (QCA) is an emerging trend in nanotechnology and appropriate for the development of high performance and low power integrated circuit design. Dadda and Wallace tree multipliers are designed by employing CZBCO technique to overcome the crossover issues of geometric design complexity and alignment accuracy and also to achieve high device density. The proposed design of QCA-based Hybrid parallel multiplier consists of decomposing structure that adopts Dadda and Wallace algorithms to optimize the design. In this proposal, N-bit multiplier array is decomposed into four N/2-bit multiplier arrays that are easily constructed by employing both Wallace and Dadda multipliers. The Hybrid multiplier comprising dadda and Wallace tree multiplier uses less number of majority gates and inverters and hence minimizes area, cell count and delay. It has been observed that the QCA cost function of the proposed multiplier better than existing multiplier referred in the literature in terms of energy and speed. Furthermore, the proposed multiplier significantly achieves high device density, lessened clock delay, area and cell count and also to eliminate fabrication difficulty of crossover.

Design Of Dadda And Wallace Tree Multiplier Using Compressor Technique

The work portrays about the design of the Dadda multiplier using 4:2 compressor techniques. The three design techniques, namely conventional design, optimized design using exclusive OR with multiplexer and a further optimized design with less number of critical paths with gates are implemented. All the three designs are implemented in Dadda multiplier and wallace tree multiplier and their performances are compared. The performance metrics measured are area, power consumption, delay and transistor count and these parameters are efficient in dadda multiplier compared to wallace tree multiplier with the above three design techniques. The designs are using behavioral modeling and the results are taken in the 180nm Cadence tool. The result shows that the Dadda multiplier performs better in terms of delay, area and transistor count for all three designs than the Wallace tree multiplier.

Design of Low Power CMOS Array and Tree Multiplier using DSM Technology

currently days, improvement of digital gadgets has been advanced. The requirement for low-manage configuration is additionally turning into a noteworthy problem in superior computerized framework plan programs. A 4 piece CMOS Multiplier has one heart of the chip in dealing with framework structure it require low manipulate usage This paper complicated the multiplier plans of both Array and Tree in 90nm, 65nm, improvements. on this the real segment is CMOS multiplier in labored of adders which makes use of conventional Static CMOS (CSL) logic configuration fashion using the Deep Submicron innovation at various stock voltages. the key point of our mission is to consider the CMOS Array and Tree 4x4 Multipliers concerning Propagation delay, strength dissemination and Transistor check. the usage of CMOS 1 piece complete snake cell for low power is won and is actualized on Array and Tree multiplier and the consequences are investigated for stepped forward strength delay item. The circuit plan and reenactment is finished with MICROWIND tool

High Performance of Wallace Tree Multiplier Stacking Circuit

In this paper one novel double counter proposed which is quick when contrasted with another normal's parallel counters. First, we are designing binary counter using solely full adders, and after with new symmetric stacking method. We are evaluating these two techniques and displaying how the symmetric stacking method is decreasing the x-or gate delays in the essential route of the binary counter. This kind of our proposed counter is very useful in the existing counter based totally Wallace tree multiplier design. With this new symmetry stacking counter we are lowering delay and increasing the performance of multipliers in VLSI circuits. We are designing and simulating our proposed quick binary counter using Xilinx ISE layout suite14.7.

Design of Advanced Multiplier using 15-4 Compressor

The major role of electronics device is to provide low power dissipation and compact area with high speed performance. Among the major modules in digital building blocks system, multiplier is the most complex one and main source of power dissipation. Approximate Computing to multiplier design plays major role in electronic applications, like multimedia by providing fastest result even though it possesses low reliability. In this paper, a design approach of 16 bit Wallace Tree approximate multiplier with 15-4 compressor is considered to provide more reliability. The 16×16 Wallace tree multiplier is synthesized and simulated using Xilinx ISE14.5 software. The multiplier occupies about 15% of total coverage area. The dissipated power and delay of the multiplier are 0.042μw, 3.125ns respectively.

An Efficient Design Approach of ROI Based DWT Using Vedic and Wallace Tree Multiplier on FPGA Platform

<span lang="EN-US">In digital image processing, the compression mechanism is utilized to enhance the visual perception and storage cost. By using hardware architectures, reconstruction of medical images especially Region of interest (ROI) part using Lossy image compression is a challenging task. In this paper, the ROI Based Discrete wavelet transformation (DWT) using separate Wallace- tree multiplier (WM) and modified Vedic Multiplier (VM) methods are designed. The Lifting based DWT method is used for the ROI compression and reconstruction. The 9/7 filter coefficients are multiplied in DWT using Wallace- tree multiplier (WM) and modified Vedic Multiplier (VM). The designed Wallace tree multiplier works with the parallel mechanism using pipeline architecture results with optimized hardware resources, and 8x8 Vedic multiplier designs improves the ROI reconstruction image quality and fast computation. To evaluate the performance metrics between ROI Based DWT-WM and DWT-VM on FPGA platform, The PSNR and MSE are calculated for different Brain MRI images, and also hardware constraints include Area, Delay, maximum operating frequency and power results are tabulated. The proposed model is designed using Xilinx platform using Verilog-HDL and simulated using ModelSim and Implemented on Artix-7 FPGA device.</span>

Implementation of multi-precision floating point divider for high speed signal processing applications

The introduction of fused multiplier and add technique enhances design metrics of floating point (FP) arithmetic operations. Particularly Newton–Raphson (NR) based division algorithm is popular choice to SRT division algorithms. This paper proposes 32-bit FP division using NR computational division technique with pipelining method capable of doing high speed signal processing operations. The proposed divider used as IP core and make it as optimal choice to speed up FP operations. It improves rounding accuracy in addition with reduction in area overhead. The NR computational calculations are implemented by iteratively using 32-bit FP multiplier and adder. The key module used for calculating significand (mantissa) part is 24-bit Wallace tree multiplier using carry save adders. The Wallace multiplier provides higher computational speed, hence, is effectively utilized as a part of FP divider. The proposed pipelined FP divider is fully combinational circuit with clock and data gating applied to reduce the dynamic power consumption, delay and area overhead designed for signal processing applications. It also improves the accuracy of the result. The operands are represented and operated using IEEE 754 standard. The operation and results are validated through simulation using VIVADO software and implemented on Xilinx-7 series, ARTIX field programmable gate array.

Toward Verifying Nonlinear Integer Arithmetic

We eliminate a key roadblock to efficient verification of nonlinear integer arithmetic using CDCL SAT solvers, by showing how to construct short resolution proofs for many properties of the most widely used multiplier circuits. Such short proofs were conjectured not to exist. More precisely, we give n O (1) size regular resolution proofs for arbitrary degree 2 identities on array, diagonal, and Booth multipliers and n O (log n ) size proofs for these identities on Wallace tree multipliers.

Design and Simulation of a Nanoscale Threshold-Logic Multiplier

Multiplication is one of the most important operations in microprocessors and digital signal processing systems. Different multiplier architectures have been proposed in the literature. One of the most widely used architecture is the Wallace tree multiplier. This multiplier is known for its high speed. However, it occupies a large area. In this paper, we used Threshold Logic Gates instead of conventional logic gates to reduce the area. The multiplier was designed in 65nm CMOS technology, and achieved 28% reduction in the number of transistors compared to the one with conventional logic gates. It also achieved a lower power-delay-product.

Design and Implementation of Area Efficient BIST Based Vedic and Wallace Tree Multipliers on FPGA

Design and Implementation of Area Efficient BIST Based Vedic and Wallace Tree Multipliers on FPGA

A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications

Nonvolatile logic implemented by memristor devices is a potential candidate for inherent logic-in-memory architecture. Majority-inverter graph (MIG) logic is a novel logic-structure compared with conventional AND/OR/INV graphs logic. In this brief, MIG logic constructed by memristors is proposed to implement the stateful logic arithmetic. A design of full adders based on MIG logic is proposed, followed by a 4-bit Wallace tree multiplier based on the MIG logic to implement in-situ store. A test chip controlled by a FPGA is designed to verify its feasibility. Compared with multipliers implemented by conventional logic, this method has fewer steps and smaller area, making it suitable for frequent-off and instant-on circuits in IoT applications. The experimental results have proved its significance on the grounds that the 4-bit multiplier only needs 18 processing steps with 51 memristor cells to complete a multiplication arithmetic whereas, by contrast, one conventional 4-bit binary multiplier requires 648 MOSFETs and 124 steps while IMP based 4-bit multiplier logic requires 112 CRS units and 221 steps to operate a multiplying computation.

SYMMETRIC STACKING BINARY COUNTER

High efficient and fast addition of multiple operands is an essential process in any computational units. The power and speed efficiency of multiplier circuits is one of critical importance in the overall performance of microcontrollers and microprocessors. Multiplier circuits are an essential part of an arithmetic logic unit, or a digital signal processor system for performing convolution, image processing, filtering, and other purposes. The binary multiplication of fixedpoint numbers and integers ends up in partial products that is used to provide the ultimate product. Adding those partial products dominates the power consumption and efficiency of the number. A new binary counter design uses 3- bit stacking circuit, which groups all the “1” bits together, to combine pairs of 3- bit stacks into 6- bit stacks through novel symmetric method has been proposed. The bit stacks square measure then reborn to binary counts, producing 6:3 counter circuits with no xor gates on the critical path. This avoidance of xor gates results in faster designs with efficient area and power utilization. Additionally, using the counters present in proposed system in existing counter - based Wallace tree multiplier architectures reduces latency and power consumption for 128 and 64 - bit multipliers. We apply this Counter design in FIR filter Application

A new twelve-transistor approximate 4:2 compressor in CNTFET technology

ABSTRACTPower consumption is a serious concern in the field of digital design. Reducing power supply voltage, power gating, transistor downscaling, voltage over scaling, applying modern technology and approximate computing are some candidate means in reducing power consumption. Among these candidates, approximate computing can generate a trade-off between accuracy and power-delay-area efficiency in error resilient applications. According to Moore’s law together with CMOS problems in nanoscale regime, modern technologies emerge to solve these problems. Among these recent technologies, CNTFET technology is considered as promising. As multiplication is frequently applied in multimedia processing, implementing efficient multipliers constitute critical. Compressors are fundamental elements in reduction tree multipliers and improve their efficiency, thus an improvement in multipliers’ performance. A new 12-transistor approximate 4:2 compressor is proposed here. This new appropriate compressor, in terms of area, power consumption, accuracy and reliability design, is more efficient than its existing counterparts.

Design of high speed Wallace tree multiplier using 8-2 and 4-2 adder compressors

Multiplication is one of the most common arithmetic operations employed in digital systems such as FIR filters and DSP processors but multipliers are the most time, area, and power consuming circuits. Improvement in any of these parameters can be advantageous for improv-ing the efficiency of the circuit. High-speed multiplier which uses the high-speed adder is designed based on the Wallace tree concept in this paper. In this paper first we present an approach towards the reduction of delay in Wallace tree multipliers by using 8:2 and 4:2 adder com-pressors, in the partial product reduction stage. The proposed design is also compared to the Wallace Tree multiplier which uses 4:2 and 8:2 adder compressors in terms of propagation delay. The proposed design enhances speed of the system by 74.1% compared to the conven-tional Wallace Tree multiplier, while 24.1 % reduction was achieved in the delay of the system relative to Wallace tree multiplier with 16-bit adder with one of the 8-2 adder compressors.

High‐performance low‐power approximate Wallace tree multiplier

SummaryMultipliers are considered critical functional units in many systems like Digital Signal Processing (DSP), machine learning, and so on. The overall performance of such systems are dependent on the efficiency of multipliers. However, multipliers are slow and power inefficient components due to their complex circuits, so we aim to reduce their power consumption by relaxing their accuracy requirements and at the same time enhancing their speed. In this paper, we present a fast and a power‐aware multiplier that targets error‐resilient systems. This is achieved by using our proposed approximation algorithm, a hybrid Wallace tree technique for reducing power consumption, and a hybrid ripple‐carry adder for reducing latency. The proposed approximation algorithm is implemented using both a modified bit‐width aware and carry‐in prediction technique, while the proposed hybrid Wallace tree is implemented using high order counters. These proposed algorithms are implemented using HDL language, synthesized, and simulated using Quartus and Modelsim tools. For a 16‐bit multiplier, a mean accuracy of 98.35% to 99.95% was achieved with a 45.77% reduction in power, a 21.48% drop in latency, and a 34.95% reduction in area. In addition, our design performs even better for larger size multipliers (32‐bit multiplier) where a 61.24% reduction in power was achieved, with an 8.74% drop in latency and a 35.24% reduction in area with almost no loss in accuracy.

Design and Analysis of Hybrid Tree Multipliers for Reduction of Partial Products

This paper confers one of the three phases of tree multipliers, i.e. the Partial Product reduction phase. In this paper four types of hybrid tree multipliers are studied and proposed using parallel counters (full adders and half adders) for reduction of Partial Products in multiplication operation.After ANDing the bits of multiplier and multiplicand, the Partial Products are arranged into two groups for reduction, each group uses a different technique for reduction of Partial Products, resulting in a fewer gates than the parent tree reduction techniques. The results of the proposed tree reduction techniques are then tabulated and compared with the parent tree multipliers. The performance comparison is done in terms of number of gate counts of half adder and full adders used in the Partial Product reduction phase. Four types of hybrid tree multipliers are presented using CSA (Carry Save Adder) Array multiplier, Wallace Tree multiplier, Modified Wallace Tree multiplier and Dadda Tree Multiplier. The results show significant reduction in number of full adders and half adders with the slight overhead of increased final addition stage of the hybrid multiplier. The proposed multipliers can prove to be the better choice for digital signal processing designs, image processing designs and processor architecture.

An Efficient MAC Architecture using Multiplier for DSP and DIP Operations

DSP operations are very important part of engineering as well as medical discipline. For the designing of DSP operations Multiplication is play important role to perform signal processing operations. Multiplier is one of the critical components in the area of digital signal processing and hearing aids. So the objective is to design an efficient MAC hardware architecture using multiplier with assistance of compressors by conserving less area, power and delay. In this paper, efficient hardware architecture of MAC using a modified Wallace tree multiplier is proposed. The proposed MAC uses multiplier with novel compressor designs and adders as primitive building blocks for efficient application. Further, the Verilog-HDL coding of 8 bit MAC architecture and their FPGA implementation by Xilinx ISE 14.4 Synthesis Tool on Virtex7 kit have been done. The proposed compressor and adder based architecture used to be applied to MAC unit and in comparison to the previous design MAC unit and verified that the proposed architecture have reduce in terms of area, delay and power. The high performance is obtained by using a new hierarchical structure, these adders are called compressors. These compressors make the multipliers faster as compared to the conventional design used in Engineering, Science & Technology as well as medical discipline.

Analysis and Evaluation of MAC Operators for Fast Fourier Transformation

Arithmetic tasks are broadly utilized in Digital Signal Processing (DSP) applications. In this paper, a streamlined plan of the melded Add-Multiply (FAM) administrators is being investigated for the expanding execution. The direct plan of an AM unit is executed by apportioning a snake and afterward driving its yield to the contribution of a multiplier, increments essentially both region and basic way postponement of the circuit. The immediate recoding of the entirety of two numbers in its MB structure prompts a progressively effective execution of the intertwined Add-Multiply unit contrasted with the regular one, earlier recoding plans depend on complex controls in bit-level, which are actualized by committed circuits in entryway level. This new recoding plan and Modified CSA Tree, diminishes the basic way delay and decreases power utilization. This paper focuses on the extra decrease of dormancy and force utilization of CSA tree multiplier. This is cultivated by the utilization of Modified stall ADD-Multiply administrator and 4:2 compressor adders. Three elective plans of the proposed S-MB approach utilizing regular and marked piece Full Adders (FAs) and Half Adders (HAs) are being investigated as building squares.