Transmission Gate Research Articles

Design of Low Power CMOS Parallel Prefix Adder Cell

Addition is the basic operation in many modern electronic applications. As the fastest adder, parallel prefix adder is of most interest for many circuit designers. For the past few decades, supply voltage and the size of transistors have been reduced tremendously. With more and more transistors being integrated on one single chip, the power issue must be taken care of. Low power adder has been studied for years and many solutions are proposed. In this paper, a new circuit is designed at transistor level. The proposed circuit cell employs transmission gate logic and a MUX-based structure. Simulations are conducted using Cadence® Virtuoso Spectre Simulator. The result shows that the new adder demonstrates a better performance in terms of power dissipation, which saves more than 5% energy compared with Conventional CMOS logic adders with different word length.

Conventional and sub-threshold operation regimes of CMOS digital circuits

In this paper a comparison of static and dynamic parameters of CMOS logic circuits operated in standard and sub-threshold regimes is presented. Analytic models of logic threshold voltage, logic delay and power consumption are derived for the sub-threshold operation regime. Certain analytic models analogies between these two regimes are shown. Threshold voltages of inverter, NAND and NOR logic circuits depend on the same parameters in both regimes. These circuits functional differences appear as a consequence of the drain current analytic model differences in the strong and weak inversion regimes. In both of these regimes, the inverter and transmission gate temperature characteristics are analyzed. Analytic models are verified by PSPICE simulation using the BSIM3 transistor models of the 0.18 μm CMOS technology process.

A hybrid memristor-CMOS XOR gate for nonvolatile logic computation

Memristor-based logic gates that can execute memory and logic operations are promising elements for building non-von Neumann computation architecture. In this paper, we proposed a fundamental hybrid memristor-CMOS nonvolatile XOR Boolean logic block with one memristor and four voltage-controlled switches, such as MOSFET or transmission gate. The Ag/Ag5In5Sb60Te30/Ta structure memristors with bipolar resistive switching behaviors were utilized to experimentally demonstrate the XOR function of the block. Further, with the XOR logic block as a basis, a full adder as an extensive circuit example was designed and verified by HSPICE simulation. Our work shows logic-in-memory capabilities with memristors, and provides an alternative way to implement nonvolatile logic operations and construct parallel computation systems.

Combined Gate Replacement and Transmission Gate Based Logic Insertion Algorithm for Leakage Optimization in VLSI Circuits

Combined Gate Replacement and Transmission Gate Based Logic Insertion Algorithm for Leakage Optimization in VLSI Circuits

Bias dependence of TID induced single transistor latch for 0.13 μm partially depleted SOI input/output NMOSFETs

In this work, single transistor latch effects induced by total dose irradiation for 0.13μm partially depleted silicon-on-insulator (PDSOI) n-type metal-oxide-semiconductor field effect transistors (NMOSFETs) were investigated. The front gate transfer characteristics under different bias configurations with forward and reverse gate voltage sweep are characterized to evaluate the latch phenomenon. The results indicate that transmission–gate (TG) bias is the worst case bias for total dose induced latch, and the onset drain voltage required for latchup degrades as the irradiation level increased. Experiments and 2D simulations are performed to analyze the positive trapped charge in the buried oxide (BOX) and its impact on the latch effect. It is demonstrated that the irradiation can enhance the impact ionization and thereby make the device more sensitive to latchup, especially at negative gate voltage. Moreover, the radiation induced coupling effect between the front gate and back gate can make the PDSOI devices in our experiments behave like the fully depleted (FD) ones.

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 $\mu $ W) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 $\mu $ W and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79- $\mu $ W (53.36- $\mu $ W) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.

Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction

This paper presents a hybrid non-volatile (NV) SRAM cell with a new scheme for soft error tolerance. The proposed cell consists of a 6T SRAM core, a resistive RAM made of a transistor and a Programmable Metallization Cell. An additional transistor and a transmission gate are utilized for selecting a memory cell in the NVSRAM array. Concurrent error detection (CED) and correction capabilities are provided by connecting the NVSRAM array with a dual-rail checker; CED is accomplished using a dual-rail checker, while correction is accomplished by utilizing the restore operation, such that data from the non-volatile memory element is copied back to the SRAM core. The simulation results show that the proposed scheme is very efficient in terms of numerous figures of merit.

Modeling Static Delay Variations in Push–Pull CMOS Digital Logic Circuits Due to Electrical Disturbances in the Power Supply

Soft errors can occur in digital integrated circuits (ICs) as a result of an electromagnetic disturbance, such as might result from an electrical fast transient (EFT). Many soft errors come from changes in propagation delays through digital logic, which are caused by changes in the on-die power supply voltage. An analytical model was developed to predict timing variations in digital logic as a result of variations in the power supply voltage. The derivation of the analytical delay model is reported. The model was validated experimentally by applying EFTs to a ring oscillator built in a test IC. The predicted and measured ring oscillator frequencies (or periods) agreed within a relative error of less than 2.0%. To further validate the approach, the model was applied to test the response of more complex circuits consisting of NAND/NOR logic gates, binary adders, dynamic logic gates, and transmission gates. The circuits were fabricated on a 0.5 μm test IC and simulated on two additional process technologies (0.18 μm and 45 nm). The model performed well in each case with a maximum relative error of 5.6%, verifying the applicability of the model for analyzing complex logic circuits within a variety of process technologies. The proposed delay model can be used by IC design engineers to predict and understand the change in the propagation delay through logic circuits due to the disturbed power supply.

A Low-Leakage Body-Guarded Analog Switch in 0.35- <inline-formula> <tex-math notation="LaTeX">$\mu\mbox{m}$</tex-math></inline-formula> BiCMOS and Its Applications in Low-Speed Switched-Capacitor Circuits

A low-leakage body-guarded analog switch (BG-switch) for slow switched-capacitor (SC) circuits is presented. The improvement of accuracy in SC circuits employing BG-switches is demonstrated by comparing their performance with counterparts employing conventionally biased CMOS switches in three applications: sample-and-hold (S/H) amplifier, SC amplifier, and high-voltage drain-extended MOSFET (DEMOS). The leakage currents of BG-switch-enabled circuits are characterized across process variations and different operation voltages in all demonstrated applications. With nominal output voltages at room temperature, the average absolute leakage current of BG-switch-enabled S/H amplifier (12.02 aA), SC amplifier (54.52 aA), and DEMOS (53.71 fA) show leakage current improvement of 21, 28, and 17 dB, respectively, compared with equivalent circuits utilizing transmission gates (TGs). BG-switch-enabled S/H circuits and SC amplifiers with average performance exhibit lower leakage currents up to 100 °C compared with TG-enabled circuits. The demonstrated applications utilizing BG-switches were fabricated in a standard 0.35- $\mu\mbox{m}$ BiCMOS process.

Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

Abstract This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (−0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

Monolithic Integration of Si<sub>3</sub>N<sub>4</sub> Microring Filters With Bulk CMOS IC Through Post-Backend Process

An experimental demonstration of backend monolithic integration of Si3N4 microring filter with bulk complementary metal–oxide–semiconductor (CMOS) integrated circuit (IC) is accomplished using CMOS postbackend process. Si3N4 photonic layer is integrated on the top surface of CMOS IC die which is manufactured in commercial CMOS foundry. The Si3N4 microring filters in photonic layer are fabricated using CMOS postbackend process with only two additional lithography steps. The filters can be thermally tuned by microheaters integrated in CMOS circuits, which are controlled by transmission gates. A measured optical transmission spectrum and a dynamic characteristic of the integrated filter are provided.

An Area-Efficient Clamp Based on Transmission Gate Feedback Technology for Power Rail Electrostatic Discharge Protection

An area-efficient clamp based on transmission gate feedback technology is presented for power rail electrostatic discharge (ESD) protection. With this novel design, only a time constant of 10 ns is required for triggering and keeping the clamp turn-on during an ESD event. Full chip ESD protection with this design can endure a human body model pulse of 4500 V. Compared with the conventional clamp with the same area, the proposed clamp has 28% improvement in ESD protection capability. Simulation results show that there is no mistriggering problem caused by power-on pulse and power noise.

Low-Voltage CMOS Switch for High-Speed Rail-To-Rail Sampling

Sampling switches have a dominant role in switched-capacitor circuits and analog-to-digital convertors. Since they act as input gates, their nonlinearities directly degrade the quality of the input signals. The scaling-down trend of CMOS technology and increasing demands for high-speed and power-efficient circuits pose design challenge in high-speed sampling switches for low-voltage applications. To address this issue, an optimized CMOS switch is proposed in this paper consisting of a bootstrapped NMOS switch and a boosted PMOS switch as a transmission gate. By utilizing this technique, the nonlinearity resulting from the threshold voltage variation (body effect) of NMOS switch is mitigated, considerably. To evaluate the proposed switch, it is designed in 0.18 $$\upmu \hbox {m}$$μm CMOS process technology. According to the obtained simulation results, this switch can achieve total harmonic distortion of $$-$$-78.81 and $$-$$-62.99 dB in 100 MS/s at $$V_\mathrm{dd}$$Vdd = 1 Volt and 50 MS/s at $$V_\mathrm{dd}$$Vdd = 0.8 V, respectively.

Power and Area Efficient Design of 6T Multiplexer using Transmission Gate Logic

The main issue in designing of VLSI circuits is power consumption and area requirement In this paper Multiplexer circuit is proposed with the help of transmission gate logic using 6 transistors. Different design methodologies are used for designing of multiplexer layout. Multiplexer is essential circuit for different field of network and communication. Multiplexer requires less number of transistors using transmission gate logic. The main concerned of this paper is to reduce area, power consumption and complexity of Multiplexer using different design methodologies.

Eight-FinFET Fully Differential SRAM Cell With Enhanced Read and Write Voltage Margins

An eight-FinFET fully differential SRAM cell is proposed in this paper to achieve stronger data stability and enhanced write ability. The p-type transistors are used for data access during read operations and transmission gates are employed to force new data into the cell during write operations. At the nominal process corner, the proposed SRAM cell enhances the read data stability, write voltage margin, and write data transfer speed by up to 2.7×, 15.8%, and 76%, respectively, while consuming similar leakage power as compared with the previously published six-FinFET fully differential SRAM cells in 15-nm FinFET technology. Under isodata stability, the proposed SRAM cell allows the lowering of the power supply voltage by up to 44.3% as compared with the other SRAM cells that are investigated in this paper.

Wide-Input Range Dual Mode PWM / Linear Buck Converter with High robustness ESD Protection Circuit

This paper proposes a high-efficiency, dualmode PWM / linear buck converter with a wide-input range. The proposed converter was designed with a mode selector that can change the operation between PWM / linear mode by sensing a load current. The proposed converter operates in a linear mode during a light load and in PWM mode during a heavy load condition in order to ensure high efficiency. In addition, the mode selector uses a bit counter and a transmission gate designed to protect from a malfunction due to noise or a time-delay. Also, in conditions between -40 °C and 140 °C, the converter has variations in temperature of 0.5mV/°C in the PWM mode and of 0.24 mV/°C in the linear mode. Also, to prevent malfunction and breakdown of the IC due to static electricity, the reliability of IC was improved by embedding a self-produced 8 kVclass(Chip level) ESD protection circuit of a Psubstrate Triggered SCR type with high robustness characteristics.

DESIGN OF AREA AND POWER EFFICIENT HALF ADDER USING TRANSMISSION GATE

This paper gives an idea to reduce power and surface area of half adder circuit using very popular technique i.e. transmission gate. An adder is a digital circuit that performs addition of two numbers. In many computers and other kind of processors, adders are used not only in arithmetic logic unit but also in other parts of the processors where they are used to calculate addresses, table indices and similar operations .in this paper two bit addition has been done using conventional and transmission gate level and power, area and number of transistors are the scope of comparison. According to the simulation result, power and area are reduced by 55.35 % and 40.269% respectively when the circuit is implemented by transmission gate .thus transmission gate has become a very popular and useful technique to implement digital circuits which help to reduce power, surface area as well as number of transistors.

Ultra Low Power MUX Based Compressors for Wallace and Dadda Multipliers in Sub-threshold Regime

The computing efficiency of modern column compression multipliers offers a highly efficient solution to the binary multiplication problem and is well suited for VLSI implementations. The various analyses are established more on compressors circuits particularly with Multiplexer (MUX) design. Conventionally, compressors are anatomized into XOR gate and MUX design. In this study, fully MUX based compressors, utilizing the CMOS transmission gate logic have been proposed to optimize the overall Power-Delay-Product (PDP). The proposed compressors are also used in the design and comparative analysis of 4×4-bit and 8×8-bit Wallace and Dadda multipliers operating in sub-threshold regime. The multipliers based on the proposed compressor designs have been simulated using 45 nm CMOS technology at various supply voltages, ranging from 0.3 to 0.5 V. The result shows on an average 89% improvement in the PDP of the proposed compressor blocks, when compared with the existing published results in sub-threshold regime. The multipliers designed using the proposed compressor blocks also show improved results.

Transmission Gate base Programmable Binary Incrementer Decrementer

We can use a high-speed parallel adder in incrementer / decrementer to improve the operating speed which can count up or count down from the loaded value by one step in one clock cycle. For this, design of a faster and highly reliable adder is of major importance. Thus, much effort has been invested in the research that has led to faster and more efficient ways to perform this operation. To prove the efficiency of the proposed method, the circuit is simulated in pass transistor CMOS 50nm technology and some simulation parameters are calcultes in the layout of the circuit. The binary decrementer reduces the stored binary data in memopry or register by ‘1’. This can be done by using 2’s complement method by using XOR gates which convert binary data in 1’s complement and then by addition of binary ‘1’ it can be converted to 2’s complement form. It is made by cascading ‘n’ full adders for ‘n’ number of bits i.e. the storage capacity of the register to be decremented. Hence, a 4-bit binary decrementer requires 4 cascaded half adder circuits. This paper presents the eight bit CMOS base incrementer and decrementer logic design using eight bit adder and subtractor. The parametric simulation is done on MICROWIND layout editor tool. The any conventional static CMOS adder with pullup and pulldown logic requires 32 MOSFET whereas our design adder requires 30 MOSFETs. Our design methodology is based on static CMOS logic and transmission gate logic to achieve smaller delays, reduce power dissipation and optimized area.

Scan Test of Die Logic in 3-D ICs Using TSV Probing

Prebond testing of through-silicon-vias (TSVs) and die logic is a significant challenge and a potential roadblock for 3-D integration. Built-in self-test solutions introduce considerable die area overhead. Oversized probe pads on TSVs to provide prebond test access limit both test bandwidth and TSV density. This paper presents a solution to these problems, allowing a probe card to contact TSVs without the need for probe pads, enabling both TSV and prebond scan test. Several possible prebond scan test configurations are shown-they provide varying degrees of test parallelism under design constraints. HSPICE simulations are performed on two logic-on-logic 3-D benchmarks. Results show that the ratio of the number of probe needles available for test access to the number of prebond scan chains determines which prebond scan configuration results in the shortest test time. Maximum prebond scan-in and scan-out shift-clock speeds are determined for dies in a benchmark 3-D design as a function of driver strength and transmission gate width. These clock speeds show that prebond scan test can be performed at a speed that is comparable with scan testing of packaged dies. The maximum clock speed can also be tuned by changing the drive strength of the probe and on-die drivers of the TSV network. Estimates are also provided for peak and average power consumption during prebond scan test for both a high-power pattern per scan chain and an average power pattern per scan chain. On-die area overhead for the proposed method is estimated to be between 1.0% and 2.9% per die for two 3-D benchmarks.