Transition Metal Dichalcogenide Transistors Research Articles

Nb Doping and Alloying of 2D WS2 by Atomic Layer Deposition for 2D Transition Metal Dichalcogenide Transistors and HER Electrocatalysts.

We utilize plasma-enhanced atomic layer deposition to synthesize two-dimensional Nb-doped WS2 and NbxW1-xSy alloys to expand the range of properties and improve the performance of 2D transition metal dichalcogenides for electronics and catalysis. Using a supercycle deposition process, films are prepared with compositions spanning the range from WS2 to NbS3. While the W-rich films form crystalline disulfides, the Nb-rich films form amorphous trisulfides. Through tuning the composition of the films, the electrical resistivity is reduced by 4 orders of magnitude compared to pure ALD-grown WS2. To produce Nb-doped WS2 films, we developed a separate ABC-type supercycle process in which a W precursor pulse precedes the Nb precursor pulse, thereby reducing the minimum Nb content of the film by a factor of 3 while maintaining a uniform distribution of the Nb dopant. Initial results are presented on the electrical and electrocatalytic performances of the films. Promisingly, the NbxW1-xSy films of 10 nm thickness and composition x ≈ 0.08 are p-type semiconductors and have a low contact resistivity of (8 ± 1) × 102 Ω cm to Pd/Au contacts, demonstrating their potential use in contact engineering of 2D TMD transistors.

Van der Waals Contact for Two-Dimensional Transition Metal Dichalcogenides.

Two-dimensional (2D) transition metal dichalcogenides (TMDs) have emerged as highly promising candidates for next-generation electronics owing to their atomically thin structures and surfaces devoid of dangling bonds. However, establishing high-quality metal contacts with TMDs presents a critical challenge, primarily attributed to their ultrathin bodies and delicate lattices. These distinctive characteristics render them susceptible to physical damage and chemical reactions when conventional metallization approaches involving "high-energy" processes are implemented. To tackle this challenge, the concept of van der Waals (vdW) contacts has recently been proposed as a "low-energy" alternative. Within the vdW geometry, metal contacts can be physically laminated or gently deposited onto the 2D channel of TMDs, ensuring the formation of atomically clean and electronically sharp contact interfaces while preserving the inherent properties of the 2D TMDs. Consequently, a considerable number of vdW contact devices have been extensively investigated, revealing unprecedented transport physics or exceptional device performance that was previously unachievable. This review presents recent advancements in vdW contacts for TMD transistors, discussing the merits, limitations, and prospects associated with each device geometry. By doing so, our purpose is to offer a comprehensive understanding of the current research landscape and provide insights into future directions within this rapidly evolving field.

Engineering TiOx interlayers in high vacuum for Al-contacted MoSe2 transistors

We present an enhanced performance of MoSe2 transistors via sequentially depositing Ti and Al in high vacuum to establish TiOx interlayers positioned between the MoSe2 channel and Ti/Al contacts. Transmission electron microscopy analysis revealed the presence of TiOx at the MoSe2/Ti interface. While MoSe2 transistors exhibited poor device performance in the absence of a TiOx interlayer, the introduction of a TiOx interlayer yielded a notable transistor performance, including an on/off ratio of ∼105, a field-effect mobility of ∼40 cm2 V−1 s−1, and a contact resistance of ∼100 kΩ μm. These enhancements were attributed to the beneficial effects of Fermi level unpinning and interfacial doping facilitated by TiOx interlayers. These results underscore the feasibility of incorporating TiOx interlayers to enable the use of conventional Al contacts in MoSe2 transistors, delivering significant implications for enhancing the performance of transition metal dichalcogenide transistors.

Cascaded Logic Gates Based on High-Performance Ambipolar Dual-Gate WSe2 Thin Film Transistors.

Ambipolar dual-gate transistors based on low-dimensional materials, such as graphene, carbon nanotubes, black phosphorus, and certain transition metal dichalcogenides (TMDs), enable reconfigurable logic circuits with a suppressed off-state current. These circuits achieve the same logical output as complementary metal-oxide semiconductor (CMOS) with fewer transistors and offer greater flexibility in design. The primary challenge lies in the cascadability and power consumption of these logic gates with static CMOS-like connections. In this article, high-performance ambipolar dual-gate transistors based on tungsten diselenide (WSe2) are fabricated. A high on-off ratio of 108 and 106, a low off-state current of 100 to 300 fA, a negligible hysteresis, and an ideal subthreshold swing of 62 and 63 mV/dec are measured in the p- and n-type transport, respectively. We demonstrate cascadable and cascaded logic gates using ambipolar TMD transistors with minimal static power consumption, including inverters, XOR, NAND, NOR, and buffers made by cascaded inverters. A thorough study of both the control gate and the polarity gate behavior is conducted. The noise margin of the logic gates is measured and analyzed. The large noise margin enables the implementation of VT-drop circuits, a type of logic with reduced transistor number and simplified circuit design. Finally, the speed performance of the VT-drop and other circuits built by dual-gate devices is qualitatively analyzed. This work makes advancements in the field of ambipolar dual-gate TMD transistors, showing their potential for low-power, high-speed, and more flexible logic circuits.

Solution-Processed 2D Transition Metal Dichalcogenides: Materials to CMOS Electronics

ConspectusTwo-dimensional (2D) semiconducting transition metal dichalcogenides (TMDs) have demonstrated exceptional potential as materials for future complementary metal-oxide-semiconductor (CMOS) technology. This is primarily because of their atomic thickness and excellent electrical and mechanical properties. With advancements in fabrication technology, electronic devices based on 2D TMD materials have rapidly progressed from isolated units for scientific experimentation to integrated circuits with practical applications. Among the different production methods, the solution-processing of 2D TMD nanomaterial dispersions offers the distinct advantages of low-temperature processing and cost-effective manufacturing for large-scale flexible and wearable electronics. A wide range of 2D nanoflake inks with versatile electronic properties can be assembled into atomic-thick thin films with dangling-bond-free van der Waals interfaces between adjacent nanoflakes. Furthermore, direct printing techniques can easily integrate multifunctional devices, such as n-type and p-type transistors, into CMOS devices and more complex integrated circuits. Despite these benefits and previous accomplishments, the field of solution-processed CMOS electronics using 2D TMD semiconducting materials is in its early stages of development and requires further research. One of the current challenges is the production of scalable and high-purity 2D semiconductor mono- and few layers with large lateral sizes and narrow thickness distribution. The field-effect mobility of solution-processed 2D TMD transistors remains lower than that of the transistors manufactured using mechanical exfoliation and chemical vapor deposition methods. In particular, limited research has been conducted on solution-processed p-type 2D TMD transistors. As a result, solution-processed CMOS devices using n-type and p-type 2D TMD transistors are scarce. In this Account, we provide an overview of the recent progress in the field of solution-processed CMOS electronics employing 2D TMD materials. First, we introduce the basic liquid exfoliation methods, such as sonication-assisted exfoliation and molecular intercalation methods, that are commonly utilized to prepare 2D TMD dispersions. In addition, we discuss the production of monolayer 2D materials, which serve as the building blocks for fabricating atomic-thick thin films. Subsequently, we review the typical techniques for depositing 2D inks, including spin coating, drop casting, and inkjet printing. Furthermore, we outline the thin-film patterning process for each technique, which is crucial for integrating multifunctional materials in CMOS devices. Subsequently, we focus on the recent advancements in solution-processed 2D TMD transistors. Furthermore, we explore the various factors that can improve the performance of the devices with regard to charge transport and charge traps. Afterward, we highlight notable applications of solution-processed CMOS technology, such as logic circuits and ring oscillators. Finally, we provide an overview of the challenges and opportunities in the development of solution-processed 2D materials and the integration of multifunctional devices for the advancement of CMOS electronics. This Account aims to provide a comprehensive guide for readers, offering both a broad overview and an in-depth insight into solution-processed 2D material-based electronics, covering a wide range of topics from the preparation of 2D TMD ink to device fabrication and CMOS applications. Therefore, this Account is expected to drive further progress and advancements in this field and promote the realization of practical applications.

Improved Self-Heating in Short-Channel Monolayer WS2 Transistors with High-Thermal Conductivity BeO Dielectrics.

Two-dimensional semiconducting transition metal dichalcogenides (TMDs) enable ultimate channel length scaling of transistor technology due to their atomic-thin body nature, which also brings the challenge of a pronounced self-heating effect inside the ultrathin channel. In particular, high current density under high electric field could lead to negative differential resistance behavior due to self-heating, not only limiting the current carrying capability of the TMDs transistors but also leading to severe reliability issues. Here, we report high-performance monolayer WS2 transistors on a high-thermal-conductivity BeO dielectric with effective suppression of the self-heating effects, eliminating the negative differential resistance behavior at high field, as observed in the case of the HfO2 dielectric. The monolayer CVD WS2 device on BeO with a 50 nm channel length exhibits a record-high on-state current of 325 μA/μm, transconductance (gm) of 150 μS/μm, and a on/off ratio of 1.8 × 108 at Vds = 1 V, far exceeding previous results.

Unanticipated Polarity Shift in Edge-Contacted Tungsten-Based 2D Transition Metal Dichalcogenide Transistors

Creating metal edge contacts in transition metal dichalcogenide (TMD) transistors is a promising path to advance transistor miniaturization for future technology nodes. Current experimental demonstrations nearly exclusively focus on MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as the channel material. Here, we create edge-contacted WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> transistors using a convergent Ar <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> ion beam source integrated within an e-beam evaporator chamber for <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-situ</i> processing. An unanticipated polarity shift was observed compared to top-contact behavior for Ti-WS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> devices, which displayed p-type conduction. Meanwhile, three distinct metal contact materials yielded comparable p-branch-dominant performance on WSe <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . Transmission electron microscope (TEM) imaging with energy dispersive spectroscopy (EDS) analysis indicated the existence of a residual layer of W (and chalcogen atoms to a lesser extent) beneath the metal contacts, even though the substrate was over-etched. The images presented a physically pure edge interface. This intriguing etching effect could carry significant implications for the design of tungsten-based, edge-contacted TMD transistors.

Enhanced performance of multilayer MoS2 transistors encapsulated with a photoresist

We report the enhanced performance of multilayer MoS2 transistors by AZ® 5214E photoresist encapsulation. The MoS2 transistors with SiO2 bottom-gate dielectrics exhibited an average increase of 4× in the on/off-current ratio and a 50% increase in the field-effect mobility after photoresist encapsulation. The Y-function method further showed a decrease of 87% in the contact resistance and a 30% increase in the intrinsic carrier mobility, suggesting that photoresist encapsulation provides not only n-type doping but also dielectric screening. The Raman spectra of the photoresist-encapsulated MoS2 also suggest n-type doping, which may be due to the electropositive hydroxyl groups in the photoresist. The operation of the photoresist-encapsulated MoS2 transistors remained stable in ambient air for at least one month. These results demonstrate that simple photoresist encapsulation can be an effective performance booster of MoS2 and other transition metal dichalcogenides transistors.

Directly grown Te nanowire electrodes and soft plasma etching for high-performance MoTe2 field-effect transistors

Contact tailoring for two-dimensional (2D) transition metal dichalcogenides (TMDs) to achieve high-performance devices remains a challenge. Fermi-level pinning at 2D TMD–metal contacts leads to a Schottky barrier for contacts. In addition, when there are no dangling bonds between 2D TMDs and contacts, the contact resistance increases. In this study, Te nanowire (NW) contacts were employed for a MoTe2 p-channel of enhancement mode field-effect transistor (FET). The Te NWs were directly grown on 2D MoTe2 film by metal–organic chemical vapor deposition and selectively etched by a soft plasma etching technique for contact isolation. Using t-Te NW contacts on three-atomic-layer MoTe2, a highly effective field-effect mobility of 543.9 cm2/Vs, as well as ohmic contacts and atomic hybridization, was achieved. These results of t-Te NW electrodes provide a novel device structure for p-type 2D TMD transistors with excellent performances. Further, they offer a practical guideline for wafer-scale 2D TMD-based high-performance electronics and optoelectronics.

Frequency Doubler and Universal Logic Gate Based on Two-Dimensional Transition Metal Dichalcogenide Transistors with Low Power Consumption.

Two-dimensional transition metal dichalcogenide semiconductors are very promising candidates for future electronic applications with low power consumption due to a low leakage current and high on-off current ratio. In this study, we suggest a complementary circuit consisting of ambipolar WSe2 and n-MoS2 field-effect transistors (FETs), which demonstrate dual functions of a frequency doubler and single inversion AND (SAND) logic gate. In order to reduce the power consumption, a high-quality thin h-BN single crystal is used as a gate dielectric that leads to a low operating voltage of less than 5 V. By combining the low operating voltage with a low operating current in the complementary circuit, a low power consumption of 300 nW (a minimum of 10 pW) has been achieved, which is a significant improvement compared to the tens of μW consumed by a graphene channel. The complementary circuit shows the effective frequency doubling of the input with a dynamic range from 20 to 100 Hz. Furthermore, this circuit satisfies all the truth tables of a SAND logic gate that can be used as a universal logic gate like NAND. Considering that the NAND logic gate generally consists of four transistors, it is significantly advantageous to implement the equivalent circuit SAND logic gate with only two FETs. Our results open up possibilities for analog- and logic-circuit applications based on low-dimensional semiconductors.

Ambipolar device simulation based on the drift-diffusion model in ion-gated transition metal dichalcogenide transistors

Ionic gating is known as a powerful tool for investigation of electronic functionalities stemming from low voltage transistor operation to gate-induced electronic phase control including superconductivity. Two-dimensional (2D) material is one of the archetypal channel materials which exhibit a variety of gate-induced phenomena. Nevertheless, the device simulations on such ion-gated transistor devices have never been reported, despite its importance for the future design of device structures. In this paper, we developed a drift-diffusion (DD) model on a 2D material, WSe2 monolayer, attached with an ionic liquid, and succeeded in simulating the transport properties, potential profile, carrier density distributions in the transistor configuration. In particular, the simulation explains the ambipolar behavior with the gate voltage comparable to the band gap energy, as well as the formation of p-n junctions in the channel reported in several experimental papers. Such peculiar behavior becomes possible by the dramatic change of the potential profiles at the Schottky barrier by the ionic gating. The present result indicates that the DD model coupled to the Poisson equation is a fascinating platform to explain and predict further functionalities of ion-gated transistors through including the spin, valley, and optical degrees of freedom.

Layered TMDFETS for Nano Devices: A Short Review

Two-dimensional semiconducting materials of the transition-metal-dichalcogenide (TMD) family, such as MoS\({}_{2}\) and WSe\({}_{2}\), have been intensively investigated in the past few years, and are considered as workable contenders for next-generation electronic devices. In this very brief review, we provide an evaluation of devices based on monolayer and multi layer two-dimensional materials, outlining their prospects as a technological option for low power transistor designs. Our study revealed that the two dimensional transition-metal-dichalcogenide are versatile materials which may be used as a single layer or multi layered with diverse properties enabling to suit a wide range of low power applications. Further study divulges that experimental investigations of monolayer TMD transistors encourage workers with excellent carrier mobilities required for low power applications, whereas multilayer TMD transistors reveal WS\({}_{2}\) to be an excellent channel material for making of high performance FET required for energy efficient electronic applications. We understand that this work will provide an important step towards the design and performance evaluation of FETs in low power applications based on two-dimensional materials. Further, the results obtained due to the TMDs so far, prove beneficial to both states of FET operation i.e. ON state and OFF state, when compared to conventional materials.

Static characteristics of CMOS digital circuit based on transition metal dichalcogenide transistors

Static characteristics of digital combinational logic circuits and Schmitt triggers based on two-dimensional (2D) transition metal dichalcogenides (TMDs) have been systematically explored. Selenide tungsten (WSe2) transistors act as the P type metal oxide semiconductor (PMOS). Molybdenum disulfide (MoS2) transistors play the role as N type metal oxide semiconductor (NMOS). Based on the circuit simulations, we find that the output of the complementary metal oxide semiconductor (CMOS) inverters and Schmitt triggers can approach the supply voltage (VDD) and ground (GND), respectively. The key performance indexes of the two digital circuits have been studied with the change of the device parameters. The simulation results indicate that a thinner gate oxide thickness and a higher dielectric permittivity gate oxide material can increase the noise margin of the inverters. Besides, different width ratios of PMOS and NMOS can influence the noise margin of inverters. An inverter with a large PMOS whose width is 64 nm and a small NMOS whose width is 32 nm can improve the low level noise margin, but reduce the high level noise margin. In addition, a gate oxide thickness of 2.8 nm can broaden the hysteresis window of the Schmitt triggers obviously. The output curves of the Schmitt triggers change slightly with different gate oxide materials. The hysteresis window of the Schmitt triggers becomes narrow with decreasing of the supply voltage. The present work could help to design the standard cells with different requirements and improve the performance of digital integrated circuits using TMDs transistors.

On the limit of defect doping in transition metal oxides

Transition metal oxides are being increasingly used in many applications like nonvolatile memory, contacts to transition metal dichalcogenide transistors and photovoltaics, and thin-film transistors, to name a few, because the conductivity can be tuned by defect doping. The mechanism of conduction through substoichiometric oxides is however not well understood. Earlier studies attributed the conduction in substoichiometric oxides to Poole–Frenkel emission. But the assumptions underlying the Poole–Frenkel model break down in thin dielectrics and when a broad range of temperature is considered. The authors model the conduction through substoichiometric nickel oxide (NiOx) using a kinetic Monte-Carlo framework based on trap-assisted tunneling (TAT), by studying devices made of metal/NiOx/Si stacks. Modeling the temperature dependence of I–V characteristics enables the extraction of the trap parameters, like trap ionization energy and trap relaxation energy. The authors study the effects of the UV/ozone treatment, which has been shown to reduce the resistivity of NiOx by orders of magnitude, as well as the choice of metal electrode on the trap properties. The high trap relaxation energy (∼1.6 eV) is identified as an important factor in limiting the effectiveness of defect doping in NiOx, because it hinders the carrier emission step of the TAT process. The relaxation energy is another design knob that can be used when screening oxide candidates for various applications.

Charge-Based Modeling of Transition Metal Dichalcogenide Transistors Including Ambipolar, Trapping, and Negative Capacitance Effects

In this paper, we present a charge-based compact model for transition metal dichalcogenide (TMD)-based thin-channel field-effect transistor. In model development, first, charge densities at the source and drain terminals are calculated in terms of the applied gate and drain voltages. Calculated charge densities are then used to develop a charge-based drain-current model. Effects of interface traps, ambipolar current behavior, and negative capacitance are then included in the developed drain-current model in terms of charge densities. Predictions of the proposed model are verified by the simulation and experimental data of the TMD channel material-based n-type and p-type MOSFETs.

2D MoSe2 Field Effect Transistor with Small Threshold Voltage for Piezoelectric Touch Sensor Applications

Being implemented as an active component in the circuits, two dimensional (2D) transition metal dichalcogenide (TMD) transistors have two kinds of difficulties. First, regardless of carrier type, threshold voltage (Vth) of TMD 2D field effect transistors (FETs) is located far away from 0 V. Second, gate bias induced hysteresis exists in general 2D TMD transistors, causing an unstable operation of FETs. Here, we have fabricated stable n-channel MoSe2 FETs with a relatively small Vth of -5 V and minimized-hysteresis of 0.5 V. And we have checked the stable operation by integrating a smart touch sensor circuit composed of piezoelectric P(VDF-TrFE) polymer, the MoSe2 FET, and organic light emitting diode (OLED). To minimize the Vth and gate voltage hysteresis of 2D FET, we inserted ultrathin (8.46 nm) polystyrene (PS)-brush layer between MoSe2 channel and 50 nm-thin Al2O3 dielectric. Our MoSe₂ FET has showed a maximum drain-current (ID) of ~9 μA at VDS of 1 V along with a high linear mobility of 11.2 cm2/Vs. In the analogue touch sensor circuit gated by piezoelectric film of large scale Al/50 μm-thick P(VDF-TrFE)/ITO/glass, the MoSe₂ FET exhibites high ON/OFF ratio and ON-state ID which quite well demonstrated OLED pixel operation. Figure 1

Analyzing the Carrier Mobility in Transition‐Metal Dichalcogenide MoS2 Field‐Effect Transistors

Transition‐metal dichalcogenides (TMDCs) are an important class of two‐dimensional (2D) layered materials for electronic and optoelectronic applications, due to their ultimate body thickness, sizable and tunable bandgap, and decent theoretical room‐temperature mobility. So far, however, all TMDCs show much lower mobility experimentally because of the collective effects by foreign impurities, which has become one of the most important limitations for their device applications. Here, taking MoS2 as an example, the key factors that bring down the mobility in TMDC transistors, including phonons, charged impurities, defects, and charge traps, are reviewed. A theoretical model that quantitatively captures the scaling of mobility with temperature, carrier density, and thickness is introduced. By fitting the available mobility data from literature over the past few years, one obtains the density of impurities and traps for a wide range of transistor structures. It shows that interface engineering can effectively reduce the impurities, leading to improved device performances. For few‐layer TMDCs, the lopsided carrier distribution is analytically modeled to elucidate the experimental increase of mobility with the number of layers. From our analysis, it is clear that the charge transport in TMDC samples is a very complex problem that must be handled carefully.

Vertical charge transport through transition metal dichalcogenides - a quantitative analysis.

Based on the careful design of two-terminal devices from multi-layer transition metal dichalcogenides (TMDs) such as MoS2 and WSe2, truly vertical transport has been experimentally evaluated and theoretically analyzed. By exploring, the electric field and temperature dependence of in total 28 TMD devices of various thicknesses, a model that describes vertical transport as Fowler Nordheim mediated at high electric fields and thermal injection dominated at low fields has been developed. Our approach is similar to the description chosen to capture gate leakage current levels through amorphous materials such as SiO2. Employing our quantitative analysis, an effective vertical transport mass of m*/m0 (MoS2) ≈ 0.18 and m*/m0 (WSe2) ≈ 0.14 has been extracted for the first time and barriers at the metal contact-to-TMD interface of heights similar to those extracted for lateral transport in TMD transistors have been confirmed.

Effects of annealing on top-gated MoS2 transistors with HfO2 dielectric

Transition metal dichalcogenides (TMDs) have attracted intensive attention due to their atomic layer-by-layer structure and moderate energy bandgap. However, top-gated transistors were only reported in a limited number of research works, especially transistors with a high-k gate dielectric that are thinner than 10 nm because high-k dielectrics are difficult to deposit on the inert surface of the sulfide-based TMDs. In this work, the authors fabricated and characterized top-gated, few-layer MoS2 transistors with an 8 nm HfO2 gate dielectric. The authors show that the cleaning effect of ultrahigh vacuum annealing before high-k deposition results in significantly reduced gate leakage current of HfO2, and they show that N2 or a forming gas anneal after device fabrication affects the threshold voltage, drive current, dielectric leakage, and C-V frequency dependence. This work demonstrates how the fabrication process can affect the yield and the electrical characterization of top-gated TMD transistors, which in effect can help researchers further enhance the performance of their devices.

High‐Performance Flexible Multilayer MoS2 Transistors on Solution‐Based Polyimide Substrates

Transition metal dichalcogenides (TMDs) layers of molecular thickness, in particular molybdenum disulfide (MoS2), become increasingly important as active elements for mechanically flexible/stretchable electronics owing to their relatively high carrier mobility, wide bandgap, and mechanical flexibility. Although the superior electronic properties of TMD transistors are usually integrated into rigid silicon wafers or glass substrates, the achievement of similar device performance on flexible substrates remains quite a challenge. The present work successfully addresses this challenge by a novel process architecture consisting of a solution‐based polyimide (PI) flexible substrate in which laser‐welded silver nanowires are embedded, a hybrid organic/inorganic gate insulator, and multilayers of MoS2. Transistors fabricated according to this process scheme have decent properties: a field‐effect‐mobility as high as 141 cm2 V−1 s−1 and an Ion/Ioff ratio as high as 5 × 105. Furthermore, no apparent degradation in the device properties is observed under systematic cyclic bending tests with bending radii of 10 and 5 mm. Overall electrical and mechanical results provide potentially important applications in the fabrication of versatile areas of flexible integrated circuitry.