Threshold Voltage Of Transistors Research Articles

A Study of Device Parameters Affecting the Current Error Rate in a Low-Temperature Polycrystalline Silicon Thin-Film Transistor Pixel Circuit for Active-Matrix Organic Light-Emitting Diode Display Applications

In active-matrix organic light-emitting diode (AMOLED) displays, conventional pixel circuits that compensate for the non-uniformity of the threshold voltage (VT) of low-temperature polycrystalline silicon thin-film transistors (TFTs) can hardly compensate for variations in other TFT parameters, such as carrier mobility (μ0), subthreshold swing (SS) and the various effects of parasitic capacitance. In recent high-resolution AMOLED displays, as the current required for OLED pixel driving decreases, the current error rate (CER) caused by the non-uniform TFT parameters increases. In this study, we analyzed the influence of each TFT parameter on the CER using SPICE simulation. Based on our analysis, the origin of the increased CER can be classified into two categories: the charging capability of driving TFT and the capacitive coupling effect of the switching TFT. The SS of the driving TFT and the parasitic capacitance of the switching TFT are major factors that affect the CER in terms of the charging capability and capacitive coupling effect, respectively. Our analysis results can be summarized as follows: The SS value of the driving TFT should be high, and its variation should be small to minimize the CER. The variation in the parasitic capacitance of the switching TFT possibly occurs due to long-term bias conditions, as well as process non-uniformity. Therefore, the stability of TFT should also be confirmed for the prevention of anomalous CER caused by long-term bias stress.

Tuning the Organic Electrochemical Transistor (OECT) Threshold Voltage with Monomer Blends

Tuning the Organic Electrochemical Transistor (OECT) Threshold Voltage with Monomer Blends

DC characteristics of a dynamic vision sensor's photoreceptor circuit evaluated for event-based sensing in the mid-wave infrared

Forthcoming infrared event-based sensors will have utility in the space-based surveillance domain where they could potentially perform traditional sensing and tracking functions with significantly enhanced temporal resolution and reduced downstream datalink demands and power consumption. As a first step toward extending event-based sensing technology into the mid-wave infrared, a DC simulation of the conventional event-based sensor unit cell's photoreceptor circuit is performed, and the results are compared with measurements of a printed circuit board implementation of the same circuit to assess what design freedom is available to interface the photoreceptor with a mid-wave infrared photodetector. Detailed analysis of the circuit and measurements provides insight into which fundamental properties of the transistors drive the photoreceptor's dynamic range and demonstrates several characteristics that are relevant to mid-wave infrared sensing. These characteristics include the capability to produce a stable, low voltage bias on the infrared photodetector to maximize sensitivity, and that operating the circuit below room temperature increases the photoreceptor's dynamic range. Measurements show that even the simplest implementation of the photoreceptor circuit exhibits a dynamic range of logarithmic compression of 150 dB at room temperature. However, the dynamic range is ultimately limited by the mid-wave infrared photodetector's dark current activation energy, which is significantly lower than the threshold voltage (energy) of the photoreceptor's feedback transistor and, thus, there is an incentive for the photodetector's dark current to be diffusion-limited.

A comprehensive investigation of total ionizing dose effects on bulk FinFETs through TCAD simulation

This study investigates the total-ionizing-dose (TID) effect on bulk FinFETs under ON-state irradiation bias, aiming to analyze the cause and physical mechanism of irradiation enhancement effects. Utilizing technology computer-aided design (TCAD), for the first time, we find that parasitic transistors located at the apex of the shallow trench isolation (STI) oxide significantly contribute to the subthreshold degradation of the device, leading to a notable increase in off-state leakage current. Furthermore, under identical irradiation bias conditions, narrower-fin and shorter-channel devices exhibit a more pronounced increase in off-state leakage current. This escalation is attributed to an increased amount of trapped charge in the STI oxide and the elevated electrostatic potential of the punch-through stop (PTS) layer, respectively. Additionally, higher drain voltage reduces the threshold voltage of the STI parasitic transistors, resulting in an increased off-state current as drain voltage rises. In summary, investigating the TID effect of bulk FinFETs under ON-bias is crucial, as it can provide theoretical support for reinforcing nanostructured devices against irradiation-induced degradation.

Ultra‐Low Threshold Voltage in N‐Type Organic Electrochemical Transistors Enabled by Organic Mixed Ionic‐Electronic Conductors with Dual Electron‐Withdrawing Substitutions

AbstractAchieving low threshold voltage (Vth) in organic electrochemical transistors (OECTs) is essential for minimizing power consumption and enhancing sensitivity in bioelectronic devices. However, obtaining OECT materials with ultra‐low Vth, close to 0 V for n‐type conjugated polymers remains challenging. Here, a conjugated polymer FBDOPV‐CNTVT is introduced, which features a rigid backbone structure and high electron deficiency, leading to an exceptionally low lowest unoccupied molecular orbital (LUMO) energy level of −4.67 eV, achieved through dual electron‐withdrawing substitutions. With its ultra‐low LUMO energy level, FBDOPV‐CNTVT exhibits high susceptibility to electrochemical doping, even demonstrating efficient doping near 0 V. Consequently, the OECT device employing FBDOPV‐CNTVT as the active material shows an ultra‐low Vth of 7.5 mV, setting a new record for the Vth of n‐type OECT devices. Furthermore, FBDOPV‐CNTVT exhibits a µC* value of 6.13 F cm−1 V−1 s−1 and retains ≈85% of its current after 2000 s cycling. This study highlights the potential of conjugated polymers with dual electron‐withdrawing substitutions to achieve ultra‐low LUMO energy levels, effectively reducing the Vth of n‐type OECT devices and promising advancements in bioelectronics.

Quantum coupling and self-heating impacts on threshold voltages of GaN metal–insulator-semiconductor high-electron-mobility transistors

A transient heat conduction equation has been proposed to describe the cooling process of a hot two-dimensional electron gas layer in a GaN-based transistor. This equation serves as the basis for a physical analytical model that explains the impacts of hot electrons in the hot two-dimensional electron gas layer via quantum coupling on the threshold voltage of GaN-based transistors. The temperature of the two-dimensional electron gas layer decreases to ambient temperature as time increases, and the threshold voltage shifts caused by such a temperature will recover with time. The proposed model accurately reflects the observed recovery of threshold voltage over time in experiments. At the same time, it offers insight into how the gate voltage, the source-drain voltage, and the ambient temperature can shift the threshold voltage in these transistors. The simplicity and analytic nature of this proposed model not only provide a physical origin of the threshold voltage instability in GaN-based devices but also offer the possibility for improving device reliability by selecting appropriate device physical parameters.

A gas sensing neural circuit for an olfactory neuron

A gas sensor can convert external gas concentration or species into electric voltage or current signals by physical adsorption or chemical changes. As a result, a gas sensor in a nonlinear circuit can be used as a sensitive sensor for detecting external gas signals from the olfactory system. In this paper, a gas sensor and a field-effect transistor are incorporated into a simple FithzHugh–Nagumo neural circuit for capturing and encoding external gas signals. An improved functional neural circuit is obtained, and the effect of gas concentration, gas species and neuronal activity can be discerned as the gate voltage, threshold voltage and activation coefficient of the field-effect transistor, respectively. The gas concentration can affect the neural activities from quiescent to normal working and, finally, to saturation state in bursting, spiking, periodic and chaotic firings with different frequencies. The effects of gas species and neuronal activity on the firing state can also be achieved in this functional neural circuit. In addition, variations in the gate voltage, threshold voltage and activation coefficient can cause switching between different firing modes. These results can be helpful in designing artificial olfactory devices for bionic gas recognition and other coupled systems arising in applied sciences.

A 40 mV cold-start circuit with bootstrap clock booster for thermoelectric energy harvesting

In this paper, a cold-start circuit with bootstrap clock booster for thermoelectric energy harvesting is proposed. The relationship between enhancing the clock swing amplitude and lowering the input voltage for a cross-coupled charge pump (CCCP) is analyzed. Based on the existing one-shot start-up mechanism, a series-parallel bootstrap clock booster (SP-BCB) for boosting the clock amplitude is proposed to lower the cold start voltage. Besides, a dynamic threshold MOS (DTMOS) technique for dynamically changing the threshold voltage of MOS transistors is used to achieve better conduction and leakage current suppression. The complete circuit is simulated in a 0.18-μm CMOS process. The simulated results demonstrate that using DTMOS technique and enhancing the clock swing amplitude can contribute to lowering the input voltage. The SP-BCB-based CCCP can boost the input voltage from 40 mV to 668 mV for a 500 MΩ load in 100 m s, which meets the requirement for one-shot start-up mechanism, realizing 40-mV integrated cold start for thermoelectric energy harvesting (TEH).

Persistent polarization effects and memory properties in ionic-liquid gated InAs nanowire transistors

Iontronics exploits mobile ions within electrolytes to control the electronic properties of materials and devices' electrical and optical response. In this frame, ionic liquids are widely exploited for the gating of semiconducting nanostructure devices, offering superior performance compared to conventional dielectric gating. In this work, we engineer ionic liquid gated InAs nanowire-based field effect transistors and adopt the set-and-freeze dual gate device operation to probe the nanowires in several ionic gate regimes. We exploit standard back-gating at 150 K, when the ionic liquid is frozen and any crosstalk between the ionic gate and the back gate is ruled out. We demonstrate that the liquid gate polarization has a persistent effect on the nanowire properties. This effect can be conveniently exploited to fine-tune the properties of the nanowires and enable new device functionalities. Specifically, we correlate the modification of the ionic environment around the nanowire to the transistor threshold voltage and hysteresis, on/off ratio and current level retention times. Based on this, we demonstrate memory operations of the nanowire field effect transistors. Our work shines a new light on the interaction between electrolytes and semiconducting nanostructures, providing useful insights for future applications of nanodevice iontronics.

Tuning the Threshold Voltage of an Oxide Thin-Film Transistor by Electron Injection Control Using a p-n Semiconductor Heterojunction Structure.

Herein, a heterojunction structure integrating p-type tellurium (Te) and n-type aluminum-doped indium-zinc-tin oxide (Al:IZTO) is shown to precisely modulate the threshold voltage (VT) of the oxide thin-film transistor (TFT). The proposed architecture integrates Te as an electron-blocking layer and Al:IZTO as a charge-carrier transporting layer, thereby enabling controlled electron injection. The effects of incorporating the Te layer onto Al:IZTO are investigated, with a focus on X-ray photoelectron spectroscopy (XPS) analysis, in order to explain the behavior of oxygen vacancies and to depict the energy band structure configurations. By modulating the thickness and employing both single and double deposition methods for the heterojunction Te layer, a remarkable VT shift of up to +20 V is achieved. Furthermore, this study also shows excellent stability to a positive bias stress of +2 MV/cm for 10,000 s without additional passivation layers, demonstrating the robustness of the designed TFT. By a thorough optimization of the Al:IZTO/Te interface, the results demonstrate not only the substantial impact of the introduced heterojunction structure on VT control but also the endurance, durability, and stability of the optimized TFTs under prolonged long-term operating stress, thus offering promising prospects for tailored semiconductor device applications.

Dielectric multilayers impact on radiation-induced charge accumulation in highly sensitive oxide field effect transistors

Radiation dosimetry is crucial in many fields where the exposure to ionizing radiation must be precisely controlled to avoid health and environmental safety issues. Among solid state detectors, we recently demonstrated that Radiation sensitive OXide Field Effect Transistors (ROXFETs) are excellent candidates for personal dosimetry thanks to their fast response and high sensitivity to x rays. These transistors use indium–gallium–zinc oxide as a semiconductor, combined with a dielectric based on high-permittivity and high-atomic number materials. Here, we present a study on the ROXFET gate dielectric fabricated by atomic layer deposition, where we compare single- and multi-layer structures to determine the best-performing configuration. All the devices show stable operational parameters and high reproducibility among different detectors. We identified an optimized bi-layer dielectric structure made of tantalum oxide and aluminum oxide, which demonstrated a sensitivity of (63 ± 2) V/Gy, an order of magnitude larger than previously reported values. To explain our findings, we propose a model identifying the relevant charge accumulation and recombination processes leading to the large observed transistor threshold voltage shift under ionizing radiation, i.e., of the parameter that directly defines the sensitivity of the device.

Ultra-low-power CMOS ring oscillator with minimum power consumption of 2.9 pW using low-voltage biasing technique

Abstract The need for low-power low-voltage circuit so lutions increases significantly with the rapid spread of wireless sensor network (WSN) and energy harvesting applications. The design of Complementary Metal-Oxide Semiconductor (CMOS) oscillators in sub-threshold region is challenged by the limits of the minimum start-up sup ply voltage, the power available from the harvester, die area, the demand of fully integrated CMOS circuits, and the additional auxiliary circuits that are needed to stabilize the frequency vs a supply voltage V DD. In this work, low-power CMOS oscillator with a simplified design is proposed in order to overcome the aforementioned obstacles. The circuit is designed using 2.5 µm 2-polySi 2-metal CMOS technology from IMB–CNM (CSIC) [1] with a threshold voltage of n-channel metal oxide semiconductor NMOS and p-channel metal oxide semiconductor PMOS transistors of 0.86 and −1.52 V, respectively. The suggested oscillator is capable to start up even in the deep sub-threshold region at V DD of 0.25 V. Accordingly, the minimum power consumption is 2.9 pW with an oscillation frequency of 2 Hz. The circuit can produce a P–P voltage of the oscillation signal equal to the supply voltage within a power supply range of 0.25–1.25 V.

CMOS Voltage-Controlled Oscillator with Complementary and Adaptive Overdrive Voltage Control Structures

This paper displays a voltage-controlled oscillator (VCO) with high performance implemented in 0.18 µm CMOS. The proposed CMOS VCO adopts a current-reused method, analog coarse and fine tuning mechanisms, and an adaptive overdrive voltage control structure to increase the overall performance, such as the power dissipation, phase noise, and tuning range, and has a robust start-up condition. The current-reused complementary structure with higher transistor transconductances is to save power consumption; the analog coarse and fine tuning mechanisms are to effectively widen the tuning range; and the adaptive overdrive voltage control technique is to change the transconductances of the transistors to improve power consumption by reasonably biasing the gate and body terminals in a class-AB mode to adjust the threshold voltage of the NMOS transistors. The proposed CMOS VCO adopts the class-AB mode to improve the overall performance and the start-up condition. The figure-of-merit (FOM) and FOM with tuning range (FOMT) are used in evaluating the CMOS VCO performance. The measured phase noise at 1 MHz and 10 MHz offsets is –130.34 dBc/Hz and –150.96 dBc/Hz at the 3.38 GHz operating frequency, respectively. The proposed CMOS VCO has a tuning range between 2.85 and 3.62 GHz corresponding to 23.8% for the fifth-generation (5G) wireless communication applications. The proposed CMOS VCO core using a 1.4-V supply consumes 7.5 mW DC power. The FOMs and FOMTs at 1- and 10-MHz offsets are −192.2, −192.8, −199.7, and −200.3 dBc/Hz, respectively, from the 3.38 GHz output frequency.

Increased Threshold Voltage of Amorphous InGaZnO Thin-Film Transistors After Negative Bias Illumination Stress

Increased Threshold Voltage of Amorphous InGaZnO Thin-Film Transistors After Negative Bias Illumination Stress

Methyl functionalization on polyimide side chains as gate dielectrics for organic transistors

The strategy of methyl functionalization on polyimide side chains may offer new possibilities for achieving high mobility and low threshold voltage in organic thin-film transistors.

DETERMINATION OF THE INFLUENCE OF TEMPERATURE AND UV TREATMENT ON THE CHARACTERISTICS OF DIFFERENTIAL ISFET ELECTRODES

The work is devoted to the study of the influence of temperature, UV radiation and a number of additional chemical treatments of crystals of ion-selective field- effect transistors in the electrode assembly in order to carry out appropriate types of chemical-technological treatments of the crystal surface and improve its ability to immobilize biosensitive elements. The influence of ultraviolet treatment on the characteristics of differential pH-FET (threshold voltage and channel current difference) was studied and the long-term effect of such influence was determined. Irreversible in time and significant symmetrical shift of the threshold voltages of both transistors on the crystal in the direction of a decrease in their absolute value from –(1.5–1.6) V to –0.6 V was revealed. It was shown that most electrodes with asymmetric I–V characteristics in the initial state become almost symmetrical after UV treatment, which makes it possible to use them as differential electrodes. It has been established that the relaxation process after UV irradiation is 90% complete within the first 10 days. Limits of permissible heating temperatures of ISFET electrodes of the described design, which do not lead to their failure, have been established. It is shown that the maximum safe heating temperature of the assembled electrodes is no more than 100 ºС when kept for 2 hours, and when heated to a temperature of 130 ºС for 2 hours, the symmetry of the current-voltage characteristics was violated in about 10% of the electrodes, and a drift of the current difference occurred, which lasted for the next 2 days after the temperature treatment. The influence of a number of additional chemical and technological treatments (with the help of a chromium mixture, a «piranha» solution and silanization of the nitride-silicon surface of the crystals) on the parameters of ISFET electrodes was studied. Protocols for effective cleaning and silanization of sensitive surfaces of transistors have been developed. A study on the modification of ISFET electrodes with silver and gold nanoparticles in order to improve their ability to immobilize biological reagents was carried out. It is shown that the use of gold nanoparticles in the composition of the enzyme membrane leads to a significant increase in the operating responses of enzyme biosensors.

Low-Leakage Double-Body MOSFET: A Promising Circuit-Level Technique for Deep-Submicron Analog Integrated Circuit Design

Since the leakage currents are dramatically increasing while the MOS transistors scale down to deep-submicron processes, the [Formula: see text]–[Formula: see text] characteristic of the channel is varied unintentionally. As a result, the analog integrated circuit (IC) designs based on it (at above 100-nm technologies) will malfunction. In this paper, a novel low-leakage double-body MOSFET (LLDB-M), as a circuit-level scheme in answering to the need for the current-mode analog IC design in deep-submicron processes, is proposed. In this technique, the sub-threshold and gate-oxide tunneling leakage currents (as two major parts) are reduced via lowering the gate-source voltage and increasing the threshold voltage of the MOS transistor. An LLDB-M consists of two typical transistors — the first one is the main transistor and the latter implements the shift-voltage to reduce the gate-source voltage and floor of the channel leakage currents. The drain, gate, and body of the main transistor as well as the body and source of the second one, organize the terminals of an LLDB-M. The proposed LLDB-M transistors are replaced with large-leakage transistors in a translinear loop in the weak inversion region and then the commonly-used circuits such-as the current mirror, one-quadrant multiplier-divider (at both up-down and stack topologies), the true RMS-DC converter, and the log-domain low-pass-filter are designed. The effectiveness and performance of the proposed LLDB-M technique and circuits are evaluated using HSPICE software in 22-nm BSIM4 CMOS process and Cadence Virtuoso tool in 65-nm TSMC CMOS technology. Post-layout simulation results show that the proposed circuit-level method by considerably reducing leakage currents could ensure the effective function of the current-mode analog IC designs in deep-submicron technologies. Also, comprehensive simulations have been performed to prove the robustness and reliability of the proposed circuits against process, voltage and temperature (PVT) changes.

Impact of total ionizing dose on the alpha-soft error rate in FDSOI 28 nm SRAMs

Synergy effect of total ionizing dose (TID) on alpha-soft error rate (α-SER) in FDSOI 28 nm SRAM has been experimentally characterized using a dedicated setup combining alpha-particle irradiation (241Am solid source) in vacuum chamber and 10 keV X-ray irradiation. Measurements have been performed on a 3 Mbit single-port SRAM cut powered at 1 V. Irradiations up to 125 krad(Si) have been achieved and their impact on the α-SER has been characterized from the cumulated number of bitflips as a function of the exposition time to the alpha-source. Modelling and simulation have been used to link transistor threshold voltage variations to SRAM cell stability in terms of static noise margin (SNM), critical charge (Qcrit) and finally estimated SER, in good agreement with experimental results.

Wide-range and area-selective threshold voltage tunability in ultrathin indium oxide transistors

The scaling of transistors with thinner channel thicknesses has led to a surge in research on two-dimensional (2D) and quasi-2D semiconductors. However, modulating the threshold voltage (VT) in ultrathin transistors is challenging, as traditional doping methods are not readily applicable. In this work, we introduce a optical-thermal method, combining ultraviolet (UV) illumination and oxygen annealing, to achieve broad-range VT tunability in ultrathin In2O3. This method can achieve both positive and negative VT tuning and is reversible. The modulation of sheet carrier density, which corresponds to VT shift, is comparable to that obtained using other doping and capacitive charging techniques in other ultrathin transistors, including 2D semiconductors. With the controllability of VT, we successfully demonstrate the realization of depletion-load inverter and multi-state logic devices, as well as wafer-scale VT modulation via an automated laser system, showcasing its potential for low-power circuit design and non-von Neumann computing applications.

Characterization and modeling of threshold voltage for organic and amorphous thin-film transistors

This work portrays the study and analysis of several extraction techniques that are typically used to ascertain the threshold voltage of organic thin-film transistors (OTFTs) and oxide-based transistors. This study evaluates the effects of physical and electrical parameters such as channel length, doping concentration, temperature, and trap on the threshold voltage (VTH) of both p-type and n-type bottom gate top contact (BGTC) OTFTs using graphical method. The methods employed in the present work to extract the threshold voltage are determined in the linear region of operation and are derived from the drain current (IDS) and the gate-source voltage (VGS) transfer characteristics. To compare and analyze the threshold voltage, various techniques such as the linear extrapolation method (ELR), constant current method (CC), transconductance linear extrapolation method (GMLE), second derivative method (SD), ratio method (RM), Inverse Ratio method (VX), and transition method (TM) are employed in the present work. In addition to DC characterization, the capacitance-voltage (C-V) method was also used to extract and compare the threshold voltage using all the conventional techniques listed above. 2-D numerical simulations were performed to assess the validity and usefulness of the various methodologies used for the extraction of the threshold voltage.