Threshold Voltage Of Transistors Research Articles

(Invited) Impact of Gate Dielectrics on the Threshold Voltage in MoS2 Transistors

Introduction MoS2 is a next-generation 2D material which is considered for applications in digital electronics [1–3]. Although enormous progress has been made in the area of MoS2 FETs, the available prototypes do not yet meet the high expectations. Commonly known reliability issues like the frequently observed hysteresis in the ID(VG) characteristics [4–6] and the large drifts of the threshold voltage over time [7] prohibit stable device operation for this technology. Apart from fabrication related issues, these performance limiting issues are the most critical obstacles inhibiting industrial applications of MoS2 FETs. Complementing our previous works [7–9], here we present a physical modeling approach for studying the charging and discharging of preexisting defects in the surrounding dielectrics. Devices We compare the hysteresis widths measured at the gates of MoS2 based FET devices at different sweep frequencies. Additionally, we study the drifts of the threshold voltage on these devices in a systematic way by evaluating the threshold voltage shifts observed after stressing the devices for different time spans and stress voltages. From the wide range of samples available, we choose devices using a thermal SiO2 layer as a back-gate dielectric. The MoS2 is either exposed to the ambient or covered by an amorphous Al2O3 layer. This thin dielectric layer enables a top gate contact and is at the same time necessary to prevent any degradation of the device characteristics due to the impact of the ambient [4,8]. Degradation Modeling For simulating the transfer characteristics we use a TCAD device simulator solving the drift-diffusion equations [10]. This approach is valid for devices with large dimensions and a large number of scattering centers, even if 2D channel materials are used [11]. The impact of interface defects is considered by using the standard SRH model. The transient charging and discharging of oxide defects leading to the hysteresis and the long-term drifts of the threshold voltage are described using the four-state NMP model [12,13]. The physical defect properties determining the degradation, such as trap positions and energy levels, depend on the respective oxide and have been studied in detail for SiO2 [8,14] and Al2O3 [9]. Results In accordance with our previous experimental work [7], we argue here that the common cause for the hysteresis in the ID(VG) and the observed long-term drifts are charge capture and emission events in the surrounding dielectrics. Even though several groups claim that the hysteresis is due to charge trapping at the interface [6,15,16], we argue here that interface traps can only impact the threshold voltage via a change in the sub-threshold slope. An observed hysteresis provides information about fast-switching oxide traps, while the systematic stress measurements reveal details about slow-switching oxide traps. One important quantity, necessary for understanding the size of the observed threshold voltage shifts, is the band alignment of the defect bands in the dielectrics with respect to the band edges of the semiconductors, illustrated in Fig. 1. Conclusions We use a drift-diffusion based simulation methodology to describe the cause of the threshold voltage drifts observed in the ID(VG) characteristics of MoS2 FETs, namely the charge capture and emission processes in the gate oxide traps. Thus, it is of utmost importance not only to investigate the fabrication of 2D layers, but also to focus on the quality and the defect bands of amorphous dielectrics to enable further progress in the area of FETs based on 2D materials. Acknowledgments The authors gratefully acknowledge financial support through FWF grant noI2606-N30.

(Invited) Impact of Gate Dielectrics on the Threshold Voltage in MoS2 Transistors

The electrical characteristics of field-effect transistors based on 2D materials such as MoS2 strongly depend on defects in various regions of the device. Thus, an accurate description of charge transfer reactions with defects is essential as they have a strong impact on several important performance parameters. In particular, they disturb the electrostatic control of the gate over the channel, which is one of the central advantages of 2D devices in the ultimate scaling limit. As a consequence of charge trapping in these defects, large threshold voltage shifts are possible on short (hysteresis) and long (drift) timescales, which prohibit stable device operation. Here we introduce a driftdiffusion based simulation methodology coupled to a non-radiative multiphonon model to describe charge transfer reactions. Our results shed light on the interaction of defects with the 2D channel, which is important to enable further progress in the area of 2D based transistors.

Immobilization of glucose oxidase on ZnO nanorods decorated electrolyte-gated field effect transistor for glucose detection

In this paper, we report on growth of ZnO nanorods on the surface of gold interdigital electrodes and its implementation as a conductive n-type channel for the fabrication of a liquid-gated field effect transistor. Glucose oxidase was immobilized on the surface of the ZnO nanorods and the fabricated device was used as a four-electrode glucose biosensor. The resistance of the conductive channel was affected by addition of glucose. The applied bias voltage to the gate in the fabricated device affects the channel resistance in the same manner as the increase of enzymatic products during the glucose oxidation. Large effective area, good conductivity, and biocompatibility properties of ZnO nanorods are the key features in this highly sensitive and stable biosensor. Our measurements showed that the threshold voltage of transistor was about 0.75 V. The current increased in the presence of the glucose and exhibited a dynamic linear range with the logarithm of glucose concentration in the range between 0.01 and 5 mM. The detection limit was about 3.8 μM.

Impact of Electrostatic Coupling and Wafer-Bonding Defects on Delay Testing of Monolithic 3D Integrated Circuits

Monolithic three-dimensional (M3D) integration is gaining momentum, as it has the potential to achieve significantly higher device density compared to 3D integration based on through-silicon vias. M3D integration uses several techniques that are not used in the fabrication of conventional integrated circuits (ICs). Therefore, a detailed analysis of the M3D fabrication process is required to understand the impact of defects that are likely to occur during chip fabrication. In this article, we first analyze electrostatic coupling in M3D ICs, which arises due to the aggressive scaling of the interlayer dielectric (ILD) thickness. We then analyze defects that arise due to voids created during wafer bonding, a key step in most M3D fabrication processes. We quantify the impact of these defects on the threshold voltage of a top-layer transistor in an M3D IC. We also show that wafer-bonding defects can lead to a change in the resistance of interlayer vias (ILVs), and in some cases lead to an open in an ILV or a short between two ILVs. We then analyze the impact of these defects on path delays using HSpice simulations. We study their impact on the effectiveness of delay-test patterns for multiple instances of IWLS 2005 benchmarks in which these defects were randomly injected. Our results show that the timing characteristics of an M3D IC can be significantly altered due to coupling and wafer-bonding defects if the thickness of its ILD is less than 100nm. Therefore, for such M3D ICs, test-generation methods must be enhanced to take M3D fabrication defects into account.

High Photocurrent in Gated Graphene-Silicon Hybrid Photodiodes.

Graphene/silicon (G/Si) heterojunction based devices have been demonstrated as high responsivity photodetectors that are potentially compatible with semiconductor technology. Such G/Si Schottky junction diodes are typically in parallel with gated G/silicon dioxide (SiO2)/Si areas, where the graphene is contacted. Here, we utilize scanning photocurrent measurements to investigate the spatial distribution and explain the physical origin of photocurrent generation in these devices. We observe distinctly higher photocurrents underneath the isolating region of graphene on SiO2 adjacent to the Schottky junction of G/Si. A certain threshold voltage (VT) is required before this can be observed, and its origins are similar to that of the threshold voltage in metal oxide semiconductor field effect transistors. A physical model serves to explain the large photocurrents underneath SiO2 by the formation of an inversion layer in Si. Our findings contribute to a basic understanding of graphene/semiconductor hybrid devices which, in turn, can help in designing efficient optoelectronic devices and systems based on such 2D/3D heterojunctions.

Dual threshold voltage and sleep switch dual threshold voltage DOIND approach for leakage reduction in domino logic circuits

Subthreshold leakage current becomes the major component of total power dissipation as scaling down the feature size. In this paper, two new circuit techniques are proposed for reducing the subthreshold leakage power consumption in domino logic circuit. Dual threshold voltage DOIND (Domino logic with clock and input dependent transistors) and NMOS sleep switch dual threshold voltage DOIND circuits for low leakage domino logic circuits are presented. High threshold voltage transistors are utilized to reduce the leakage current and a sleep transistor is added to the dynamic node that strongly turnoff all the high threshold voltage transistor and significantly reduce the subthreshold leakage power. The proposed circuit techniques, dual threshold voltage DOIND logic and sleep switch dual threshold voltage DOIND logic reduces the leakage current by 71.46 and 74.86% respectively as compared to standard domino logic circuit. Simulation results also shows that both the circuits are less affected by supply and temperature variations. The proposed sleep switch dual threshold voltage DOIND exhibits 19.95% less power consumption with 24% die area overhead for the buffer circuit as compared to standard domino logic circuit. The proposed sleep switch dual threshold voltage DOIND logic has improved normalized figure of merit of 1.17 as compared to standard domino logic circuit.

A Subthreshold Voltage Reference With Scalable Output Voltage for Low-Power IoT Systems

This paper presents a subthreshold voltage reference in which the output voltage is scalable depending on the number of stacked PMOS transistors. A key advantage is that its output voltage can be higher than that obtained with conventional low-power subthreshold voltage references. The proposed reference uses native NMOS transistors as a current source and develops a reference voltage by stacking one or more PMOS transistors. The temperature coefficient of the reference voltage is compensated by setting the size ratio of the native NMOS and stacked pMOS transistors to cancel temperature dependence of transistor threshold voltage and thermal voltage. Also, the transistor size is determined considering the trade-off between diode current between n-well and p-sub and process variation. Prototype chips are fabricated in a 0.18- $\mu \text{m}$ CMOS process. Measurement results from three wafers show $3\sigma $ inaccuracy of ±1.0% from 0 °C to 100 °C after a single room-temperature trim. The proposed voltage reference achieves a line sensitivity of 0.31%/V and a power supply rejection of −41 dB while consuming 35 pW from 1.4 V at room temperature.

Controlling the threshold voltage of SnO2 nanowire transistors with dual in-plane-gate structures gated by chitosan proton conductors

We fabricated novel dual in-plane-gate electric-double-layer (EDL) SnO2 nanowire transistors gated by chitosan using only one transmission electron microscopy (TEM) nickel grid mask at room temperature, and we successfully controlled its threshold voltage. By changing the second in-plane gate bias from 1.0 to −1.0 V, we tuned the threshold voltage of these transistors from −0.35 to 0.21 V. Their operation voltage was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance (4.24 µF/cm2). These dual in-plane-gate nanowire transistors could pave the way to useful low-voltage nanoelectronic devices.

Using Memristor Formalism in Semiconductor Device Modeling

Memristors, which are the fourth kind of passive element, along with resistors, inductances and capacitors, were first explicitly described in [1]. Their main characteristics are: (i) if there is no voltage across its terminals, there is no current; and (ii) the I-V curve shows a hysteresis that depends on the frequency of the forcing signal. Equations (1)-(3) describe the most general class of memristors [2], including a “hidden” set of controlling variables (for instance, temperature). v(t)=R(Q,X)i(t) (1) dX/dt=g(Q,i,X) (2) dQ/dt=i(t) (3) v(t) and i(t) are respectively the voltage and the current in the device, R(Q,X) is the memristance of the device, X is the set of controlling variables. Equation (3) is the general relation between charge and current, and is used without change along this paper. A special case of (2) is the POP equation (power-off plot), which is the case of no external forcing stimuli. For a memristor to be used as a non-volatile memory (as ReRAMs or PCM are), the POP equation (2) must equal zero for i=0 and any Q and X. Otherwise, X and, thus, R(Q,X) will change with time. In semiconductor devices, many phenomena involving some charge trapping and releasing are easily described with equations (1)-(3). Let’s analyze two different cases where this formalism is helpful: contact effects and hysteresis effects. Contact effects: Usually, contact effects are modeled using some passive elements, like resistors or diodes. There are other approaches, however, that model them in a more physical way [3] which can be very easily reformulated using memristor formalism as in equations (4)-(5). R(Q,X)=M·(Vgs-Vth)^n (4) dVth/dt= a·i(t)-b·(Vth-Vth0) (5) There, a and b are constants related to the probability of trapping and releasing charge at the interface, M and n are constants of the material, and Vth0 is the unperturbed threshold voltage. The physical mechanism behind the contact effect is a change in the effective barrier of the metal-semiconductor interface due to the charge trapped in there. Thus, memristors can be used as a discrete contact effect element, and implemented as a parasitic element. Hysteresis effects: Another effect observed in transistors is hysteresis, defined as a difference of the transistor characteristics between two consecutive measurements for identical inputs. As shown in [4], hysteresis can be explained as a change in the threshold voltage due to the accumulation of charge in the gate interface. This change can be described as in equations (6)-(7): i(t)=f(Q,Vth,Vds,Vgs) (6) dVth/dt= a·i(t)-b·(Vth-Vth0) (7) where a and b and Vth0 have the same meaning as in (4)-(5), f is the model for the current, Vgs is the gate-source voltage, and Vds is the drain-source voltage. Notice that the POP equation (7) doesn’t equal zero at i=0, so the system will relax back to its ground state Vth=Vth0. Figure 1 shows the effect of applying consecutive up and down Vgs ramps for a fixed Vds on a device modeled using this schema. As can be seen, the effect of hysteresis is higher at high currents, an leads to a change in the effective threshold voltage, as observed in real devices. Another mechanism producing hysteresis is the change in the mobility due to the filling of traps in the semiconductor[5]. In the VRH model [6], this leads to a change of the mobility. This effect seems to be smaller than the contribution of the change in threshold voltage in organic transistors, while it can be important in organic solar cells. Using the generic mobility model with two parameters [6], we obtain equations (8)-(10): i(t)=f(Q,Vaa,Ta,Vds,Vgs) (8) dVaa/dt= a1·i(t)- a2·(Vaa-Vaa0) (9) dTa/dt= b1·i(t)- b2·(Ta-Ta0) (10) where Vaa and Ta are the parameters of the mobility model, related to the trap distribution and the rest of the semiconductor characteristics [6]. Notice that equations (9)-(10) are a linear approximation by neglecting higher order non-linear terms.

A Low-Voltage SRAM Sense Amplifier With Offset Cancelling Using Digitized Multiple Body Biasing

With continued CMOS technology scaling down, transistors exhibit higher degrees of variation and mismatch, resulting in a larger offset voltage. A large offset voltage will enlarge bitline swing, increasing dynamic power consumption during a read operation and degrading the sensing decision correct rate and operation speed. Thus, the offset voltage is the most critical metric for static random access memory sense amplifiers (SAs), mainly arising from transistor threshold voltage mismatch. Here we propose an offset-cancelling technique with digitized multiple body biasing. In this scheme, SA transistor threshold voltage mismatch is compensated by adjusting the body bias voltage digitally and repeatedly. Simulation results in 130-nm CMOS technology show that the proposed calibration technique can reduce the standard deviation of the offset voltage by over four times comparing to a conventional SA, with about 6.5% and 1.6% area power overhead of a 6-kbit prototype chip introduced.

Electrochemical Field-Effect Transistor Utilization to Study the Coupling Success Rate of Photosynthetic Protein Complexes to Cytochrome c.

Due to the high internal quantum efficiency, reaction center (RC) proteins from photosynthetic organisms have been studied in various bio-photoelectrochemical devices for solar energy harvesting. In vivo, RC and cytochrome c (cyt c; a component of the biological electron transport chain) can form a cocomplex via interprotein docking. This mechanism can be used in vitro for efficient electron transfer from an electrode to the RC in a bio-photoelectrochemical device. Hence, the success rate in coupling RCs to cyt c is of great importance for practical applications in the future. In this work, we use an electrochemical transistor to study the binding of the RC to cytochrome. The shift in the transistor threshold voltage was measured in the dark and under illumination to estimate the density of cytochrome and coupled RCs on the gate of the transistor. The results show that ~33% of the cyt cs on the transistor gate were able to effectively couple with RCs. Due to the high sensitivity of the transistor, the approach can be used to make photosensors for detecting low light intensities.

A Minimum Hamming Distance Search Associative Memory Using Neuron CMOS Inverters

SUMMARYRecently, high‐speed searching for the most similar reference data out of the database is needed for data compression, image recognition, network control, and others. However, it takes much time to search for data with software, or hardware using conventional memory. Associative memory has been developed as a high‐speed searching device. In this paper, we propose a minimum Hamming distance search associative memory using neuron CMOS inverters. The proposed associative memory is less affected by initial charge and a change of threshold voltage of neuron MOS transistors than conventional neuron CMOS circuits. The proposed circuit also makes searching speed higher by using fully parallel processing. We confirmed that the proposed circuit can be realized expected results by simulation, and experiment using test chip.

Increase the threshold voltage of high voltage GaN transistors by low temperature atomic hydrogen treatment

High-electron-mobility transistors (HEMTs) based on AlGaN/GaN epitaxial heterostructures are a promising element base for the fabrication of high voltage electronic devices of the next generation. This is caused by both the high mobility of charge carriers in the transistor channel and the high electric strength of the material, which makes it possible to attain high breakdown voltages. For use in high-power switches, normally off-mode GaN transistors operating under enhancement conditions are required. To fabricate normally off GaN transistors, one most frequently uses a subgate region based on magnesium-doped p-GaN. However, optimization of the p-GaN epitaxial-layer thickness and the doping level makes it possible to attain a threshold voltage of GaN transistors close to Vth = +2 V. In this study, it is shown that the use of low temperature treatment in an atomic hydrogen flow for the p-GaN-based subgate region before the deposition of gate-metallization layers makes it possible to increase the transistor threshold voltage to Vth = +3.5 V. The effects under observation can be caused by the formation of a dipole layer on the p-GaN surface induced by the effect of atomic hydrogen. The heat treatment of hydrogen-treated GaN transistors in a nitrogen environment at a temperature of T = 250°C for 12 h reveals no degradation of the transistor’s electrical parameters, which can be caused by the formation of a thermally stable dipole layer at the metal/p-GaN interface as a result of hydrogenation.

Field effect transistor test structures for p-stop strip isolation studies

The strip isolation of AC-coupled n-on-p silicon strip sensors is compromised by positive charges located in the oxide above the silicon bulk. These positive oxide charges form an inversion layer electrically interconnecting the n+-implanted strips. To achieve a proper strip isolation though, a p+-implantation, the p-stop, is usually inserted in between the strips. The properties of this implantation like the concentration or implantation depth influence the final strip isolation. To investigate the isolation capability of the p-stop, field effect transistor (FET) test structures have been designed, measured and simulated using Synopsys TCAD. The main goal of these studies is to relate the threshold voltage of such transistors to the inter-strip resistance of actual sensors. Therewith, extensive measurements of usually large resistances could be transferred to comparable simple ones.

Temperature-induced instability of the threshold voltage in GaN-based heterostructure field-effect transistors

Temperature-induced instability of the threshold voltage in GaN-based heterostructure field-effect transistors (HFETs) and Al2O3– and ZrO2–based metal-oxide-semiconductor (MOS) HFETs was investigated and their trapping effects were analyzed. A negative or positive threshold voltage shift was observed in the HFETs with a AlGaN or InAlN barrier, which indicates that electron or hole traps dominate in the barriers. A temperature dependence of the threshold voltage in the MOSHFETs exhibited two different regions. At lower temperatures, similarly as in the HFETs, traps in the barrier dominated. However, at temperatures above 100−150 °C the threshold voltage shift was more pronounced and connected with the oxide/insulator interface traps. The threshold voltage shift can be negative or positive if a Al2O3 or ZrO2 gate insulator, respectively, is used. The results show that the temperature dependence of the threshold voltage can be controlled by the barrier layer composition and/or the gate insulator type.

Analytical models for GaN-based heterostructure-free normally off fin-shaped field-effect transistor

Analytical models for threshold voltage and subthreshold swing of GaN-based fin-shaped field-effect transistors (FinFETs) are obtained. Analytical expressions for the drain-induced barrier lowering effect and threshold voltage roll-off effect are presented. The explicit expressions for threshold voltage and subthreshold swing make the model suitable for being embedded in circuit simulations and design tools.

Bias-Point Calculation and Parameter Extraction Using EKV Compact MOS Model Equation

ABSTRACTThe main aim of this tutorial is to apprise readers about parameter extraction and bias-point calculation using Enz–Krummenacher–Vittoz compact metal oxide semiconductor (MOS) model equation. The model equation has been applied to an NMOS (N-channel metal oxide semiconductor) transistor case present on the P-substrate and P-well. Two cases are considered to show parameters extraction and bias-point calculation for a modified/unmodified value of the transistor threshold voltage. After presenting equation simplification for the two cases, different parameter extraction methods are discussed. Then a common drain configuration biased by a resistance is simulated to match by hand-calculated results.

Effects of Threshold Voltage Variations on Single-Event Upset Response of Sequential Circuits at Advanced Technology Nodes

Threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of transistors plays an important role in single-event upsets (SEU) and system power consumption. Effect of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> on single-event upsets can be very different for different technologies. SEU responses of flip-flops and logic circuits in 20-nm bulk planar and 16-nm bulk FinFET technologies with different V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> options are investigated. Results show that for the 20-nm bulk planar technology, the design with the highest threshold voltage among all V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> options shows the lowest SEU cross-section for alpha particle irradiation. For the 16-nm FinFET technology, the option with the highest threshold voltage shows the highest SEU cross-section. As frequency increases, the SEU cross-section of the highest V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> design shows a faster increase and a larger curve slope due to increased single-event transient (SET) pulse width compared to the lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> designs for the 16-nm FinFET technology node.

Low-power voltage to a frequency-based smart temperature sensor with +0.8/--0.75 $^{\circ}$C accuracy for --55 $^{\circ}$C to 125 $^{\circ}$C

The high power densities in system-on-chips demand accurate, low power, and compact smart temperatures for thermal monitoring. In this paper, a low-power CMOS-based smart temperature sensor, operating in the subthreshold region, for military applications (-55 $^{\circ}$C to 125 $^{\circ}$C) is presented. The sensor exploits the thermal dependency of the threshold voltage of MOS transistors to generate a voltage proportional to absolute temperature ($V_{PTAT})$. A frequency locked loop technique is employed to generate frequency from $V_{PTAT}$. The frequency variation due to temperature is measured by counting the rising edge with an asynchronous 12-bit counter. The large die area and requirement of external voltage regulator and reference clock hinder the integration of the on-chip sensors in SoCs. Therefore, a compact smart temperature is introduced with embedded temperature insensitive reference signal generators. The sensor is designed in CMOS 65 nm standard process and its operation is validated through postlayout results, considering a worst-case scenario. The sensor consumes power and area of 8.8 $\mu $W and 0.009 mm$^{2}$, respectively, at a power supply of 0.5-1 V. After one-point calibration, the sensor has an accuracy of +0.8/-0.75 $^{\circ}$C and a resolution of 0.26 $^{\circ}$C for -55 $^{\circ}$C to 125 $^{\circ}$C. The sensor consumes energy of 4.8 nJ and has a figure of merit of 0.12 nJK$^{2}$.

High performance single supply CMOS 0.45–1 V input to 1.1 V output level up shifter

This paper presents the design of a single supply CMOS level up shifter for low voltage and low energy consumption. The proposed voltage level converter is implemented using low threshold voltage transistors in 65nm CMOS technology. The shifter circuit designed for an output of 1.1V was verified, through the post–layout simulation, to be functional for an input voltage range of 0.45–1V. We compare our work with several other level shifters. With a 50fF of capacitive load, the shifter's energy–delay product is a 40% lower than a similar single supply level up shifter. Moreover, the measurements on the fabricated dies show that the proposed structure is able to drive a double capacitive load of up to 105fF, without any impact on the static power consumption. Monte–Carlo analysis demonstrates the robustness of the proposed shifter within a 3σ device mismatch.