Threshold Voltage Of Transistors Research Articles

Circuit Performance Shifts Due to Layout-Dependent Stress in Planar and 3D-ICs

This paper presents an approach for analyzing stress in 2-D and 3-D integrated circuits (ICs) due to postmanufacturing thermal mismatch. For both 2D-ICs and 3D-ICs, shallow trench isolation (STI) induces thermal residual stress in active silicon. For 3D-ICs, through-silicon vias (TSVs) act as an additional source of stress. Together, the sources of stress cause changes in the delay and power of the circuit. We develop an analytical model based on inclusion theory in micromechanics to accurately estimate the stresses and strains induced in the active region by surrounding STI in a layout. The TSV-induced stress depends on the location of the transistor with respect to the TSVs. Therefore, these stresses result in placement-dependent variations in the transistor mobilities and threshold voltages of the active devices, and we propagate these effects to circuit-level performance. At the transistor level, the stress state is translated into mobility and threshold voltage variations using piezoresistivity and band deformation potential models, respectively. At the gate level, the computed changes in transistor electrical parameters are used to predict gate-level delay and leakage power changes for single-fingered and multifingered layout styles, which are subsequently used to predict circuit-level delay and leakage power for a given placement.

<inline-formula> <tex-math notation="LaTeX">$In~Situ$ </tex-math> </inline-formula> and In-Field Technique for Monitoring and Decelerating NBTI in 6T-SRAM Register Files

This paper presents a technique to monitor and decelerate transistor threshold voltage ( $V_{\text {TH}}$ ) degradation caused by negative bias temperature instability (NBTI) in SRAM-based register files (RFs). The monitoring technique is in situ as it can directly sense the $V_{\text {TH}}$ of pMOSs in a bitcell. It is also in-field (i.e., postchip deployment) since the sensor output is robust to temperature and supply-voltage variations. The monitoring technique is complemented with a software framework that can create recovery vectors ( $\text {RV}_{\text {SRV}}$ ) based on the measured $V_{\text {TH}}$ degradation, which we can decelerate NBTI degradation by storing them opportunistically in an RF when the system is at stand-by mode. Test chips for a 1-kb RF with the proposed technique are prototyped in a 65-nm process. The average errors to monitor a considerable amount of NBTI degradation (>30-mV $V_{\text {TH}}$ degrading) against temperature (20 °C–80 °C) and supply-voltage (0.5–1 V) variations are 19% and 22%, respectively. These errors are $4.4\times $ and $3.4\times $ smaller than the previous in situ techniques. In addition, the experiments across multiple chips show that the generated $\text {RV}_{\text {SRV}}$ can recover a good portion of NBTI degradation and thus decelerate the degradation of data retention voltage. The area overhead of the proposed technique is 27% for the 1-kb RF and estimated to be 21% for a 4-kb RF.

Iodine doping enabled wide range threshold voltage modulation in pentacene transistors

We demonstrate an ultra-high range of threshold voltage modulation in pentacene transistors by iodine doping. Through diffusion control and thermal treatments, the transistor's threshold voltage can be tuned in a wide range of more than 100 V from enhance mode to deep depletion mode. The correlation between physical and electrical characteristics was investigated to elucidate the modulation mechanism. The results suggest an optimistic potential for pentacene transistors in high voltage device applications. The transistors in this research exhibit a high field effect mobility of ~0.18 cm2/Vs and on/off ratio ~105.

Aging-Aware Boosting

DVFS-based boosting techniques have been widely employed by commercial multi-core processors, due to their superiority in improving the performance. Boosting , however, is particularly stressing circuits and hence it significantly contributes to an accelerated aging process. Circuit aging has become a real reliability concern because it leads to an increase in transistor threshold voltage that may cause timing errors as a result of higher delays in critical paths. Thus, high performance is desirable but it shortens the circuit lifetime through aging leaving a choice to trade-off. Besides well-known long-term aging effects, recent research also reported short-term aging effects. Our claim is that DVFS-based boosting techniques should consider both long- and short-term aging effects. This can be circumvented by wider timing guardbands. But that would be more expensive. The goal of this work is therefore to analyze and optimize boosting under specific consideration of long-term and short-term aging effects. As a result of our findings, we propose the first comprehensive aging-aware, yet efficient boosting technique. The employed aging-aware cell libraries in this work are publicly available at http://ces.itec.kit.edu/dependable-hardware.php .

A 90-nm CMOS 800 MHz 2 $$\times$$ × VDD output buffer with leakage detection and output current self-adjustment

This work presents a 800 MHz 2 $$\times$$ VDD output buffer with PVTL (Process, Voltage, Temperature, Leakage) detection techniques to reduce slew rate (SR) variation. The threshold voltage (Vth) of MOS transistors varying with PVT is detected such that Output buffer will turn on different current paths correspondingly to decrease or increase the compensation current. Moreover, the slew rate is adjusted by Delay buffer and the leakage current sensor which compensates the dynamic and static currents, respectively. Most important of all, a deterministic sizing optimization method for the output transistors is reported and analyzed. The proposed design realized using a typical 90 nm CMOS process shows that the maximum data rate is 450/800 MHz given supply voltage 1.0/1.8 V with PCB and SMA connectors . The SR variation is reduced over 43% after the compensation of the leakage detection. The core area of the prototype is 0.056 $$\times$$ 0.439 mm $$^2$$ , and the power consumption is 68.9/98.5 ( $$\upmu$$ W/MHz) at 450/800 MHz, respectively.

Floating Drain-Based Measurement of ON-State Voltage of an OTFT for Sensing Applications

The threshold voltage of an organic thin-film transistor (OTFT) is sensitive to several variables, which makes it attractive for sensing applications. However, its measurement is not straightforward, especially, when mobility is gate voltage-dependent, and source and drain resistances are significant. The on-state voltage of a TFT does not suffer from these drawbacks, and thus, offers an alternative variable for use as a sensing variable. However, conventional measurement of on-state voltage marking the onset of conduction in the device requires measurement of very low current values, and extrapolation as a result of which it is not commonly employed. This paper demonstrates a simpler alternative method for measurement of on-state voltage that requires measurement of floating drain voltage as source voltage is linearly ramped while maintaining gate voltage constant. The drain voltage tracks the source voltage until the channel is completely removed. 2-D numerical simulation results are presented to validate that the proposed technique for the extraction of on-state voltage yields reliable estimates under different device conditions. Experimental results obtained with pentacene/poly (4-vinyl phenol)-based top contact bottom-gate OTFTs are also presented to illustrate the proposed concept.

Effect of Temperature on the Performance of Triple-Gate Junctionless Transistors

The device transport parameters (subthreshold slope, low-field mobility, series resistance, and threshold voltage) of n-channel triple-gate junctionless transistors are investigated in the temperature range 298–398 K. The temperature dependence of these parameters is analyzed to clarify the mechanisms responsible for the impact of temperature on the device performance. Based on analytical empirical expressions capturing their temperature dependence, our analytical compact model can predict the transfer and output characteristics at elevated temperatures with good accuracy.

2D MoSe2 Transistor with Polymer‐Brush/Channel Interface

AbstractToward any practical applications of 2D transition metal dichalcogenide (TMD) transistors, two issues are often met. First, threshold voltage (Vth) of usual TMD 2D field effect transistors (FETs) is located quite away from 0 V, making the device already on and less practical. Second, a large hysteresis exists during transistor operation. Here, hysteresis‐minimized n‐TMD FETs are fabricated using polymer‐brush/channel interface, to extend the 2D FET study to a sensor application. Gated by piezoelectric P(VDF‐TrFE) touch pad that allows dipole switching and instantaneous voltages of +5 and ‐5 V, n‐MoSe2 FET operates well in its ON/OFF drain current behavior, due to its properly small Vth of −5 V. However, n‐MoS2 FET with a relatively high Vth of more than −8 V cannot be suitably switched off. To minimize the gate hysteresis, ultrathin polystyrene‐brush layer is applied between TMD channel and 50 nm thin Al2O3 dielectric. n‐Channel MoS2 and MoSe2 FETs exhibit a minimum voltage hysteresis of 1 and 0.5 V, respectively. It is regarded that Vth and hysteresis issues are uneasy to resolve but still possible to circumvent by using proper TMD channel and channel/dielectric interface materials.

(Invited) SOI Wafer Technology for Advanced Mos Applications

Emerging microelectronic applications such as Internet-Of-Things (IOT) or mixed signal processing utilize fully depleted MOSFETs built on SOI wafers. Advanced FD devices such as planar MOSFETs with back gate biasing require wafers with thin Si top layer as well as ultra thin BOX layer. To sustain good electrostatic control of the channel and to keep back-gate voltages reasonably low, top Si layer thickness has to be in the 5-10 nm range and BOX thickness needs to be less than 20 nm. The SmartCutTM process is the only technology that allows transferring extremely thin layers of silicon on a wide range of handling substrates with industrial quality. As threshold voltage of FD SOI transistor depends on the thickness of Si layer, the thickness has to be controlled within extremely tight tolerance, typically + /- 5A in full range of spatial frequencies spanning from 10 nm till 300 mm [1]. This creates challenge not only for manufacturing technology, but requires development of new thickness metrology. Introduction of differential reflection microscopy (DRM) [2] allows in-line SOI thickness control in wide range of spatial frequencies with unprecedented throughput and precision. The principles and main applications of DRM will be discussed in the presentation. The key process steps with their influence on specific spatial frequencies are identified. One of the main contributors to mid range frequency (in mm range) thickness variation is the interaction of propagating fracture front with acoustic waves emitted by itself. The experimental verification of this mechanism as well as the results of numerical simulations will be presented. Another critical process in SOI technology is reduction of high frequency thickness variations during finishing steps. Possibilities of using pure surface diffusion as well as chemically enhanced high temperature smoothing will be demonstrated. It will be shown that during high temperature annealing in neutral atmosphere Si surface evolution can be described by Mullings-Herring equation with two extra stochastic terms, responsible for conservative and non-conservative noise, while addition of HCl to the annealing atmosphere changes surface behavior to surface relaxation described by the Edwards-Wilkinson model. General linear 4th order surface development model is proposed covering both mechanisms. Material parameters for the model are determined experimentally in the case of HCl(<1%)/H2 etching of silicon. For some advanced applications base wafer of SOI structure can play functional role in the final device, not limited to a mechanical support. One of such examples is RF SOI substrates specifically designed for RF analog applications, such as front end RF modules in smartphones. Introduction of thermally stable layer with high density of carrier traps between BOX layer and high resistivity Si substrate significantly improves high frequency electrical parameters of the devices built on such substrates [3]. Insertion loss, second harmonic generation of coplanar waveguides as well as quality factors of inductors are such main parameters. Empirical model is presented which allows prediction of the results of RF measurements from simple SRP data.

High performance CMOS level up shifter with full–scale 1.2 V output voltage

This paper introduces a very low static current CMOS level up shifter for low voltage single supply and high performance. The proposed low to high voltage level shifter is implemented using low threshold voltage transistors in 65 nm CMOS technology and based on differential topology. The shifter circuit was designed to be functional for an input voltage from 0.45 up to 1.2 V. Driving a 450 fF of capacitive load, the shifter's energy–delay product (EPD) is a 54% lower than a similar single supply level up shifter. Post–layout simulations, for every technological corner, temperature range from 25 up to 125 °C, operating input voltages and output capacitive loads (maximum of 740 fF), demonstrate the topology is fully functional without any impact on the static power consumption and the operating frequency of 500 MHz. Monte Carlo analysis shows the robustness of the proposed shifter within a 3σ device mismatch.

A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology

Most ultra low power SRAM cells operating in the sub and near threshold region deploy 8 or more transistors per storage cell to ensure stability. In this paper we propose and design a low voltage, differential write, single ended read memory cell that consists of a total of 6 transistors. The innovative idea is to bring the loadless 4-transistor latch into the realm of low voltage memory cells by exploiting features of the 28 nm FDSOI Process and by adding a 2-transistor readbuffer with a footer line. Stand-alone and on a system level, the cell is stable during read, write and hold operations and it has great write-ability due to its differential write and loadless nature. The single NWELL option in 28 nm FD-SOI allows the loadless core to have minimal device widths while greatly improving the time it takes to evaluate the read bit-line. The cell has, in this paper, been used in a 128 kb (217) SRAM in a 16 block configuration exploring 3 different types of logic libraries for the peripheral logic of the system. Depending on the application, the IO-peripheral logic may be implemented using either high threshold voltage transistors or low threshold voltage transistors in where the power consumption of the 128 kb system was found to range from 1.31 µW to 71.09 µW, the maximum operational frequency lies within 1.87 MHz and 14.97 MHz while the read energy varies from 13.08 to 75.21 fJ/operation/bit for a supply voltage of 350 mV. The minimum retention voltage of the loadless SRAM cell is found to be 230 mV covering 5σ of variation with Monte Carlo simulations.

A comprehensive survey on UHF RFID rectifiers and investigating the effect of device threshold voltage on the rectifier performance

Rectifiers are an integral part of power harvesting systems. In this paper, the literature on RF power rectifiers is surveyed, starting from the well-known voltage doubler. Effects of using low turn-on voltage devices on forward and reverse losses, and therefore, on conversion efficiency, is discussed. Samples of rectifiers with external devices, such as Schottky diodes are presented. Idea of external Vth cancellation through a rechargeable battery, self Vth cancellation, and floating gate transistors with charge injection onto the gates are demonstrated. Then, standard bridge rectifier and its modified versions, including Vth cancellation technique, are explained. Using low voltage devices in other technologies, such as silicon on sapphire and silicon on isolator are also discussed. After literature survey, the bridge rectifier is studied in detail, to extract guidelines for efficiency enhancement. Bridge rectifier has high PCE, because the transistors have a dynamic bias that lowers their forward and reverse losses, simultaneously. Then, the effect of transistor threshold voltages on the bridge rectifier performance is investigated. We propose to shift peak region in the efficiency curve to a desired output voltage, based on which, two modified rectifiers are introduced. A single stage modified bridge rectifier is proposed with 3.3 V transistors, that achieves efficiency of around 80% at 0.9 V output. Then, a two stage modified bridge rectifier is proposed, that uses a combination of 1.8 and 3.3 V transistors to remove the need to source-bulk connection in NMOS transistors (that requires triple-well CMOS technology). Simulations predict around 80% efficiency at 1.7 V output.

Subthreshold Modeling of Tri-Gate Junctionless Transistors With Variable Channel Edges and Substrate Bias Effects

In this paper, subthreshold channel potential, current, swing, threshold voltage, and drain-induced barrier lowering models of short-channel tri-gate junctionless field-effect transistors are presented. The models incorporate the effects of both substrate-induced surface potential and variable edges of channel. The quasi-3-D approach is used for the modeling of minimum of channel potential that is subsequently used in the drift–diffusion equation to obtain the current expression in subthreshold regime. Threshold voltage and subthreshold swing models are also based on the minimum of channel potential. The analytical results are compared with the simulation data obtained using 3-D visual TCAD device simulator from Cogenda Pvt., Ltd.

2D MoSe2 Field Effect Transistor with Small Threshold Voltage for Piezoelectric Touch Sensor Applications

Being implemented as an active component in the circuits, two dimensional (2D) transition metal dichalcogenide (TMD) transistors have two kinds of difficulties. First, regardless of carrier type, threshold voltage (Vth) of TMD 2D field effect transistors (FETs) is located far away from 0 V. Second, gate bias induced hysteresis exists in general 2D TMD transistors, causing an unstable operation of FETs. Here, we have fabricated stable n-channel MoSe2 FETs with a relatively small Vth of -5 V and minimized-hysteresis of 0.5 V. And we have checked the stable operation by integrating a smart touch sensor circuit composed of piezoelectric P(VDF-TrFE) polymer, the MoSe2 FET, and organic light emitting diode (OLED). To minimize the Vth and gate voltage hysteresis of 2D FET, we inserted ultrathin (8.46 nm) polystyrene (PS)-brush layer between MoSe2 channel and 50 nm-thin Al2O3 dielectric. Our MoSe₂ FET has showed a maximum drain-current (ID) of ~9 μA at VDS of 1 V along with a high linear mobility of 11.2 cm2/Vs. In the analogue touch sensor circuit gated by piezoelectric film of large scale Al/50 μm-thick P(VDF-TrFE)/ITO/glass, the MoSe₂ FET exhibites high ON/OFF ratio and ON-state ID which quite well demonstrated OLED pixel operation. Figure 1

Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from −1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

Pentacene bottom-contact thin film transistors with solution-processed BZT gate dielectrics

The solution-processed high-k barium zirconate titanate (BZT) as gate dielectrics for bottom-gate pentacene-based organic thin film transistor (OTFT) applications is presented. To reduce the transistor threshold voltage, higher work function metals (Au) is used as the gate electrodes. The threshold voltage is efficiently decreased from −3.6 to −2.15 V as compared to that of Al. In addition, the UV/ozone was employed to treat the Au (source/drain) surface to improve the poor crystalline of pentacene grown on Au. Moreover, the surface morphologies and orientations of pentacene films were analyzed through atomic force microscopy (AFM) and X-ray diffraction. As the results, the stack of pentacene molecules from disorder state changed to vertical growth on the Au surface. Finally, the electrical properties of pentacene-based thin film transistors exhibit high field-effect mobility of 4.5 cm2/V·s, low subthreshold swing of 260 mV/decade, high on/off ratio of 1.4 × 105 and low operation voltage of −5 V. These results are better than the reported data using bottom contact pentacene OTFTs.

Dynamic and Tunable Threshold Voltage in Organic Electrochemical Transistors

In recent years, organic electrochemical transistors (OECTs) have found applications in chemical and biological sensing and interfacing, neuromorphic computing, digital logic, and printed electronics. However, the incorporation of OECTs in practical electronic circuits is limited by the relative lack of control over their threshold voltage, which is important for controlling the power consumption and noise margin in complementary and unipolar circuits. Here, the threshold voltage of OECTs is precisely tuned over a range of more than 1 V by chemically controlling the electrochemical potential at the gate electrode. This threshold voltage tunability is exploited to prepare inverters and amplifiers with improved noise margin and gain, respectively. By coupling the gate electrode with an electrochemical oscillator, single-transistor oscillators based on OECTs with dynamic time-varying threshold voltages are prepared. This work highlights the importance of electrochemistry at the gate electrode in determining the electrical properties of OECTs, and opens a path toward the system-level design of low-power OECT-based electronics.

Surface Modification of Solution-Processed ZrO2 Films through Double Coating for Pentacene Thin-Film Transistors

We report the modification of surface properties of solution-processed zirconium oxide (ZrO2) dielectric films achieved by using double-coating process. It is proven that the surface properties of the ZrO2 film are modified through the double-coating process; the surface roughness decreases and the surface energy increases. The present surface modification of the ZrO2 film contributes to an increase in grain size of the pentacene film, thereby increasing the field-effect mobility and decreasing the threshold voltage of the pentacene thin-film transistors (TFTs) having the ZrO2 gate dielectric. Herein, the molecular orientation of pentacene film is also studied based on the results of contact angle and X-ray diffraction measurements. Pentacene molecules on the double-coated ZrO2 film are found to be more tilted than those on the single-coated ZrO2 film, which is attributed to the surface modification of the ZrO2 film. However, no significant differences are observed in insulating properties between the single-and the double-coated ZrO2 dielectric films. Consequently, the characteristic improvements of the pentacene TFTs with the double-coated ZrO2 gate dielectric film can be understood through the increase in pentacene grain size and the reduction in grain boundary density.

Suppression of Anomalously Large Threshold Voltage in Wafer-Bonded Vertical Transistors by Enhancing Critical Field to Impact Ionization

Impact ionization has been seen to effect pinchoff in wafer-bonded aperture vertical electron transistors (BAVETs) comprising an InGaAs channel wafer-bonded to a III-nitride (III-N) drift region. The InGaAs-III-N junction is referred to as the wafer-bonded interface (WBI). Field plating can work well to manage the peak field and related impact ionization; however, it comes with a tradeoff of increased on-resistance. In this paper, another control knob to breakdown is explored in the critical field ( $\xi _{{\text{CRIT}\_\text{IMPCT}}}$ ) of a BAVET. Investigation focuses on the characteristics of devices that differ in their InAlAs doping profile, namely p-type, unintentional, or a combination of both. These devices are tested for the role of field plate, built-in voltage, and trap behavior on pinchoff. It is shown that the change of doping causes a dramatic change to the trap activity at WBI. These traps ionize and determine $\xi _{{\text{CRIT}\_\text{IMPCT}}}$ as ionization of traps that leads to an early onset of impact ionization in the channel, which weakens pinchoff in a BAVET. Passivating traps is proposed to be a method to improving pinchoff. Trap passivation of WBI is demonstrated if InAlAs is doped p-type rather than unintentionally. A consequent enhancement in pinchoff and breakdown voltage of a BAVET is also reported.

Analytical Model for Schottky Barrier Height and Threshold Voltage of AlGaN/GaN HEMTs With Piezoelectric Effect

Physics-based models for calculating the threshold voltage ( ${V}_{\text {th}}$ ) of GaN-based high electron mobility transistor (HEMT) is proposed. Assuming that the 2-D electron gas in III–V heterostructures originate from donor-like surface states, an analytical expression for $\phi _{b}$ is derived based on the condition of charge neutrality across the barrier layer and applied to develop ${V}_{\text {th}}$ model. Effects of introducing a GaN cap layer on distribution of surface donor states and strain relaxation due to high barrier layer Al composition are considered in the derivation of the models. Calculated ${V}_{\text {th}}$ values are in excellent agreement with the values extracted from static ${I}_{d}$ – ${V}_{g}$ measurement data for devices with different gate lengths. Furthermore, the ${V}_{\text {th}}$ models are implemented in the physics-based ${I}$ – ${V}$ model previously proposed by our group for AlGaN/GaN HEMTs and tested with devices of different geometries. Excellent agreement is obtained between the model and experimental data of the drain current and transconductance of the devices over a full range of bias conditions.