Switching Transistors Research Articles

Highly sensitive active pixel image sensor array driven by large-area bilayer MoS2 transistor circuitry

Various large-area growth methods for two-dimensional transition metal dichalcogenides have been developed recently for future electronic and photonic applications. However, they have not yet been employed for synthesizing active pixel image sensors. Here, we report on an active pixel image sensor array with a bilayer MoS2 film prepared via a two-step large-area growth method. The active pixel of image sensor is composed of 2D MoS2 switching transistors and 2D MoS2 phototransistors. The maximum photoresponsivity (Rph) of the bilayer MoS2 phototransistors in an 8 × 8 active pixel image sensor array is statistically measured as high as 119.16 A W−1. With the aid of computational modeling, we find that the main mechanism for the high Rph of the bilayer MoS2 phototransistor is a photo-gating effect by the holes trapped at subgap states. The image-sensing characteristics of the bilayer MoS2 active pixel image sensor array are successfully investigated using light stencil projection.

Organic Light-Emitting Transistors Entering a New Development Stage.

Organic light-emitting transistors (OLETs) are possibly the smallest integrated optoelectronic devices that combine the switching and amplification mechanisms of organic field-effect transistors (OFETs) and the electroluminescent characteristic of organic light-emitting diodes (OLEDs). Such a unique architecture of OLETs makes them ideal for developing the next-generation display technology and electrically pumped lasers for miniaturized photonic devices and circuits. However, the development of OLETs has been slow. Recently, some exciting progress has been made with breakthroughs in high mobility emissive organic semiconductors, construction of high-performance OLETs, and fabrication of novel multifunctional OLETs. This recent slew of advances may represent the advent of a new development stage of OLETs and their related devices and circuits. In this paper, a detailed review of these fantastic advances is presented, with a special focus on the key points for developing high-performance OLETs. Finally, a brief conclusion is provided with a discussion on the challenges and future perspectives in this field.

Diode laser generating 3-ns pulses for a high resolution lidar

An AlGaAs laser (907 nm, 0.2 μJ) with a 3-ns pulse duration and eye-safe energy density below 1 μJ cm−2 is developed for lidar application. The laser is composed of three stacked diodes in a plastic housing. An external pump current generator based on discrete elements with an FMMT417 bipolar transistor switch is assembled on a printed circuit board together with the laser. A lidar based on this laser and a single photon avalanche diode (SPAD) as a detector is used to monitor aerosols with a resolution of 10 cm inside the tunnel of the Baksan Neutrino Observatory near the Elbrus volcano. An abrupt three-fold increase in aerosol emanation of yet unknown nature is recorded for the first time. The absence of the Earth’s crust disturbance traces in the signal of a laser interferometer with a resolution of 1.6 × 10−11 m testifies to a high sensitivity of the lidar for monitoring geodynamic processes.

Design and Development of Mini-pulsar for Real-Time Bioelectric Experiment

Investigation of the effect of pulsed electric field on eukaryotic cells has been of interestto biomedical scientists and researchers since a few decades. Reversible electroporation (EP) is used for uptake of chemicals, drugs, DNA into the eukaryotic cells under low electric field (100’s V/cm) of millisecond duration to few hundreds of microsecond duration. An electric field of nanosecond duration and a very high electric field (50’s kV/cm) can stress to intracellular organelles of eukaryotic cells and that can trigger apoptotic pathways. In this article experimental setup has been prepared for real-time investigation of the effect of nanosecond electric field on eukaryotic cells. Pulsar producing ~1.5kV, 20ns FWHM, single shot as well as ~10Hz rep-rate with rise-time as fast as ~10ns, has been prepared using blumlein pulse forming line and avalanche transistor switches. A 300µm gap microplate chamber has been prepared to expose the electric fieldtoeukaryotic cells.

Battery Charger with Bidirectional Power Transmission

The gradual reduction in price of electric batteries contributes to their wider use in autonomous and centralized power supply systems as a backup source of electricity and increase the share of electric vehicles. In the paper the conditions for increasing the efficiency of electric vehicle batteries, in particular in the framework of the concept of V2G (Vehicle to Grid) as a drive for the organization of autonomous power supply systems are analyzed. It is shown that this is possible only with the simple integration of batteries into the system, flexibility, and a wide range of modes that have to be provided by unified charge-discharge devices. Such charging devices have to have such features: a wide range of input and output voltage parameters; correction of the input power factor; the ability to take the maximum power from renewable energy sources; high energy efficiency. A review of possible topologies for a charger with bidirectional power transmission and a bridge converter with soft switching of transistors at zero voltage, which has a high efficiency, galvanic isolation and the ability to correct the shape of the current. The modes of operation of the converter are analyzed and conditions of soft switching is obtained. It is shown that soft switching is valid for current that is not less than minimal one. Efficiency of the converter with soft commutation is compared with a similar converter with rigid commutation of transistors. It is shown that static losses in converter with soft commutation it higher than in the rigid one. So, the proposed converter should be used if the increase in static losses is compensated by the lack of dynamic losses. Additional feature of the converter is that the regulation of the output voltage of the converter with soft switching is carried out according to the law of frequency-pulse modulation with a constant pause duration, where the pause duration is determined by the period of resonant processes of the converter. The model of the converter in Matlab Simulink is built and it is shown that the efficiency of the proposed converter topology is 10-15% higher, which together with the possibility of sinusoidal current with THD ≈ 20% and two-way transmission energy indicates the feasibility of its use as a charger for electric vehicles under the concept of V2G. However, it should be noted that the use of LCL filter creates a phase shift between voltage and current and degrades the THD value. To improve the shape, it is possible to use specialized laws of modulation [or to use modular converters, which allow to obtain a continuous current shape and reduce the volume of the filter.

Analysis and Design of a Fully-Integrated High-Power Differential CMOS T/R Switch and Power Amplifier Using Multi-Section Impedance Transformation Technique

In this paper, a new topology for a high-power single-pole-double-throw (SPDT) antenna switch is presented, and its loss mechanisms are fully analyzed. The differential architecture is employed in the proposed switch implementation to prevent unwanted channel formations of OFF-state Rx switch transistors by relieving the voltage swing over the Rx switch devices. In addition to that, the load impedance seen by the Tx switch is stepped down to reduce the voltage swing even more, allowing the antenna switch to handle a high-power signal without distortions. To drop the switch operating impedance, two matching networks are required at the input and the output of the Tx switch, respectively, and they are carefully implemented considering the integration issue of the front-end circuitries. From the loss analysis of the whole signal path, an optimum switch operating impedance is decided in view of a trade-off between power handling capability and insertion loss of the antenna switch. The insertion loss of the proposed design is compared to the conventional design with electromagnetic (EM) simulated transformer and inductors. The proposed antenna switch is implemented in a standard 0.18 µm CMOS process, and all switch devices adopt the deep n-well structure. The measured performance of the proposed transmitter front-end chain shows a 1 dB compression point (P1dB) of 32.1 dBm with 38.3% power-added efficiency (PAE) at 1.9 GHz.

Display-pixel performances driven by contact-limited switching transistors

In this paper, a direct link between contact properties of the transistor and electrical behaviors of the display system is established. Employing a liquid-crystal display driven by organic thin-film transistors as a model platform, systematic simulation of the image pixel circuit is performed to investigate this critical relationship. An elevated contact resistance at the transistor level is found to have a profound impact on charging dynamics of cell capacitors, revealing the importance of rendering such effects in designing advanced display electronics.

Ground Plane Electrostatically Doped Junctionless Tunnel Field Effect Transistor: Process Immune Design for Suppressed Ambipolarity

The incorporation of a highly doped Si layer below the Si film, termed as the ground plane, in the electrostatically doped junctionless tunnel field effect transistor (ED-JLTFET) with high-K gate stack. This allows the conceptualization and realization of highly reduced ambipolar behaviour with enhancement in the drive current. The deployed GP sinks the electric field induced at drain side, increases the effective channel length for the short channel devices, prevents the direct source-to-drain tunneling and also the channel-to-drain tunneling in reverse direction at negative gate voltages. A significant reduction of sub-threshold slope and DIBL is also reported for the considered device structure. Using a calibrated exhaustive TCAD study, the detailed sensitivity analysis is also carried for the proposed device with the parametric sweep method. Further, the device analog/RF performance is also comprehensively examined for its high frequency operations. Interestingly, it is also observed that the deployment of this GP also results in better volume depletion. Moreover, due to electrostatically doped structure, the reported device is also expected to have a lower thermal budget, immune towards the random dopant fluctuations (RDFs) effects and tolerant towards the velocity degradation effects as well. Hence, the reported device is a potential candidate for implementing ultra low power steep switching transistors.

Constrained minimization of switched capacitor converter equivalent resistance by adjusting transistor sizes and duty cycles

This paper presents a novel optimization technique for Switched Capacitor Converters (SCCs). The optimization focuses on minimizing the SCC equivalent resistance by adjusting MOSFET widths and switching duty cycles. The optimized SCC parameters are obtained from numerical optimization with constant total transistor width and switching period constraints. The transistor carrier mobilities and gate-to-source voltages are accounted during the optimization. A Fibonacci SCC with two flying capacitors is used as an example and is simulated in a 65 ​nm low-power process. By comparing SCC parameters before and after the optimization, we obtain certain performance improvements. Particularly, at a switching frequency of 10MHz and 50Ω load, the optimized design shows improvement in average and minimum output voltage parameters by 2.5% and 4.1%, respectively, which are caused by 20.6% reduction of the equivalent resistance. The output voltage ripple is also decreased by 22.4%. By sweeping the duty cycle and transistor widths in simulation, the optimized parameters show nearly the best performance.

Phase noise analysis of the connected-sources parallel quadrature oscillator

In this work, the operation mechanism of the Connected-Sources Parallel Quadrature Oscillator (CSPQO) is investigated meticulously through a novel perspective. It is proven that, unlike Disconnected-Sources Parallel Quadrature Oscillator (DSPQO), conduction angles of the switching and coupling transistors vary versus the coupling factor in CSPQO. This perspective leads to formulating CSPQO's drain currents to derive closed-form expressions for its phase noise for the first time. A comprehensive phase noise analysis for CSPQO is presented using Hajimiri's phase noise theorem. There are less than 2% and 1dB errors for oscillation amplitude and phase noise calculations. Besides, an inclusive comparison is performed between DSPQO and CSPQO, and it is established that CSPQO has a better performance for coupling factors less than 1. It is shown that a coupling factor of 0.35 is an optimum design point for CSPQO to have better phase noise and Figure of Merit (FoM) performances compared to DSPQO.

Ka-band time-domain multiplexing front-end with minimum switch area utilization on 22 nm fully depleted silicon-on-insulator CMOS technology

AbstractA time-domain duplexing radio frequency (RF) front-end with integrated antenna switch, power amplifier (PA), and low noise amplifier (LNA) was developed aiming for fifth-generation communication (5G) applications covering 24–28 GHz frequency range. Antenna switch utilizes pre-existing LNA input matching network together embedded with grounded shunt transistor switch to provide sufficient isolation of receive side from PA. Respectively, high impedance of off-state PA is assumed to achieve acceptable receive performance. Resulting output power is 13.6 dBm with 15 dB of peak small-signal gain at 28 GHz. Maximum average channel power was 4.8 dBm with 100 MHz 64-QAM OFDM signal within 5G adjacent channel power ratio and error vector magnitude specifications. Receive (RX) front-end achieves 5 dB noise figure at 24 GHz and 7 dB of peak gain. Performances of amplifiers degraded only by 2 dB from switch integration. The front-end dissipates 183 and 4.6 mW of power in transmit and receive mode, respectively. The simplistic design method minimizes cost both in circuit area (only 0.19 mm2) and design time making this front-end an attractive alternative in massive phased array applications using 22 nm complementary metal oxide semiconductor (CMOS) fully depleted silicon on insulator process.

Analysis and Design of Three-Level Full-Bridge LLC Resonant Converter Based on Pulse Frequency Modulation

Aiming at the problem of serious switching loss in high-power and high-voltage occasions, the traditional LLC resonant network is difficult to adapt, the DC gain is difficult to obtain intuitively, and the voltage stress on the switch is too high, resulting in large switching losses and difficult selection of the switch. This paper uses a three-level full-bridge LLC resonant converter topology, the First Harmonic Approximation (FHA) is used to analyze the LLC resonant converter gain characteristics, and the parameter design ideas are given. A simulation experiment of a three-level full-bridge LLC resonant converter based on frequency modulation control is presented. The simulation results show that each primary side switch transistor can achieve zero voltage switching (ZVS), the secondary side diode realizes zero current switching (ZCS), and can obtain higher working efficiency, which verifies the feasibility of the design.

RF Small and large signal characterization of a 3D integrated GaN/RF-SOI SPST switch

AbstractThis paper presents the radio frequency (RF) measurements of an SPST switch realized in gallium nitride (GaN)/RF-SOI technology compared to its GaN/silicon (Si) equivalent. The samples are built with an innovative 3D heterogeneous integration technique. The RF switch transistors are GaN-based and the substrate is RF-SOI. The insertion loss obtained is below 0.4 dB up to 30 GHz while being 1 dB lower than its GaN/Si equivalent. This difference comes from the vertical capacitive coupling reduction of the transistor to the substrate. This reduction is estimated to 59% based on a RC network model fitted to S-parameters measurements. In large signal, the linearity study of the substrate through coplanar waveguide transmission line characterization shows the reduction of the average power level of H2 and H3 of 30 dB up to 38 dBm of input power. The large signal characterization of the SPST shows no compression up to 38 dBm and the H2 and H3 rejection levels at 38 dBm are respectively, 68 and 75 dBc.

Design and Development of a Proficient Converter for Solar Photovoltaic Based Sustainable Power Generating System

The demand for renewable energy resources is invigorated due to various issues primarily related to energy security, energy sustainability, and greenhouse gas emissions. The proper utilization of renewable energy resources has certain challenges due to the varying nature of meteorological parameters and atmospheric aerosols. Therefore, it is of utmost importance to extract the maximum power from the photovoltaic systems with the help of proficient converters. Here, a coupled inductor based highly efficient synchronous interleaved boost converter is designed and developed for the grid integrated photovoltaic system. The proposed converter contains an Insulated Gate Bipolar Transistor (IGBT) switch in place of the conventional diode to maintain zero leakage current, bared minimum switching losses, and improved conduction time thereby enhancing the overall efficiency and reliability of the system. In addition, the proposed system topology is simple to implement and is capable of controlling power at both the generation as well as the load sides. The results obtained are validated with the help of a laboratory prototype under practical scenarios like varying temperature and solar irradiance. Further, an intelligent technique based on modified particle swarm optimization is utilized to extract the maximum power from the photovoltaic system. Moreover, the power quality indices were monitored and analyzed at the point of common coupling and at the grid level which vets the effectiveness of the proposed topology.

Design and concept proof of an inductive impulse self-destructor in sense-and-react countermeasure against physical attacks

This paper presents an inductive impulse self-destruction circuit utilized in a sense-and-react IC-level countermeasure against physical attacks on a cryptographic processor. Triggered upon an alarm signal assertion by an integrated attack sensor, the proposed circuit instantaneously generates >10 V high-voltage impulse to permanently destruct the cryptographic processor for enhancing tamper resiliency. A compact design with only a single on-chip inductor and a transistor significantly saves the hardware overhead. The inductor accumulates large electric energy in its magnetic field and the switch transistor suddenly opens the accumulated energy to boost the impulse voltage in an inertial manner. Since the inductor is drawn over the cryptographic core by existing on-chip IC interconnections, no extra area for the inductor and no any optional IC process steps are needed. This fully standard CMOS compatible, complete circuit solution, results in no fabrication cost penalty. A prototype implemented in both discrete components and a 0.18 μm standard CMOS process successfully demonstrated the-proof-of-concept.

Improving the Energy Performance of Traction Electric Drive Vehicles in Solving Electric Braking

The effectiveness of the electric braking system largely depends on how the braking is carried out, whether the braking characteristics that it forms are acceptable for a given vehicle, how simple and reliable the technical solutions embedded in the system are, and where the braking energy is used. With electric braking, it is possible not only to extinguish the electrical energy on the braking resistor, but also to send it back to the storage device and again use it in traction mode. This paper analyzes the most common methods of electric braking used in electric braking systems for traction electric drives that are in operation on vehicles. As the main criterion for evaluating the method of electric braking, its energy indicators are selected. The results of scientific research of the proposed new method of electric braking, which provides better energy performance and new technical solutions for its implementation, are considered. When implementing this method, DC motors are operated by sequential excitation generators. The current in the field windings is regulated by a DC-DC-converter. Energy in the power circuit is accumulated in storage devices and used in traction mode. When the storage devices are filled, the energy in the power circuit is extinguished by the braking resistor, and the energy from the output of the DC-DC-converter is used for own needs. In this case, braking characteristics are formed as in generators of independent excitation. To increase the braking efficiency at low speeds, it is necessary to smoothly regulate the resistance of the braking resistors by shunting them with transistor switches.

Low Power Analog Multiplexers for ECG Applications

This paper demonstrates the design of the 8 channel and 16 channel biomedical data selector with passtransistor switches. Pass transistor switches are designed with NMOS switch logic in 45nm technology. Data selectors are the important input circuitry to instrumentation amplifier in the Electrocardiogram (ECG). Generally, Inputs for ECG are very low voltages in terms of millivolts and frequency also in HZs. The proposed designs are useful in 3 lead 6 lead and 12 lead ECGs. The power dissipation is 11.055 pW at 1HZ and its calculated for supply voltages of 0.5 V and frequency analysis are done in between 1HZ to 10 KHZ.

0D/1D organic ferroelectrics/multiferroics for ultrahigh density integration: Helical hydrogen-bonded chains, multi-mode switching, and proton synaptic transistors.

In recent years, room-temperature ferroelectricity has been experimentally confirmed in a series of two-dimensional (2D) materials. Theoretically, for isolated ferroelectricity in even lower dimensions such as 1D or 0D, the switching barriers may still ensure the room-temperature robustness for ultrahigh-density non-volatile memories, which has yet been scarcely explored. Here, we show ab initio designs of 0D/1D ferroelectrics/multiferroics based on functionalized transition-metal molecular sandwich nanowires (SNWs) with intriguing properties. Some functional groups such as -COOH will spontaneously form into robust threefold helical hydrogen-bonded chains around SNWs with considerable polarizations. Two modes of ferroelectric switching are revealed: when the ends of SNWs are not hydrogen-bonded, the polarizations can be reversed via ligand reorientation that will reform the hydrogen-bonded chains and alter their helicity; when both ends are hydrogen-bonded, the polarizations can be reversed via proton transfer without changing the helicity of chains. The combination of those two modes makes the system the smallest proton conductor with a moderate migration barrier, which is lower compared with many prevalent proton-conductors for higher mobility while still ensuring the robustness at ambient conditions. This desirable feature can be utilized for constructing nanoscale artificial ionic synapses that may enable neuromorphic computing. In such a design of synaptic transistors, the migration of protons through those chains can be controlled and continuously change the conductance of MXene-based post-neuron for nonvolatile multilevel resistance. The success of mimicking synaptic functions will make such designs promising in future high-density artificial neutral systems.

BISH–QVCO: A Low–Power, Low–Phase noise Bulk–Injected Super–Harmonic coupling QVCO

In this paper, a novel method of Super–Harmonic coupling is proposed to generate quadrature outputs. In this method, by direct connection of all switching transistors bulk terminals, a second harmonic current is injected from each one of the I/Q oscillators to the other. Therefore, the proposed circuit is called Body–Injected Super–Harmonic coupling (BISH–) QVCO. The quadrature operation of the proposed circuit is mathematically proven and certified by simulations. In addition, through a detailed analysis, closed–form expressions are derived for the output phase noise and phase error. To have a fair performance evaluation of the proposed topology, the proposed BISH-QVCO, and the conventional P–QVCO are designed and simulated in 0.18 ​μm RF-CMOS technology with 3.22–3.64 ​GHz oscillation frequency (12.25% tuning range), a power supply of 1.8V, and the same power consumption of 3.85 ​mW. The quality factor of the tank circuits is calculated as 9.2. Post layout simulation results predict phase noise of −122.3dBc/Hz at 1 ​MHz offset from 3.64 ​GHz oscillation frequency that presents 4.1 ​dB and 2.7 ​dB phase noise improvements compared to the conventional P–QVCO and simple LC VCO, respectively. The maximum I and Q outputs phase error due to a 2% tank capacitor mismatch is 7°. A FOMT of 189.4 ​dB is achieved for the proposed QVCO. Also, the proposed method is capable of generating multi–phase outputs, which can be ranked among the well-performing ones.

An Improved Bipolar Voltage Boost AC Voltage Controller With Reduced Switching Transistors

Single-stage power conversion with simple circuit arrangement is one of the attractive features of direct bipolar voltage ac-ac converters. This increases their potency in various applications that require voltage and frequency regulation. The grid voltage compensators, direct variable speed ac-ac drives, and induction heating systems require inverting and non-inverting operation of the input voltage. Their size, cost, and circuit complexity directly depend on the number of switching transistors, as the operation of each transistor requires the use of one gate drive circuit (GDC) and one isolated dc power supply (IDCPS). The size and cost of GDC and IDCPS are much larger than that of switching transistors. The use of fewer switching transistors also ensures low conversion losses and simplifies the switching schemes. Therefore, this research proposes a new ac-ac converter that is realized as a bipolar boost ac voltage controller having a low count of switching transistors. The suggested topology also eliminates the shoot-through of the input source or output filtering capacitor. The characteristics of the proposed circuit are explored through simulation results obtained through the Simulink platform. The confirmation of the simulation results is validated through the laboratory prototype.