Abstract
AbstractThis paper presents the radio frequency (RF) measurements of an SPST switch realized in gallium nitride (GaN)/RF-SOI technology compared to its GaN/silicon (Si) equivalent. The samples are built with an innovative 3D heterogeneous integration technique. The RF switch transistors are GaN-based and the substrate is RF-SOI. The insertion loss obtained is below 0.4 dB up to 30 GHz while being 1 dB lower than its GaN/Si equivalent. This difference comes from the vertical capacitive coupling reduction of the transistor to the substrate. This reduction is estimated to 59% based on a RC network model fitted to S-parameters measurements. In large signal, the linearity study of the substrate through coplanar waveguide transmission line characterization shows the reduction of the average power level of H2 and H3 of 30 dB up to 38 dBm of input power. The large signal characterization of the SPST shows no compression up to 38 dBm and the H2 and H3 rejection levels at 38 dBm are respectively, 68 and 75 dBc.
Highlights
With the drastic increase of users, Internet of Thing devices and Machine to Machine communications, the 4G network has been challenged motivating an evolution to 5G
To the previous results, we have modeled the small-signal behavior of the gallium nitride (GaN)/radio frequency (RF)-Silicon on Insulator (SOI) SPST to quantify the substrate coupling reduction and measured in large-signal a coplanar waveguide (CPW) to assess the non-linearity of the GaN/RF-SOI substrate compared to the GaN/Si
The calculated compression on the breakdown voltage occurs for a larger stack height for the GaN/RF-SOI technology compared to the GaN/Si
Summary
With the drastic increase of users, Internet of Thing devices and Machine to Machine communications, the 4G network has been challenged motivating an evolution to 5G. Insertion loss and isolation The small-signal characterization of this heterogeneous device is performed from 0.2 to 30 GHz on the wafer with a Vector Network Analyzer. The heterogeneous structure presents lower insertion loss than the simulated GaN/Si switch, Fig. 1.
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