Transistor Parameters Research Articles

High-Voltage LDMOS Transistors on an SOI Structure for Electronics That Operate in Extreme Conditions

The parameters of high-voltage LDMOS transistors on a silicon structure on an insulator formed in a technological cycle combined with the manufacturing technology of low-voltage CMOS LSI are investigated. LDMOS transistors are studied under conditions of the temperature changing in the range –60 to 300°C and exposure to ionizing radiation.

Cross-Laboratory Experimental Validation of a Tunerless Technique for the Microwave Noise Parameters Extraction

In this article, a novel tunerless technique aimed at extracting the noise parameters of on-wafer transistors is experimentally validated. In detail, the effectiveness of the method has been confirmed by employing two different setups in two remotely located laboratories. The obtained noise parameters exhibit the level of accuracy typical of the standard source tuner-based Lane technique, without the well-known limitations due to the microwave tuner. The theoretical bases of the technique have been straightforwardly illustrated, and an extensive measurement campaign has been carried out on GaAs pHEMTs to confirm the suitability of the proposed approach. Furthermore, the technique can be applied to determine the contribution of additional thermal noise sources. The developed technique might represent the core of an automatic noise parameters’ extraction test bench.

Extremely low-voltage low-power differential difference current conveyor using multiple-input bulk-driven technique

In this paper, a new differential difference current conveyor (DDCC) with ultra-low voltage and low-power capability is presented. The DDCC is designed by using a non-tailed differential pair with multiple-input bulk-driven MOS transistor technique to obtain a rail-to-rail input common-mode swing and extremely low supply voltage. The MOS transistors biased in the sub-threshold region have been used to achieve extremely low power consumption. The performance of the proposed DDCC is evaluated by simulation results using SPICE program and MOS transistors parameters provided by a standard n-well 0.18 µm CMOS process from TSMC. A rail-to-rail input common-mode range was shown and a high accuracy was expressed. The bandwidth was 2.2 kHz and the total harmonic distortion was 1% for an input signal with amplitude of 240 mVp-p, obtained at supply voltage of 0.3 V and power dissipation of 28.6 nW. The proposed DDCC has been used to realize a sixth-order low-pass filter for application to electrocardiogram (ECG) applications.

The influence of low indium composition ratio on sol–gel solution-deposited amorphous zinc oxide thin film transistors

In this work, we examined the influence of In doping on the morphological and structural characteristics of ZnO active layers grown by the spin coating and the electrical performance of ZnO-based thin film transistors. XRD results indicated that the active layers were amorphous due to the absence of any sharp peaks. XPS analysis was carried out to determine indium amounts as an atomic percentage in ZnO and oxidation state of In. AFM images indicated that the roughness of the active layers decreased with increasing indium concentration in ZnO. The indium doping has dramatically improved the electrical parameters of ZnO-based transistors. The field-effect mobility of undoped TFT increased ~ 157 times by adding %3 In content. The highest field-effect mobility (μsat) of 12.9 cm2V−1 s−1 was obtained for %3 In-doped ZnO TFT (IZO3). Also IZO3 has a 6.96 V threshold voltage (Vth), 106Ion/Ioff ratio, 1.98 V/dec subthreshold slope (SS), and a high on-current of 4.6 mA. We ascribed the performance enhancement of devices with In doping due to increasing carrier concentration of channel. These results show that the low concentration of indium incorporation is very crucial to change the morphological properties of ZnO active layers and to obtain high-performance solution-processed TFTs.

Interstice: Inverter-Based Memristive Neural Networks Discretization for Function Approximation Applications

In this article, the accuracy of inverter-based memristive neural networks (NNs) for function approximation applications is improved under the presence of process variations. The improvement is achieved by using a design approach, called INTERSTICE (Inverter-based Memristive Neural Networks Dis cretization for Function Approximation Applications), which discretizes the output values by employing a classifier. More precisely, in the INTERSTICE approach, the output range is divided into $K$ subranges where each subrange is considered as a class. To train the classifier, the training samples are labeled where each label shows belonging to a specific class. To evaluate the efficacy of the design technique, some function approximation applications such as BlackScholes, FFT, $K$ -means, and Sobel are considered. Compared to PHAX, a recently published inverter-based memristive NN, INTERSTICE provides lower mean squared error (MSE) values in the presence of memristor and transistor variations. More specifically, the improvements in the mean of MSE ( $\mu _{\mathrm {MSE}}$ ) are in the range of 40%–80% when considering 10% variations in the memristor resistance and transistor parameters. In addition, for most of the benchmarks, INTERSTICE improves the $\mu _{\mathrm {MSE}}$ values of the nominal case (the case where all circuit elements are ideal) compared to PHAX. As another advantage compared to the PHAX, in INTERSTICE, digital outputs can be generated based on the selected classes which eliminates the need for an analog-to-digital converter at the output port connected to the digital part of the system. Finally, achieving lower $\mu _{\mathrm {MSE}}$ values using fewer memristors and consuming lower energy is also attainable with this design approach.

A Broadband Millimeter-Wave Continuous-Mode Class-F Power Amplifier Based on the Deembedded Transistor Model

In this letter, a broadband millimeter-wave (mm-wave) continuous-mode Class-F power amplifier (PA) based on the deembedded transistor model is proposed for the fifth-generation (5G) applications. To design the output matching network at the intrinsic current-generator plane, an $S$ -parameter fitting method is proposed to extract the parasitic parameters of nonpackaged transistors over a wide frequency range. The PA is implemented in the 0.13- $\mu \text{m}$ SiGe BiCMOS process, which occupies only 0.42 mm2. By controlling the even and odd harmonics impedance, the PA achieves a 78.2% −3-dB small-signal gain fractional bandwidth from 21.1 to 48.2 GHz. The −1-dB $P_{\mathrm {sat}}$ bandwidth covers 21–43 GHz (68.8% fractional bandwidth) and the saturated output powers are 17.2–18.1 dBm. Meanwhile, the designed PA provides a 24.1%–32.1% peak power-added efficiency (PAE) over the band.

Poly[2,5-bis(3-tetradecylthiophen-2-yl) thieno [3,2-b] thiophene] Organic Polymer Based-Interdigitated Channel Enabled Thin Film Transistor for Detection of Selective Low ppm Ammonia Sensing at 25°C

In the present work, we have developed a solution-processable poly (2,5-bis (3-tetradecylthiophen 2yl) thieno(3,2b) thiophene) (PBTTT-C14) based organic thin film transistor, for possible selective sensing the toxic ammonia (NH3) gas at 25°C. This thin-film transistor based sensor makes use of PBTTT-C14 polymer as an organic channel that exhibits highly responsive (>61%) behavior at different levels of ammonia concentrations, even in presence of a mixture of ethanol and butanol gases in a humid environment. The notable changes are observed in the transistor parameters including channel mobility, threshold voltage and the on-off ratio. Interdigitated channels obtained using shadow masking technique enables the device to respond to a low ammonia concentration (<10 ppm). Better sensing capabilities with a detection limit of 2 ppm, the response time of 30 sec and recovery time of 40 sec of exposed ammonia, butanol and ethanol gases have been recorded. The mechanism of sensing has been explained for a better understanding of electrostatic and chemical interaction between gases and PBTTT-C14 semiconductor. Electrical characterizations of the device for the sensing were carried-out in the ambient condition. The device performance has been tested in humid environmental conditions. The fabricated device exhibited enormous potential for ammonia sensing for real-life applications.

Radiation-Resistant Memory Device Based on Chalcogenide Glassy Semiconductor

A memory cell structure is proposed that uses a Schottky barrier thin film transistor based on an amorphous semiconductor as a junction element, and a chalcogenide glassy semiconductor film as a switching element. A physical storage cell model has been developed. The dependence of the transistor and memory cell parameters on the dose of neutron flux and γ - quanta was investigated. It is shown that when the dose of neutron irradiation is changed, the steepness of the drain-gate characteristic (DGC) decreases by 10% at a dose of the order of 1015 n/s, at the same time, the transfer coefficient of the bipolar n-p-n transistor decreases by 20% already at doses of 1013 n/s, indicating a significant increase in the radiation resistance of the proposed memory cell. In the case of irradiation with γ - quanta in the range up to 2.6 Mrad, the steepness of the DGC of the proposed structure changes by only 10%. When used as an isolation element, a field-effect transistor with an insulated gate, the slope of the DGC is reduced by 50%, that it is bad result. It is shown that the current of recording information of the proposed structure when changing the dose of γ - quantum flux to 2.6 Mrad changes by about 10%, at the same time, in the case of using a field-effect transistor with an isolated cover, the information recording current changes by 50%. The study of the dependence of the gate current on the dose of γ – quanta is showed. When the radiation dose changes from 0 to 2.6 Mrad, the gate current changes only by 10%, which indicates the high resistance of the proposed structure to the action of permeable radiation.

A Genetic algorithm for the optimal design of a multistage amplifier

&lt;span lang="EN-US"&gt;The optimal sizing of analog circuits is one of the most complicated processes, because of the number of variables taken into, to the number of required objectives to be optimized and to the constraint functions restrictions. The aim is to automate this activity in order to accelerate the circuits design and sizing. In this paper, we deal with the optimization of the three stage bipolar transistor amplifier performances namely the voltage gain (A&lt;sub&gt;V&lt;/sub&gt;), the input impedance (Z&lt;sub&gt;IN&lt;/sub&gt;), the output impedance (Z&lt;sub&gt;OUT&lt;/sub&gt;), the power consumption (P) and the low and the high cutoff frequency (F&lt;sub&gt;L&lt;/sub&gt;,F&lt;sub&gt;H&lt;/sub&gt;), through the Genetic Algorithm (GA). The presented optimization problem is of multi-dimensional parameters, and the trade-off of all parameters. In fact, the passive components (Resistors and Capacitors) are selected from manufactured constant values (E12, E24, E48, E96, E192) for the purpose of reduce the cost of design; also, the intrinsic parameters of transistors (hybrid parameters and the junction capacitances) are considered variables in order not to be limited in design. SPICE simulation is used to validate the obtained result/performances.&lt;/span&gt;

CMOS voltage and current feedback opamps: a comparison between two similar topologies

ABSTRACT The voltage feedback operational amplifier (VFOA) and the current feedback operational amplifier (CFOA) are the main voltage type output opamps currently used in electronics. The VFOA is a combination of an operational transconductance amplifier (OTA) used as an input stage and an output voltage buffer (VB). In this paper, the CFOA is described as a combination of an operational transconductance conveyor (OTC) used as an input stage and with an output voltage buffer. Two similar CMOS architectures are then defined, analysed and simulated in order to provide some elements of comparison. Results, from a typical CMOS 0.35μm transistor parameters, show the role of compensation capacitances in boosting the frequency performances of the non-inverting amplifier.

Design strategies for improvement in nonvolatile memory characteristics of metal-ferroelectric-metal-insulator-semiconductor capacitors using ferroelectric Hf0.5Zr0.5O2 thin films

The effects of top electrode and thickness control of ferroelectric HfxZr1−xO2 (HZO) film on the memory device characteristics were investigated for metal-ferroelectric-metal-insulator-semiconductor (MFMIS) capacitors. It was suggested from capacitance-voltage analysis for the MFM and MFMIS capacitors that the Al top electrode increased leakage current components and caused memory retention degradation owing to the formation of intermediate transistion layer at interfaces with HZO. Alternatively, the choice of Pt top electrode was appropriate to guarantee sound device operations without any reaction at interfaces. When the HZO thickness increased from 20 to 30 nm, the maximum memory window supported by ferroelectric field-effect increased from 2.6 to 3.1 V at an area ratio (MIS:MFM) of 60. Load-line and operating-point analysis show that polarization loops close to more saturated polarizations can be exploited for the memory operations of MFMIS capacitors using thicker HZO films. As a result, for the MFMIS capactior using 30 nm-thick HZO, the capacitance loss at on-state was only 8.7% after a lapse of retention time for 104 s. Choice of top electrode and control of HZO thickness were found to be important design parameters for highly-functional ferroelectric transistors using MFMIS gate-stack structures.

Magnetic bipolar transistor based on ZnO/NiO/Si heterostructure using pulsed laser deposition

Oxide semiconductors are promising candidates for next generation electronics. In this work, magnetic bipolar transistor was fabricated by growing thin films of p-NiO and n-ZnO on n-type silicon wafer by pulsed laser deposition technique with an in-situ annealing at 670° C in the presence of oxygen. The structural characterization of these films was done by X-ray diffraction and Raman spectroscopy and magnetic properties were studied by vibrating sample magnetometer (VSM). I-V characteristic of fabricated transistor was tested in common emitter configuration with DC biasing. Junction parameters such as ideality factor, series resistance, and transistor parameters like q-point were determined by using conventional transistor output characteristics. The diode and transistor showed an increase in current with the externally applied magnetic field due to the presence of Nickel or Oxygen vacancies in NiO attributing to spin polarized bipolar transport. Therefore the current amplification in these devices can be controlled by spin; making it attractive for spintronic applications.

Effects of pre-irradiated thermal treatment on ideal factor of excess base current in bipolar transistors

&lt;sec&gt;During the service of the spacecraft, it will be disturbed by the energetic particles and rays, and thus induce total ionizing dose (TID), displacement damage (DD) or single event effect (SEE) to generate inside the electronic system, which can seriously affect the service lifetime of the electronic components. The difference in structure and types of electronic components are less sensitive to the radiation effects, but bipolar transistor is strongly sensitive to ionizing radiation effect. As a basic component of bipolar circuits, the in-depth study of bipolar transistor ionization radiation effect is of significance for engineering.&lt;/sec&gt;&lt;sec&gt;It has been shown that the an amount of hydrogen can inevitably introduced from an external source during the sealing process of the devices. The KOVAR alloy is widely used as a metal cap material of bipolar transistor in the process of encapsulation. The residual gas analysis (RGA) for sealed Kovar lid packages is shown to have 1%–2% of the hydrogen in the cavity. The source of the hydrogen is generally considered to be out-gassing from the gold plating on the KOVAR. So far, the researches have focused on the study of the ionization damage effect of bipolar transistors with different structures under &lt;sup&gt;60&lt;/sup&gt;Co gamma ray irradiation. There is lack of systemic study on the comparison of transistors packaged with and without cap.In this paper, we study the influence of sealed KOVAR lid packaged on ionizing radiation damage of lateral PNP bipolar transistor (LPNP) by using &lt;sup&gt;60&lt;/sup&gt;Co gamma ray as an irradiation source. The semiconductor parameter analyzer is used to measure the electrical parameters of LPNP transistor during irradiation. The irradiation defects in LPNP transistors packaged with and without cap are characterized by deep level transient spectroscopy (DLTS). Experimental results show that the LPNP transistors packaged with and without cap have similar electrical characteristics. The base current increases with the total dose increasing, while the collector current remains almost constant. The degradation of LPNP transistor packaged with cap is more serious.&lt;/sec&gt;&lt;sec&gt;According to the excess base current varying with base-emitter voltage for the LPNP transistors packaged with and without cap, the degradation of bipolar transistor packaged with cap is more serious under the same irradiation conditions. According to the analysis of DLTS, comparing with bipolar transistor packaged without cap, the signal peak at about 300 K is shifted to the left for the bipolar transistor packaged with cap. These results indicate that the LPNP transistors packaged with cap can generate more interface states during irradiation, which is attributed to a large amount of hydrogen and water vapor out-gassing from the gold plating on the KOVAR, which is released under the thermal stress. In the sealed environment, hydrogen can only diffuse into the device cavity, and is combined with the metal material in the transistor to form metal hydride. Therefore the degradation of transistor is severe under the same irradiation condition.&lt;/sec&gt;

The Nature of Introduced Phase 1/f Noise in Microwave Oscillators

The nature of introduced phase 1/f (flicker) noise in an amplifier of a microwave oscillator that contains an isolating element (directional coupler) is studied. It is shown that noise can be generated due to fluctuations in resistive equivalent parameters of a heterojunction bipolar transistor (HBT) in the amplifier. The spectra of the fluctuations can be estimated using dc measurements. Such an approach allows selection of transistors for fabrication of amplifiers with low introduced 1/f noise and, hence, oscillators with low flicker fluctuations in the frequency.

Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern FPGA Fabric–Detection Methodology and Mitigation

The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship's integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillator-based sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation.

INVESTIGATION OF THE GRAPHOANALYTICAL METHOD OF DETERMINING THE STANDARD W-PARAMETERS OF THE FOUR-POLE

The level of social and economic development of modern society is determined by the volume, speed and quality of information processing by methods and technical means. Measurement and information processing systems are becoming an integral part of production automation. The development of radio electronics is inextricably linked with the development of measurements, and the state of modern radio electronics is largely determined by the level of development of measurement methods and the availability of sufficiently advanced measuring equipment to measure the parameters of radio-electronic devices, in particular transistors, allows: first, exploitation; second, to provide the source material for calculating the devices; third, to judge their internal properties and technological features in an average way; fourth, to design new, high-quality devices. The intensification and automation of the processes of production, complication and expansion of the front of scientific experiments entails the need to develop fundamentally new methods and means of measuring transistor parameters based on new algorithms and computers. Increasing the level of semiconductor devices, improving their performance, will inevitably affect potential stability over a wide frequency range. Classical methods and standard measuring equipment are not designed to measure the parameters of potentially unstable transistors. The measurement systems are uncontrollably excited, which increases the measurement error. Therefore, the current task is to measure the parameters of both transistors in particular and quadruplets in general, in the frequency range of potential instability. The clock speed at which modern computer technology operates is very close to the microwave range (ultra high frequencies), which makes the problem of measuring and calculating various functional units of computers and operating elements quite relevant. The development of new methods and means for measuring the parameters of potentially unstable quadruplets in the microwave range is an important scientific area, which can significantly improve the accuracy of their measurement on standard equipment. Improving the performance of the microwave range devices can be achieved both through the use of a fundamentally new element base and through the use of new circuit designs. Promising in this regard is the direction of using the reactive properties of transistors, as well as transistor structures with a negative resistance for the construction of information-measuring systems and operating and computing devices of the microwave range. The graphical methods for determining the parameters of an equivalent four-pole according to the measurement results are, as a rule, much more convenient than analytical ones. Having a mathematical equation and its graphical interpretation, it is relatively easy to determine the required quantities by solving graphical techniques. There are several ways of graphically depicting the relationships that characterize the impedance (conductivity). The following two are the most convenient: 1) pie chart of total resistance in rectangular coordinates [1]; 2) circular diagram of the total resistance in polar coordinates, proposed for the first time by Soviet scientist AR Volpert [2].

An LTspice Simulation Model of Gamma-radiation Effects and Annealing in a Voltage Regulator With a Lateral Serial PNP Transistor With Round Emitters

The aim of this paper was to determine the reasons for a complex radiation response of the commercial-off-the-shelf LM2940CT5 low-dropout voltage regulator. Examination of this circuit in a gamma-radiation environment disqualified its use when operated with relatively high output currents, while its radiation tolerance was satisfactory when load current was approximately one-tenth (or lower) of the nominal value. In order to obtain a more thorough insight into the radiation response of this integrated circuit, a detailed SPICE model was developed. This model enabled mutual comparison of the influence of serial and driver PNP power transistor parameters: forward emitter current gain, knee current and emitter resistance. The serial lateral PNP power transistor with round emitters was identified as the weakest element that crucially affected the entire circuit radiation tolerance. The effects of gamma-radiation were examined for total doses up to 500 Gy followed by three sequences of isothermal annealing. Detailed characteristics of Beta(Ic) were procured for four different kinds of bias and load conditions during irradiation. The emitter resistance increase of the serial power transistor was a primary reason for the low radiation tolerance of the entire voltage regulator; it was much more influential than the perceived decline of the PNP power transistor forward emitter current gain. The influence of bias and load conditions were analysed with buildup of interface traps and the oxide-trapped charge, which affected the radiation and post-irradiation response of the serial power transistor.

Web-drive based source measure unit for automated evaluations of ionic liquid-gated MoS2 transistors.

For reliable characterization of two-dimensional semiconducting devices and continuous monitoring in toxic environments, construction of an electrical characterization-based massive database using a portable source measure unit (SMU) with a WiFi connection is desirable. The web-drive based SMU using a microcontroller developed here exhibits superior voltage source performance (∼1 mV) and voltage/current measurement (∼0.15 mV/∼1 nA) capabilities, with automatic construction of a measurement database for online storage using web-drive based software, which can be applied for reliable electrical characterization. Electrical characterization of ionic liquid-gated MoS2 transistors was achieved with the designed SMU and showed results comparable with those obtained using a commercial semiconductor characterization system. Ionic liquid-gated transistors only require a small gate bias (∼1.5 V) for on-state operation because of the high gate capacitance originating from the thin dielectric layer constructed of an electrical double layer, which makes the device a promising candidate for low power consumption applications. Finally, several electrical parameters of the ionic liquid-gated transistor were extracted from the datasets and uploaded to the web-drive.

Analysis of the role of inter-nanowire junctions on current percolation effects in silicon nanonet field-effect transistors

In this paper, we compare the evolution with temperature of the experimental characteristics of Nanonet-based Field-Effect Transistors, with a modelling of carrier transport in the percolating regime. The main electrical parameters of Nanonet-based Field-Effect Transistors that featured different nanowire densities and source-drain distances were extracted from static measurements at different temperatures. The temperature dependence of low field mobility and threshold voltage was explained by the temperature activated behaviour of inter-nanowire junctions, and the activation energy dispersion of individual junctions. A Monte-Carlo simulation of Nanonet FET in the shape of a random percolating network of resistances and thermally activated junctions was used to confirm the influence of activation energy dispersion on low field mobility. The simplest model which was able to capture experimental trends consisted in a bimodal distribution of activation energies, with a subset of non-thermally activated junctions (resistive junctions) while other junctions were thermally activated (energy barriers at the junctions).

Radiation Effect on the Parameters of Field Effect Transistors with Schottky Barrier on GaAs

In the present work, we report the result of the study of electron and γ-radiation effect on the parameters of normally open and normally closed field effect transistors with Shottky barrier on GaAs. It has been shown that normally closed transistors are more sensitive to the action of radiation than normally opened transistors. Both transistors are more sensitive to the electron radiation. As substrates ware used epitaxial structures of GaAs of n-type conductivity doped with tellurium with ND=2×1017 cm3 with surface orientation [100]. Electron irradiation was conducted on the linear accelerator of RELUS type with electron energy 4 MeV at the room temperature, with the intensity of electrons flow of 2.5×1012 e/cm2 sec. Integral doses made 1×1014 e/cm2, 5×1014 e/cm2, 1×1015 e/cm2 and 3×1015 e/cm2. The γ-radiation was conducted using the source 60Co at the room temperature with the intensity of 5×103 P/sec. For the γ-radiation, visible changes of saturation flow current are observed at the doses of more than 105 Grey (GaAs). As whole, the γ-radiation makes an action on the parameters of MESFET in the less degree than electron irradiation. The annealing of the irradiated samples of MESFET at the temperature of 573 K in the nitrogen atmosphere for 45 min provides complete restoration of their parameters. The possible reasons for the mentioned effects are given.