Transistor Dynamic Random Access Memory Research Articles

A critique of length and bias dependent constraints for 1T-DRAM operation through RFET

Capacitorless dynamic memory (one transistor dynamic random access memory (1T-DRAM)) operation in a reconfigurable field effect transistor (RFET) is critically governed by different lengths associated with the architecture. These lengths consisting of ungated region (L UG), control gate (L CG), polarity gate (L PG), storage region length (L S), and total length (L T) can be sensitive to the fabrication process, and hence, critical for 1T-DRAM. This work presents an insightful critique of the above mentioned lengths for realising optimal 1T-DRAM performance. It is shown that RFET with highest values of L S/L T and L CG/L T shows good short channel immunity but does not necessarily ensure enhanced 1T-DRAM metrics. Results indicate that for a fixed L T, retention time can vary over a wide range (550 ms to 8.7 s) depending on the values of L S/L T and L CG/L T, and hence, appropriate optimization is imperative. The work contributes towards better understanding and optimizing L CG/L T to ensure improved 1T-DRAM metrics in terms of enhanced retention (>64 ms), acceptable sense margin (>6 µA µm−1), current ratio (>104) with low values of read (2 ns) and write (1 ns) time to further extend multi-functional facets of nanoscale RFETs for memory applications. In addition, the effect of traps, process sensitivity, reduced number of voltage levels, and disturbance caused by shared word line (WL)/bit line (BL) are also analysed in this work. Results indicate that state ‘0’ of the cell sharing BL with the selected cell is strongly affected by BL disturbance. WL disturbance primarily impacts state ‘1’ of the cell sharing WL with selected cell (only for write 1 and read operations).

Ferroelectric-Metal Field-Effect Transistor With Recessed Channel for 1T-DRAM Application

The ferroelectric-metal field-effect transistor with recessed channel (RC-FeMFET) is proposed for one transistor dynamic random-access memory (1T-DRAM). Through technology computer-aided design (TCAD) simulations, the effects of inter-metal insertion on the FeFET with recessed channel (RC-FeFET) is identified. By evaluating electric field (e-field) across interlayer (IL) and memory window (MW), the improvements of program/erase cycling endurance and read current sensing margin (RSM) are verified in the RC-FeMFET. Moreover, considering program voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</sub> ) and polarization switching time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\tau _{\mathrm{ p}}$ </tex-math></inline-formula> ), the guide line of the RC-FeMFET design is provided in terms of e-field across IL and MW for 1T-DRAM applications.

The Effect of Grain Boundary on Electrical Characteristics in the Source and Drain Regions of Polycrystalline Silicon Based in One Transistor Dynamic Random Access Memory.

In this paper, we present a capacitorless one transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) double gate MOSFET with grain boundaries (GBs). Several studies have been conducted to implement 1T-DRAM using poly-Si. This is because poly-Si has the advantage of low-cost fabrication and can be stacked. However, poly-Si has GBs, which can adversely affect semiconductor device. So far, related studies on poly-Si-based 1T-DRAM have only focused on GBs present in the channel domain. Hence, in this study, we analyzed the transfer and memory characteristics when a GB is present in the source and drain regions. As a result, we found that in the center of the depletion region in the source and channel junction, where the effect of GB was most significant, sensing margins decreased the most from 0.88 to 0.29 μA/μm, and retention time (RT) decreased from 85 ms to 47 μs. In addition, we found that at the center of the depletion region in the drain and channel junction, where the effect of GBs was most significant in the drain region, RT decreased the most from 85 ms to 52 μs.

Enhancement in Retention Time of 3TDRAM Using Double Gate Finfet Technology at Nanometer Regime.

Leakage current, power and area is the key challenges for VLSI designer during implementation of low power devices. In an integrated circuit number of transistors double in small silicon area every two years. There are certain limitations of cmos technology in nanometer regime out of which leakage current, leakage power, average current and average power is an important issues. In this paper, Retention time improvement in three transistor dynamic random access memory using double gate Finfet technology is proposed. Double gate finfet technology in 3TDRAM overcomes the issues related to cmos technology and it does not required additional circuitry. Proposed 3T DRAM is investigated with cmos and finfet technology at 90nm technology using cadence tool. Analysis of 3TDRAM using cmos and double gate finfet technology is carried out by variation in supply voltage and capacitance values. In double gate finfet technology leakage parameters are minimized and retention time(Th) is more improved as compared to cmos technology is observed.

A low power L-shaped gate bipolar impact ionization MOSFET based capacitorless one transistor dynamic random access memory cell

In this paper, a capacitorless, low power and CMOS compatible L-shaped gate bipolar impact ionization metal-oxide semiconductor (L-BIMOS) one transistor dynamic random access memory (1T DRAM) cell is proposed. The proposed 1T DRAM offers high retention time (RT = ∼1.4 s), sense margin (SM = ∼45 μA μm−1) and read current ratio (∼5 orders of magnitude). The RT and SM are 1.86×, and 300× , respectively higher than the previously reported silicon germanium (SiGe) based BIMOS 1T DRAM. Therefore, the proposed 1T DRAM cell stands out to be power efficient, and provides better integration density that makes it suitable for various emerging computing applications.

Investigation of Modified 1T DRAM with Twin Gate Tunneling Field Effect Transistor for Improved Retention Characteristics

This paper proposes a one transistor dynamic random access memory (1T DRAM) with localized partial insulator (LPI) to increase data retention time. Proposed 1T DRAM cell is based on twin gate tunneling field effect transistor (TGTFET) and has improved retention characteristics with LPI. The LPI inhibit stored carrier movement with high energy barrier. Key process sequence is suggested and device optimizations with parameter variation are also investigated with device simulation. As the barrier length increases, retention characteristics can be improved but also it causes a decrease in the read 1 current. An increase in LPI length within the appropriate range is required in the proposed 1T DRAM.

A Comprehensive Study of a Single-Transistor Latch in Vertical Pillar-Type FETs With Asymmetric Source and Drain

The single-transistor latch in vertical pillar-type FETs with asymmetric source and drain (S/D) was investigated for capacitorless one transistor dynamic random access memory (1T-DRAM). The asymmetric S/D is produced by the different energies of ion implantation at different depths of the pillar. The window of latch voltage ( $\Delta {V}_{L}$ ), which is the difference between the latch-up voltage ( ${V}_{\textit {LU}}$ ) and latch-down voltage ( ${V}_{\textit {LD}}$ ), was dominantly governed by ${V}_{\textit {LD}}$ . Fluctuation in the $\Delta {V}_{L}{(}{=}{V}_{\textit {LU}} - {V}_{\textit {LD}}$ ) is mainly induced by different series resistances ( ${R}_{\textit {SD}}$ ). The variation in ${R}_{\textit {SD}}$ becomes increasingly fatal to the stable operation of a 1T-DRAM with a smaller diameter; therefore, uniform control of ${R}_{\textit {SD}}$ is very important for the read operation in 1T-DRAM. In addition, the doping concentration of the source should be high for wide $\Delta {V}_{L}$ .

Excellent scalability including self-heating phenomena of vertical-channel field-effect-diode type capacitor-less one transistor dynamic random access memory cell

The scalability study and the impact of the self-heating effect (SHE) on memory operation of the bulk vertical-channel field effect diode (FED) type capacitorless one transistor (1T) dynamic random access memory (DRAM) cell are investigated via device simulator for the first time. The vertical-channel FED type 1T-DRAM cell shows the excellent hold characteristics (100 ms at 358 K of ambient temperature) with large enough read current margin (1 µA/cell) even when silicon pillar diameter (D) is scaled down from 20 to 12 nm. It is also shown that by employing the vertical-channel FED type, maximum lattice temperature in the memory cell due to SHE () can be suppressed to a negligible small value and only reach 300.6 from 300 K ambient temperature due to the low lateral electric field, while the vertical-channel bipolar junction transistor (BJT) type 1T-DRAM shows significant SHE ( K). Moreover, this excellent thermal characteristic can be maintained even when D is scaled down from 20 to 12 nm.

Novel Field Effect Diode Type Vertical Capacitorless One Transistor Dynamic Random Access Memory Cell with Negative Hold Bit Line Bias Scheme for Improving the Hold Characteristics

In this paper, the novel field effect diode (FED) type vertical capacitorless one transistor dynamic random access memory (1T-DRAM) cell with negative hold bit line (BL) voltage (VBL) scheme is proposed. In comparison with the conventional planar type, the proposed vertical type with negative hold VBL scheme shows excellent static and disturb retention time. The proposed vertical type memory cell with negative hold VBL scheme achieves 1,000 times longer static retention time and 104 times longer BL disturb retention time at 85 °C than that of the conventional planar type. Furthermore, the proposed vertical type memory cell has a small cell size of 4F2 due to its stacked vertical structure. The proposed FED type vertical capacitorless 1T-DRAM cell with negative hold VBL scheme is shown to be an excellent candidate for stand-alone and embedded memory applications and extends scaling limitations.

Channel Recessed One Transistor Dynamic Random Access Memory with SiO2/Si3N4/SiO2Gate Dielectric

Channel Recessed One Transistor Dynamic Random Access Memory with SiO₂/Si₃N₄/SiO₂Gate Dielectric

Capacitorless single transistor dynamic random-access memory devices fabricated on silicon–germanium-on-insulator substrates

Capacitorless single transistor dynamic random-access memory (1T-DRAM) cells on silicon–germanium-on-insulator (SGOI) substrates with various Ge mole fractions in the relaxed-SiGe layers were investigated. SGOI substrates with strained-Si channels showed higher on-currents and carrier mobility than a silicon-on-insulator (SOI) substrate with unstrained-Si channels. SGOI 1T-DRAM devices had larger memory windows than a similar device with SOI; memory window increased with increasing Ge mole fraction in the relaxed-SiGe layer. The SGOI 1T-DRAMs showed degraded retention times. High-temperature annealing reduced the effects of crystalline defects and thus improved the electrical properties of the SGOI substrates, leading to higher carrier mobility, larger memory window, and longer data retention.

Analysis of UTBOX 1T-DRAM Memory Cell at High Temperatures

This work investigates the behavior of Ultra Thin BOX (UTBOX) FDSOI devices used as a memory cell 1T-DRAM (single transistor dynamic random access memory) at high temperatures through 2D numerical simulations. The minimum drain voltage for the onset of the bipolar junction transistor (BJT) effect (VLatch) was obtained for various buried oxide thickness (tbox) and silicon film thickness (tSi). The simulation results clearly show that, when temperature increases, the VLatch, the sense margin current (ΔISENSE), the latch time (tLatch) and the retention time decreases.

Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

A data retention time has been investigated for various gate oxide schemes of saddle-fin (S-Fin) transistor dynamic random access memory (DRAM). The interface traps strongly affected the data retention time which was not clearly explained with a gate-induced-drain-leakage (GIDL) current as well as a junction leakage current. Despite the lower GIDL current by the thicker side-wall oxide of a dry oxidation scheme than a radical scheme, the degradation of the retention time was originated from the high interface-trap density (Dit). It is worthwhile to note that the Dit as well as the GIDL current is a still meaning parameter to analyze the data retention time.

Data Retention Characteristics for Gate Oxide Schemes in Sub-50 nm Saddle-Fin Transistor Dynamic-Random-Access-Memory Technology

A data retention time has been investigated for various gate oxide schemes of saddle-fin (S-Fin) transistor dynamic random access memory (DRAM). The interface traps strongly affected the data retention time which was not clearly explained with a gate-induced-drain-leakage (GIDL) current as well as a junction leakage current. Despite the lower GIDL current by the thicker side-wall oxide of a dry oxidation scheme than a radical scheme, the degradation of the retention time was originated from the high interface-trap density (Dit). It is worthwhile to note that the Dit as well as the GIDL current is a still meaning parameter to analyze the data retention time.

Effects of back interface trap states on the fully depleted strained-silicon-on-insulator capacitorless single transistor dynamic random access memory cells

A series of systematic experiments were carried out to investigate the effects of silicon back interface state density between silicon channel layer and buried oxide layer on the memory characteristics. The back interface states of fully depleted strained-silicon-on-insulator (FD sSOI) substrate were intentionally generated by controlling the temperature of rapid thermal annealing (RTA) process and the amount of back interface trap was evaluated by using the backgated metal-oxide-semiconductor field-effect transistor method. As a result, the trap density of back interface increased with RTA temperature, which causes the degradation of FD sSOI single transistor dynamic random access memory.

Bipolar Mode Operation and Scalability of Double-Gate Capacitorless 1T-DRAM Cells

In this paper, we study the operation mode and the scalability of the second generation (type II) of double-gate capacitorless one transistor dynamic random access memory (1T-DRAM) cells. We find that the memory operates by accumulating charge at the gate interfaces, not in the body of the cell. The type-II configuration allows an infinitely long retention of state “1,” whereas the total retention time is limited by the leakage associated with state “0” due to band-to-band tunneling (BTBT) at the source/drain to bulk junctions. Extensive and careful scaling analysis shows that longitudinal scaling is limited by short-channel effects related to source/drain to bulk barrier lowering, whereas transverse scaling is limited by BTBT. We conclude that type-II 1T-DRAM is somewhat more scalable than type-I 1T-DRAM (i.e., 15 nm versus 25 nm). The better scaling perspective of type-II 1T-DRAM cells is ascribed to the higher READ sensitivity, programming window, and retention time.

Vertically Self-Aligned Buried Junction Formation for Ultrahigh-Density DRAM Applications

In this letter, we present a novel junction integration scheme that enables vertical transistors to have high performance, low leakage, and easy scalability. Controlled solid-phase diffusion is used to form the vertically self-aligned buried strap junction of the vertical transistor. The electric field at the capacitor node junction is carefully optimized by creating a graded junction profile, resulted from a combination of out-diffusion from Arsenic-doped poly-silicon and Phosphorus-doped oxide. The Phosphorus-doped oxide serves as the dopant source for the vertical lightly doped drain, as well as the spacer for the high dose junctions. Integration of the self-aligned junctions into a vertical transistor dynamic random access memory (DRAM) process flow is presented. Significant improvement in the retention characteristics of a 256-Mb DRAM product confirms the applicability of this newly developed junction integration scheme for future DRAM generations.

A capacitor-less 1T-DRAM cell

A simple true transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI devices to store the logic 1 or 0 binary states. This cell is two times smaller in area than the conventional 8F/sup 2/ 1T/1C DRAM cell and the process of its manufacturing does not require the storage capacitor fabrication steps. This concept will allow the manufacture of simple low cost DRAM and embedded DRAM chips for 100 and sub-100 nm generations.

Oxygen precipitation effects on Si n+-p junction leakage behavior

The effects of oxygen precipitation in (100) Si wafers on junction leakage characteristics are investigated for double polysilicon gate field-effect transistor dynamic random-access memory technology. Experimental data indicate the presence of a very large bulk diffusion leakage current component in the elevated (≳45 °C) temperature range. A simple one-dimensional minority-carrier diffusion model predicts the existence of carrier generation centers at the interface between the precipitate-free and the precipitated regions in the bulk.