Effects of back interface trap states on the fully depleted strained-silicon-on-insulator capacitorless single transistor dynamic random access memory cells

Abstract

A series of systematic experiments were carried out to investigate the effects of silicon back interface state density between silicon channel layer and buried oxide layer on the memory characteristics. The back interface states of fully depleted strained-silicon-on-insulator (FD sSOI) substrate were intentionally generated by controlling the temperature of rapid thermal annealing (RTA) process and the amount of back interface trap was evaluated by using the backgated metal-oxide-semiconductor field-effect transistor method. As a result, the trap density of back interface increased with RTA temperature, which causes the degradation of FD sSOI single transistor dynamic random access memory.