A capacitor-less 1T-DRAM cell

Abstract

A simple true transistor dynamic random access memory (DRAM) cell concept is proposed for the first time, using the body charging of partially-depleted SOI devices to store the logic 1 or 0 binary states. This cell is two times smaller in area than the conventional 8F/sup 2/ 1T/1C DRAM cell and the process of its manufacturing does not require the storage capacitor fabrication steps. This concept will allow the manufacture of simple low cost DRAM and embedded DRAM chips for 100 and sub-100 nm generations.