Transistor Channel Research Articles

(Invited) Technology Scaling from Bulk to Fin and Nano-Sheet Transistors

In recent years, scaling of semiconductor device has progressed, leading to the development of advanced semiconductor devices with code names of below 10-nm. Various new materials and technologies have been introduced to accompany the miniaturization of semiconductor devices. First, the resistivity of aluminum became higher due to miniaturization, and aluminum was replaced by copper as the wiring metal. Then, to increase the gate capacitance of MOS field-effect transistors, the thickness of the gate insulating film (SiO2) was reduced to the limit, and as a result, gate leakage current could no longer be suppressed, which led to the introduction of a high-k gate insulating films (HfO2).The next bottleneck in miniaturization was the suppression of short channel effects. As the gate length became smaller, the gate electrode's control over the channel decreased, resulting in the generation of a small amount of leakage current even when the transistor is turned off, and the threshold voltage also fluctuated as the gate length became shorter, which interfered with circuit operation. To suppress the short-channel effect, the conventional bulk transistor was replaced around 2011 by a transistor with an upright channel, called a fin transistor. The purpose of this is to increase the gate's dominance over the channel, suppress leakage current, and prevent the short-channel effect by having multiple opposing gate electrodes for the raised channel. However, since the channel width of a fin transistor corresponds to the sidewall height, a fin with a high height must be formed to increase the channel width and gain total current density, which has been a problem in terms of processing technology. In addition, in order to increase the current, a layout configuration with multiple fins formed horizontally had to be adopted, which increased the area of the chip, thereby hindering the integration of the chip.This leads to an increase in the area of the chip, which in turn hinders high integration of the chip. The nanosheet transistor is a new transistor structure in which multiple 10-nm-thick "nanosheets" of silicon are stacked in the height direction to form the transistor channel. Another major feature of this nanosheet transistor is the use of a gate all-around structure, which is a further development of the gate structure of the double gate type. As a result, this structure is the most effective in suppressing short channels. Furthermore, by stacking nanosheets vertically, it is possible to increase the current density per unit area without increasing the chip area. As a further evolution of the nanosheet transistor, a complementary FET (CFET) structure is currently being considered, in which pMOS and nMOS are stacked vertically to realize a CMOS circuit in the vertical direction. So far, CFETs with pn stacked in silicon and attempts to form CFETs by laminating silicon and germanium together have been presented. In Japan, research and mass production of this nanosheet type transistor has recently been planned, overtaking mass production of fin transistors.

Influence of the Bound Electron-Hole Pairs Dissociation Probability Field Dependence Form on the Photocurrent and Spatial Resolution of Organic Field Phototransistors

In this work, numerical simulations are used to study ambipolar organic field-effect phototransistors, in which a spatially localized photoelectric effect can take place. This effect consists in the fact that there is a small spatially localized photosensitive region in the transistor channel, the position of which can be controlled by changing the gate voltage. The purpose of this work is to analyze the relationship between the form of the field dependence of the bound electron-hole pairs (𝑒/ℎ pairs) dissociation probability and characteristics of the studied ambipolar phototransistors such as normalized photocurrent, spatial resolution, and response time. It is shown that the optimal form of the field dependence of 𝑒/ℎ pairs dissociation probability is stepwise-like form, which can provide a high spatial resolution at high values of the normalized photocurrent without degrading the response time of the phototransistor. This shape can be achieved when the organic semiconductor has an extremely narrow distribution of 𝑒/ℎ pairs by size, described by the delta function. Also, on the example of several distributions of various shapes, it is shown that a decrease in the width of the distribution leads to an increase in the spatial resolution. Approaches to the selection and modification of organic semiconductor materials that would provide the most pronounced spatially localized photoelectric effect in ambipolar field-effect transistors are discussed.

Self-Expansion Based Multi-Patterning for 2D Materials Fabrication beyond the Lithographical Limit.

Two-dimensional (2D) materials are promising successors for silicon transistor channels in ultimately scaled devices, necessitating significant research efforts to study their behavior at nanoscopic length scales. Unfortunately, current research has limited itself to direct patterning approaches, which limit the achievable resolution to the diffraction limit and introduce unwanted defects into the 2D material. The potential of multi-patterning to fabricate 2D materials features with unprecedented precision and low complexity at large scale is demonstrated here. By combining lithographic patterning of a mandrel and bottom-up self-expansion, this approach enables pattern resolution one order of magnitude below the lithographical resolution. In-depth characterization of the self-expansion double patterning (SEDP) process reveals the ability to manipulate the critical dimension with nanometer precision through a self-limiting and temperature-controlled oxidation process. These results indicate that the SEDP process can regain the quality and morphology of the 2D material, as shown by high-resolution microscopy and optical spectroscopy. This approach is shown to open up new avenues for research into high-performance, ultra-scaled 2D materials devices for future electronics.

Comprehensive Study of Contact Length Scaling Down to 12 nm With Monolayer MoS2 Channel Transistors

Comprehensive Study of Contact Length Scaling Down to 12 nm With Monolayer MoS₂ Channel Transistors

Ultrasensitive Carbon Monoxide Gas Sensor at Room Temperature Using Fluorine-Graphdiyne.

Currently, most carbon monoxide (CO) gas sensors work at high temperatures of over 150 °C. Developing CO gas sensors that operate at room temperature is challenging because of the sensitivity trade-offs. Here, we report an ultrasensitive CO gas sensor at room temperature using fluorine-graphdiyne (F-GDY) in which electrons are increased by light. The GDY films used as channels of field-effect transistors were prepared by using chemical vapor deposition and were characterized by using various spectroscopic techniques. With exposure to UV light, F-GDY showed a more efficient photodoping effect than hydrogen-graphdiyne (H-GDY), resulting in a larger negative shift in the charge neutral point (CNP) to form an n-type semiconductor and an increase in the Fermi level from -5.27 to -5.01 eV. Upon CO exposure, the negatively shifted CNP moved toward a positive shift, and the electrical current decreased, indicating electron transfer from photodoped GDYs to CO. Dynamic sensing experiments demonstrated that negatively charged F-GDY is remarkably sensitive to an electron-deficient CO gas, even with a low concentration of 200 parts per billion. This work provides a promising solution for enhancing the CO sensitivity at room temperature and expanding the application of GDYs in electronic devices.

Review of: "The changes in the width of the nano transistor channel due to the field effect of the gate around can cause undesirable changes and loss of mobility"

Review of: "The changes in the width of the nano transistor channel due to the field effect of the gate around can cause undesirable changes and loss of mobility"

Effects of Thermal Boundary Resistance on Thermal Management of Gallium-Nitride-Based Semiconductor Devices: A Review.

Wide-bandgap gallium nitride (GaN)-based semiconductors offer significant advantages over traditional Si-based semiconductors in terms of high-power and high-frequency operations. As it has superior properties, such as high operating temperatures, high-frequency operation, high breakdown electric field, and enhanced radiation resistance, GaN is applied in various fields, such as power electronic devices, renewable energy systems, light-emitting diodes, and radio frequency (RF) electronic devices. For example, GaN-based high-electron-mobility transistors (HEMTs) are used widely in various applications, such as 5G cellular networks, satellite communication, and radar systems. When a current flows through the transistor channels during operation, the self-heating effect (SHE) deriving from joule heat generation causes a significant increase in the temperature. Increases in the channel temperature reduce the carrier mobility and cause a shift in the threshold voltage, resulting in significant performance degradation. Moreover, temperature increases cause substantial lifetime reductions. Accordingly, GaN-based HEMTs are operated at a low power, although they have demonstrated high RF output power potential. The SHE is expected to be even more important in future advanced technology designs, such as gate-all-around field-effect transistor (GAAFET) and three-dimensional (3D) IC architectures. Materials with high thermal conductivities, such as silicon carbide (SiC) and diamond, are good candidates as substrates for heat dissipation in GaN-based semiconductors. However, the thermal boundary resistance (TBR) of the GaN/substrate interface is a bottleneck for heat dissipation. This bottleneck should be reduced optimally to enable full employment of the high thermal conductivity of the substrates. Here, we comprehensively review the experimental and simulation studies that report TBRs in GaN-on-SiC and GaN-on-diamond devices. The effects of the growth methods, growth conditions, integration methods, and interlayer structures on the TBR are summarized. This study provides guidelines for decreasing the TBR for thermal management in the design and implementation of GaN-based semiconductor devices.

High-Performance and Low-Power p-Channel Transistors Based on Monolayer Be2C.

The advantages of 2D materials in alleviating the issues of short-channel effect and power dissipation in field-effect transistors (FETs) are well recognized. However, the progress of complementary integrated circuits has been stymied by the absence of high-performance (HP) and low-power (LP) p-channel transistors. Therefore, we conducted an investigation into the electronic and ballistic transport characteristics of monolayer Be2C, which features quasi-planar hexacoordinate carbons, by employing nonequilibrium Green's function combined with density functional theory. Be2C monolayer has planar anticonventional bonds and a direct bandgap of 1.53 eV. The Ion of p-type Be2C HP FETs can achieve a remarkable 2767 μA μm-1. All of the device properties of 2D Be2C FETs can exceed the demands of the International Roadmap for Devices and Systems. The excellent properties of Be2C as a 2D p-orbital material with a high hole mobility are discussed from different aspects. Our findings thus illustrate the tremendous potential of 2D Be2C for the next generation of HP and LP electronics applications.

Tungsten-Doped Indium Tin Oxide Thin-Film Transistors for Dual-mode Proximity Sensing Application.

Technologies for human-machine interactions are booming now. In order to achieve multifunctional sensing abilities of electronic skins, further developments of various sensors are in urgent demand. Herein, a dual-mode proximity sensor based on an oxide thin-film transistor (TFT) is reported. Although InSnO (ITO) is featured with high mobility, the inherent high carrier concentration limits its use as a channel material for thin-film transistors. Herein, the tungsten element was introduced as a carrier suppressor to develop ITO-based semiconducting materials and devices. TFTs with amorphous tungsten-doped ITO (ITWO) channel layers were fabricated. As for a flat panel display application, the TFT device from 250 °C-annealed ITWO layer with an atomic ratio of In/Sn/W = 86:9:5 presented the optimal device performance with carrier mobility of 11.53 cm2 V-1 s-1, swing subthreshold of 0.66 V dec-1, threshold voltage of -2.18 V, and Ion/Ioff ratio of 3.33 × 107 and much small hysteresis of transfer characteristic. ITWO TFT devices were further developed as dual-mode proximity sensors that could work with both extended-gate and compact configurations, where the drain current was directly related to the surface potential of a charged object and the distance between the sensing end and the object, enabling the proximity sensing of charged stimuli. For extended-gate-configured proximity sensing, a charged object modulated the formation of a conductive channel at the semiconductor/SiO2 interface, while this conductive channel occurred at the semiconductor/air interface for compact-configured sensing. Formation of the conductive channel of the compact transistor was modulated by the electric field component in the direction perpendicular to the interface, and the drain current was sensitive to the orientation of the approaching object, which implied the capacity of angle sensing to the approach of a charged object. This work further emphasizes that the basic device performance should be optimized according to its specific application scenarios rather than only considering the requirements of the panel display.

Simulation of vertical ballistic quantum-barrier field-effect transistor based on undoped AlxGa1–xAs quantum nanowire

A design-topological solution for a tunnel field-effect transistor of a new type is proposed and the simulation of the transistor is performed. The device is a vertical ballistic field-effect transistor with a cylindrical metallic gate based on a cylindrical undoped AlxGa1–xAs quantum nanowire located in an Al2O3 matrix. For a given geometry of the device structure, the optimum of the fraction of aluminum in the semiconductor composition varying along the transistor channel is found, at which, unlike a conventional tunnel field-effect transistor, not only the complete suppression of the quantum barrier for electrons by a positive gate voltage is ensured, but also the minimum possible electrical resistance of the transistor channel. The current-voltage characteristics of the transistor are calculated within the framework of a rigorous quantum-mechanical description of the electron transport in its channel, taking into account the non-parabolic nature of the band structure of the semiconductor.

High-Performance Vertical Light-Emitting Transistors Based on ZnO Transistor/Quantum-Dot Light-Emitting Diode Integration and Electron Injection Layer Modification.

Vertical light-emitting transistors (VLETs) consisting of vertically stacked unipolar transistors and organic light-emitting diodes (OLEDs) have been proposed as a prospective building block for display technologies. In addition to OLEDs, quantum-dot (QD) LEDs (QLEDs) with high brightness and high color purity have also become attractive light-emitting devices for display applications. However, few studies have attempted to integrate QLEDs into VLETs, as this not only involves technical issues such as compatible solution process of QDs and fine patterning of electrodes in multilayer stacked geometries but also requires a high driving current that is demanding on transistor design. Here we show that these integration issues of QLEDs can be addressed by using inorganic transistors with robust processability and high mobility, such as the studied ZnO transistor, which facilitates simple fabrication of QD VLETs (QVLETs) with efficient emission in the patterned channel area, suitable for high-resolution display applications. We perform a detailed optimization of QVLET by modifying ZnO:polyethylenimine nanocomposite as the electron injection layer (EIL) between the integrated ZnO transistor/QLED, and achieve the highest external quantum efficiency of ~3% and uniform emission in the patterned transistor channel. Furthermore, combined with a systematic study of corresponding QLEDs, electron-only diodes, and electroluminescence images, we provide a deeper understanding of the effect of EIL modification on current balance and distribution, and thus on QVLET performance.

Effects of Mg Doping to a LiCoO2 Channel on the Synaptic Plasticity of Li Ion-Gated Transistors.

Artificial synapses with ideal functionalities are essential in hardware neural networks to allow for energy-efficient analog computing. However, the realization of linear and symmetric weight updates in real synaptic devices has proven challenging and ultimately limits the online training capabilities of neural network systems. Herein, we investigate the effect of Mg doping on a LiCoO2 (LCO) channel in a Li ion-gated synaptic transistor, so as to improve long-term and short-term plasticity. Two transistor structures, based on a lithium phosphorus oxynitride electrolyte, were examined by using undoped LCO and Mg-doped LCO as the channel material between the source and drain electrodes. It was found that Mg doping increased the initial channel conductance by 3 orders of magnitude, which is probably due to the substitution of Co3+ by Mg2+ and the compensation of hole creation. It was further found that the doped channel transistor showed good retention characteristics and better linearity of long-term potentiation and depression when voltage pulses were applied to the gate electrode. The improved retention and linearity are attributed to an extended range of the insulator-to-conductor transition by Mg doping and Li-ion extraction/insertion cooperated in the LCO channel. Using the obtained synaptic weight update, artificial neural network simulations demonstrated that the doped channel transistor shows an image recognition accuracy of ∼80% for handwritten digits, which is higher than ∼65% exhibited by the undoped channel transistor. Mg doping also improved short-term plasticity such as paired-pulse facilitation/depression and Hebbian spike timing-dependent plasticity. These results indicate that elemental doping to the channel of Li ion-gated synaptic transistors could be a useful procedure for realizing robust neuromorphic systems based on analog computing.

MISHEMT intrinsic voltage gain under multiple channel output characteristics

In this paper the MISHEMT device (metal/Si3N4/AlGaN/AlN/GaN - metal–insulator–semiconductor high electron mobility transistor) is studied focusing mainly on the impact of the multiple conductions on the intrinsic voltage gain (A v). It is shown that the total drain current is composed of three different drain current components, whereof one is related to the MIS channel and the other two are related to high electron mobility transistor (HEMT) channels. The device output characteristics present double drain voltage saturation that gives rise to a double plateau in the saturation region of the output characteristics. This behavior relies also on the gate voltage, so the output characteristics and analog parameters extraction are bias dependent. The intrinsic voltage gain increases thanks to the early voltage increment in the second plateau where HEMT conduction is dominant. Electron concentration profiles were simulated in order to investigate the device saturation regime.

High-performance tin oxide field-effect transistors deposited by thermal atomic layer deposition

In this study, we investigated the impact of annealing ambient on the performance of SnO2-based field-effect transistors (FETs) while adhering to the thermal budget constraint (process temperature < 450 °C). The SnO2 films were deposited by thermal atomic layer deposition (T-ALD). After annealing the films for 2 h at 400 °C, it was observed that annealing in an O2 ambient resulted in a SnO2 film with an excessive number of background carriers, which made it difficult to fully deplete the channel. Conversely, annealing in an N2 ambient led to an unstable channel that could not be effectively modulated, despite having a carrier concentration about an order of magnitude lower than that of the O2-annealed film. Surprisingly, the devices annealed in an air ambient exhibited the best performance. X-ray photo-emission spectroscopy revealed that annealing in O2 ambient resulted in a higher level of oxygen vacancy, while N2 annealing was more effective in creating stoichiometric SnO. The best device performance achieved in this study was observed in a 6-nm thick channel that was annealed in the air. This device exhibited an on/off ratio of 1.2 × 1011, subthreshold swing of 0.4 V/dec., field-effect mobility of 14.6 cm2/V·s, and threshold voltage of 1.1 V, operating in an enhancement mode. These results emphasize the potential of ALD SnO2 channels for high-performance transistors that are compatible with back-end-of-line processes in Si technology.

A Subthreshold Biased CMOS Ring Oscillator Model Design in 180-nm Process

In this paper, a 180-nm CMOS ring oscillator design, made with halo-implanted transistors and operating in the weak inversion region, is proposed, based on an undergraduate integrated circuit design course methodology for building logic gates and comparing simulated results with reviewed literature data. Halo-implanted channel transistors have a steeper and less distorted voltage characteristic curve compared to uniformly doped channel ones, which makes them a more appropriate option when designing asynchronous digital integrated circuits aimed at low bias and low power. Three gate models were created using weak inversion and pull-up and pull-down networks made with halo-implanted transistors. The results of the study and simulation of the three inverter digital gate topologies showed that the NOT inverter model, as expected, had a higher frequency than the NAND and NOR inverter models. The ring oscillators made with the NOT inverter came up with an 8.25-MHz switching frequency as well as a dynamic power close to 270 nW. A comparison with other ring oscillators from previous studies is also shown.

Synthesis, Properties, and Application of Ultrathin and Flexible Tellurium Nanorope Films: Beyond Conventional 2D Materials.

Nanomaterials that can be easily processed into thin films are highly desirable for their wide range of applicability in electrical and optical devices. Currently, Te-based 2D materials are of interest because of their superior electrical properties compared to transition metal dichalcogenide materials. However, the large-scale manufacturing of these materials is challenging, impeding their commercialization. This paper reports on ultrathin, large-scale, and highly flexible Te and Te-metal nanorope films grown via low-power radiofrequency sputtering for a short period at 25°C. Additionally, the feasibility of such films as transistor channels and flexible transparent conductive electrodes is discussed. A 20 nm thick Te-Ni-nanorope-channel-based transistor exhibits a high mobility (≈450 cm2 V-1 s-1 ) and on/off ratio (105 ), while 7 nm thick Te-W nanorope electrodes exhibit an extremely low haze (1.7%) and sheet resistance (30 Ω sq-1 ), and high transmittance (86.4%), work function (≈4.9eV), and flexibility. Blue organic light-emitting diodes with 7 nm Te-W anodes exhibit significantly higher external quantum efficiencies (15.7%), lower turn-on voltages (3.2V), and higher and more uniform viewing angles than indium-tin-oxide-based devices. The excellent mechanical flexibility and easy coating capability offered by Te nanoropes demonstrate their superiority over conventional nanomaterials and provide an effective outlet for multifunctional devices.

(Invited) Cryogenic Electronics for Quantum Computing ICs: What Can Bring FDSOI

To design efficient quantum computers, conventional electronics is required as close as possible to the quantum bit (qubit) devices, considering either superconducting or Si-spin qubits, for the read-out and control, thus reducing the need for wiring toward room temperature [1]. This need highlights the broad importance of exploring and developing low-temperature CMOS technologies, with operation temperatures ranging from 4.2K down to well below 1K. Moreover, the Si-spin qubit process is also compatible with the CMOS process, allowing both of them, in principle, to be monolithically integrated on a single chip [2], [3]. This could provide an essential building block for any large-scale quantum processors, by enabling the design of scalable close-to-qubit cryogenic electronics for massive qubit matrix indexation and, ultimately, development of fault-tolerant universal gate-based quantum computers [4].In this approach, FDSOI technologies appear as a valuable solution, with their unique property of being able to adjust its threshold voltage (Vth) as a function of the temperature by the mean of a back bias VB. FDSOI thus enables high performance and low-power electronics. However, there is currently no process design kit to design CMOS circuits at cryogenic temperature, whatever the technology node considered. Therefore, extensive electrical characterization is required, with the aim of building a future cryogenic compact model, or at least of providing analytical and physics based models to designers in order to help them to optimize their circuits [5].In this work, we present an overview of the performances of FDSOI CMOS technology down to deep cryogenic temperature, with specific attention to devices electrostatics, variability or thermal effects. Because these aspects are essential for the development of compact models and robust design tools, we present recent progresses in electrical characterization and analysis of FDSOI MOSFETs down to 100mK, and the underlying physics, highlighting the effect of the back bias VB.We show that transistors can fully operate down to 100mK, keeping the same efficiency of the back bias on the threshold voltage [6]. Overall performances are mostly improved at low temperature, with e.g. a high reduction of the subthreshold slope and of the off current, or a higher transconductance maximum value due to higher carrier mobility. The tunability of the threshold voltage on a wide range through the back-bias offers a great advantage to the FDSOI technology, allowing improved performances [7] and the optimization of circuit in cryogenic environment [8], [9]. Other important electrical characteristics have also been investigated down to very low temperature, such as variability and mismatch properties [7], [10], or low frequency noise [11]. As a result, we show that FDSOI technology can outperform other CMOS technologies in cryogenic operation.Thermal effects, which play a fundamental role in cryogenic electronics – operating at various temperature stages, with limited cooling power. The study of self-heating effects at cryogenic temperature in this regard provides valuable information on how to manage thermal effects, and is discussed [7], [15].Finally, modeling issues are also addressed. Besides serious numerical difficulties due to singularities appearing at low temperature when solving model equations, the change of important physical parameters (like carrier mobility, thermal conductivity,...) needs to be correctly taken into account in future compact or analytical models. In addition, new physical effects evidenced at low temperature also need to be understood, analytically modeled and included as well. In particular, transport exhibits evidence of strong intersubband scattering in the channel of thin film FDSOI transistors [12]. The equations describing the sub-threshold regime are also strongly modified [13], [14].[1] E. Charbon et al., IEDM, 2016.[2] P. Galy et al., IEEE J. Electron Devices Soc., 2018.[3] L. Le Guevel et al., Appl. Phys. Rev., 2020.[4] X. Xue et al., Nature, 2021.[5] C. Enz et al., EDM, 2020[6] B. Cardoso Paz et al., EUROSOI-ULIS, 2020.[7] M. Cassé et al., to be published in IEDM, 2022.[8] H. Bohuslavskyi et al., IEEE Trans. Electron Devices, 2018.[9] L. Le Guevel et al., ISSCC, 2020.[10] B. Cardoso Paz et al., VLSI, 2020.[11] B. Cardoso Paz et al., IEEE Trans. Electron Devices, 2020.[12] M. Cassé et al., Appl. Phys. Lett., 2020.[13] H. Bohuslavskyi et al., IEEE Electron Device Lett., 2019.[14] G. Ghibaudo et al., Solid. State. Electron., 2020.[15] K. Triantopoulos et al., IEEE Trans. Electron Devices, 2019.

(Invited) ISFET-Based Sensors

The big difference between an ISFET (Ion Sensitive Field Effect Transistor) and a conventional MOSFET (Metal Oxide Semiconductor FET) is contained in the absence of the upper electrode on the gate oxide of the device, as shown in Figures 1 (a) and 1(b), respectively. In the case of an ISFET (Figure 1(a)), the gate reference electrode with the solution (of chemical or biological materials), which is in contact with the gate oxide (dielectric), work as the upper electrode, inducing the channel in the semiconductor and enabling the conduction of electric current between source and drain terminals. On these two terminals, there are the polymer layers as barrier against chemical or biological solutions. Therefore, the choice of the gate oxide is of great importance, since it must present chemical stability when in contact with the solution that will be measured. The solution pH is the main parameter which is measured. The gate dielectric chosen for application as a pH sensor must carry out measurements in acidic and basic media and be capable of forming hydrogen bonds. This ability is associated with atoms that have greater electronegativity such as fluorine, oxygen and nitrogen. Furthermore, the water contamination metals, DNA, RNA, enzymatic, antigen-antibody and cell related detections can be obtained by ISFETs.Thus, thin films of SiNx, TiOx, TaOx, AlOx and AlN were chosen as gate dielectrics because are compatible to chemical or biological substances. Various results from literature will be present. For example, pH ISFET devices with silicon nitride (SiNx) as gate dielectric were fabricated [2]. Silicon nitride (SiNx) films have been obtained by Low Pressure Chemical Vapor Deposition (LPCVD) at temperature of 720oC for 30 min, using different ratios of [SiH2Cl2]/[NH3] reagent gases. These films been used as ISFET gate dielectric. Figure 2 presents a characteristic of the current between source and drain (IDS) versus voltage between source and gate (VGS) of ISFETs (for voltage VDS of 2V) in related to the four values of pH solution. In this case, sensibility of S=51mV/pH [2]. was estimated, which is close to the expected 59mV/pH determined by the Nernst limit. Other application: Controlling the water quality has become an important issue nowadays, especially due to its contamination along the years which may cause significant damage to human health and in this context, phosphate in water reuse or lead deserves a great attention. The Electrolyte-Insulator-Semiconductor (EIS) structure, which is similar to the gate structure of ISFETs, with TiO2 thin films as gate dielectric, were fabricated and Capacitance x Voltage (CxV) curves to estimate the sensitivity values through the flat-band voltage variation for each curve. In order to enhance the Pb+ detection an additional cerium phosphate layer (TiO2 surface functionalization) was deposited over the TiO2 thin film as selective membrane for Pb+ measurements and the device presented 40 mV/100 ppm sensitivity. For the case of phosphate detection in waste water, EIS devices with TiO2 films as gate dielectric, without functionalization layer, were used and the good sensitivity to phosphate ions of 66 mV/ppm was obtained. Most of results with ISFET devices are based on Si semiconductor conduction channel between the source and drain regions. Others materials have been used as conduction channels of transistors, such as 2D layer, mainly graphene. One example is the biosensor based on Graphene Field Effect Transistor (GraFET), using the TiO2 dielectric gate, capable of being applied effectively for early diagnosis of COVID-19. The graphene channel has ten parallel ribbons, and the virus of SARS-Cov-2 interacts with the unprotected TiO2 gate dielectric. Unlike rapid tests, which depend on the body's immune response (production of IgM and/or IgG antibodies), this project seeks to detect components of the infectious agent itself. It makes graphene-based biosensors very advantageous compared to current tests available since there will be no dependence on the immune response to infection by COVID-19 but only on the presence of the virus in the tested samples. Thus, these devices can reduce the time involved in the analyses.In conclusion, as observed in this review, the ISFET devices are mandatory sensors to develop the future instrumentation, because allow the detection of various chemical and biological species, using different materials as gate dielectrics or electrodes, and conduction channels. Figure 1

Surface functionalized electrolyte-gated perovskite transistors with enhanced performance via insulating polymer additive

Perovskite–polymer microstructure engineering enables outstanding performance and improved stability in perovskite-based electronic devices. Here, we report perovskite/insulating polymer composite as engineered semiconductors for the simultaneous enhancement of the carrier mobility and environmental stability of electrolyte-gated field-effect transistors (FETs). To this end, we employed conventional poly(methyl methacrylate) (PMMA) and fluorinated poly(vinylidene fluoride-co-hexafluoropropylene) (P(VDF-HFP)) insulating polymers. The structural properties of the fabricated perovskite–polymer semiconductors were tuned by controlling the amount of insulating polymer in the perovskite–polymer composites. The optimized methylammonium lead iodide (MAPbI3) perovskite–PMMA-based FETs with a poly(3-hexylthiophene-2,5-diyl) (P3HT) surface passivation layer exhibited a highly-stable operation with a hole mobility of approximately 20 cm2 V−1 s−1 at ≤ 1.5 V and current on/off ratio of ∼103, which exceeds that of the MAPbI3-P(VDF-HFP)-based FETs under highly humid conditions (relative humidity ≈ 60–70%). This exceptional performance of our devices was attributed to the improved injection properties, increased grain size, and passivation of grain boundariesin the transistor channel coupled with the hydrophobic nature, and resistance of the insulating polymers to humidity. This study provide insights into achieving high-performance and environmentally stable perovskite transistor devices through combined bulk and surface passivation.

An investigation into the reliability of newly proposed MoSi2N4/WSi2N4 field-effect transistors: A Monte Carlo study

Recently, the two dimensional complex MA2Z4 structures have been suggested as suitable replacements for silicon channels in field-effect transistors (FETs). Specifically, two materials of MoSi2N4 and WSi2N4 due to their very desirable electrical and thermal properties are noticed. On the other hand, the reliability of transistors, which is determined by the maximum temperature they obtain during the performance, specifies the usefulness of the newly proposed channels for thermal management solution. In this work, the FETs, including MoSi2N4 and WSi2N4 channels, are investigated using Monte Carlo simulation of the phonon Boltzmann equation. In particular, the phonon analysis has been carried out to investigate the peak temperature rise. Our calculations confirm that MoSi2N4 and WSi2N4 present lower maximum temperature than the previously suggested candidate, the blue phosphorene (BP) which itself reaches a shallow temperature. Concretely, the phonon exploration shows that the competition between the dominant heat carrier velocity, and its related frequency settles the maximum temperature value. The material WSi2N4 with much more phonons in TA mode, with almost high velocity and relatively low-frequency, shows adequate thermal condition, and its peak temperature is very low, say 110 K, less than that of BP. The material MoSi2N4 attains the maximum temperature of only 10 K less than BP peak temperature. This behavior attributes to the dominant LA phonons which are fast but also have high frequency and consequently make the temperature get larger than that of the WSi2N4. In summary, WSi2N4, with very low peak temperature, and in the next step MoSi2N4, both with beneficial electrical/thermal properties, are suggested as very suitable candidates for producing more reliable FETs, fulfilling the thermal management.