Transfer Magnetic Random Access Memory Research Articles

Deep-Learning-Based Adaptive Error-Correction Decoding for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)

Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising emerging non-volatile memory (NVM) technology with wide applications. However, the data recovery of STT-MRAM is affected by the diversity of channel raw bit error rate (BER) across different dies caused by process variations, as well as the unknown resistance offset due to temperature change. Therefore, it is critical to develop effective decoding algorithms of error correction codes for STT-MRAM. In this paper, we first propose a neural bit-flipping (BF) decoding algorithm, which can share the same trellis representation as the state-of-the-art neural decoding algorithms, such as the neural belief propagation (NBP) and neural offset min-sum (NOMS) algorithm. Hence a neural network (NN) decoder with a uniform architecture but different NN parameters can realize all these neural decoding algorithms. Based on such a unified NN decoder architecture, we further propose a novel deep learning (DL)-based adaptive decoding algorithm whose decoding complexity can be adjusted according to the change of the channel conditions of STT-MRAM. Extensive experimental evaluation results demonstrate that the proposed neural decoders can greatly improve the performance over the standard decoders, with similar decoding latency and energy consumption. Moreover, the DL-based adaptive decoder can work well over different channel conditions of STT-MRAM irrespective of the unknown resistance offset, with a 50% reduction of the decoding latency and energy consumption compared to the fixed decoder.

Sparse Code With Minimum Hamming Distance of Three for Spin-Torque Transfer Magnetic Random Access Memory

Sparse Code With Minimum Hamming Distance of Three for Spin-Torque Transfer Magnetic Random Access Memory

Improving Bit-Error-Rate Performance Using Modulation Coding Techniques for Spin-Torque Transfer Magnetic Random Access Memory

In non-volatile random-access memory (RAM) technologies, the spin-torque transfer magnetic random-access memory (STT-MRAM) is a promising candidate. STT-MRAM has attracted attention owing to its advantages, such as a high density, high endurance, and high-speed writing/reading. Moreover, STT-MRAM is utilized to replace dynamic random-access memory (DRAM) in Internet of Things (IoT) and artificial intelligence (AI) applications. However, because the magnetic tunnel junction is used to write data, STT-MRAM must face process variation and thermal fluctuation problems. This causes errors in writing and reading processes. These errors are independent of each other. Therefore, to solve them and increase the reliability of STT-MRAM, the data are encoded before storage in STT-MRAM devices. In this study, we propose a method for designing codewords using modulation coding techniques. Our codewords increase the minimum Hamming distance and inheritance of the sparse code characteristic to exploit the asymmetric probability of the write errors. The simulation results show that our codewords can improve the bit error rate performance of STT-MRAM compared with previous works.

Polar Code and Symbol Mapping Design for Multi-Level Cell Spin-Torque Transfer Magnetic Random Access Memory

Multi-level-cell (MLC) spin-torque transfer magnetic random access memory (STT-MRAM) suffers from reliability issues due to the highly asymmetric error rates of its hard and soft domains. In this communication, we have proposed to include a symbol mapper prior to writing bits to the MRAM and have jointly optimized the mapping and polar codes with iterative, soft-cancellation (SCAN) decoder. Specifically, we perform code search and symbol mapping based on the extrinsic information transfer curves of <i>a posteriori</i> probability demapper and the SCAN decoder. We identify a number of variations of Gray code-based mappings, each promising best waterfall, convergence, and/or error-floor performances. In particular, our simulation results demonstrate that one of our proposed mapping achieves a bit-error-rate which is nearly three orders of magnitude lower than that of the conventional binary mapping and outperforms other Gray-code variants at a resistance spread up to 18&#x0025; and hard bit write errors up to multiples of 10^&#x2212;3.

Union Bound Analysis for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM) With Channel Quantization

As an emerging non-volatile memory (NVM) technology, spin-torque transfer magnetic random access memory (STT-MRAM) has received great attention in recent years since it combines the features of low switching energy, fast write/read speed, and high scalability. However, process variation and thermal fluctuation severely affect the data integrity of STT-MRAM, resulting in both write errors and read errors. Therefore, effective error correction codes (ECCs) are necessary for correcting memory cell errors. Meanwhile, the design of channel quantizer plays a critical role in supporting error correction coding for STT-MRAM. In this work, we propose a union bound analysis which can accurately predict the word error rates (WERs) of ECCs with maximum-likelihood (ML) decoding over the quantized STT-MRAM channel. The derived bound provides a theoretical tool for comparing the performance of ECCs with different quantization schemes at very low error rate levels without resorting to lengthy computer simulations. Moreover, we also propose a new criterion to design the channel quantizer by minimizing the WERs of ECC decoding that are obtained from the union bound analysis. Numerical results show that the proposed union-bound-optimized (UBO) quantizer can achieve better error rate performance than the state-of-art quantizers for STT-MRAM.

Deep Learning-Based Decoding of Linear Block Codes for Spin-Torque Transfer Magnetic Random Access Memory

Thanks to its superior features of fast read/write speed and low power consumption, spin-torque transfer magnetic random access memory (STT-MRAM) has become a promising non-volatile memory (NVM) technology that is suitable for many applications. However, the reliability of STT-MRAM is seriously affected by the variation of the memory fabrication process and the working temperature, and the later will lead to an unknown offset of the channel. Hence, there is a pressing need to develop more effective error correction coding techniques to tackle these imperfections and improve the reliability of STT-MRAM. In this work, we propose, for the first time, the application of deep-learning (DL)-based algorithms and techniques to improve the decoding performance of linear block codes with short codeword lengths for STT-MRAM. We formulate the belief propagation (BP) decoding of linear block code as a neural network (NN) and propose a novel neural normalized-offset reliability-based min-sum (RB-MS) (NNORB-MS) decoding algorithm. We successfully apply our proposed decoding algorithm to the STT-MRAM channel through channel symmetrization to overcome the channel asymmetry. We also propose an NN-based soft information generation method (SIGM) to take into account the unknown offset of the channel. Simulation results demonstrate that our proposed NNORB-MS decoding algorithm can achieve significant performance gain over both the hard-decision decoding (HDD) and the regular RB-MS decoding algorithm, for cases without and with the unknown channel offset. Moreover, the decoder structure and time complexity of the NNORB-MS algorithm remain similar to those of the regular RB-MS algorithm.

On Channel Quantization for Spin-Torque Transfer Magnetic Random Access Memory

As emerging memories such as spin-torque transfer magnetic random access memory (STT-MRAM) suffer from reliability issues caused by process variations and thermal fluctuations, the design of channel quantizer with the minimum number of quantization bits is critical to support effective error correction coding for ensuring high-density and high-speed memory data storage. In this paper, we first propose a quantized channel model for STT-MRAM. Based on the quantized channel model, we derive various information theoretic bounds, including the mutual information, cutoff rate, and the Polyanskiy-Poor-Verdu (PPV) finite-length performance bound. By using these bounds as design criteria, we optimize the quantizer design for the polar-coded STT-MRAM channel. Moreover, we also propose a polar-code-specific quantization design with the successive cancellation decoding algorithm, by using the block error probability bound obtained from density evolution (DE). Simulation results show that all our proposed quantizers generally outperform the prior art greedy merging quantizer. In addition, both the cutoff rate and PPV bound based quantizers outperform the most widely applied mutual information based quantizer for short-length polar codes with 2-bit quantization. Furthermore, the DE quantizer designed specifically for polar codes achieves the best performance among all the proposed quantizers.

Reduced Exchange Interactions in Magnetic Tunnel Junction Free Layers with Insertion Layers

Perpendicularly magnetized CoFeB layers with ultra-thin non-magnetic insertion layers are very widely used as the electrodes in magnetic tunnel junctions for spin transfer magnetic random access memory devices. Exchange interactions play a critical role in determining the thermal stability of magnetic states in such devices and their spin torque switching efficiency. Here the exchange constant of free layers incorporated in full magnetic tunnel junction layer stacks, specifically CoFeB free layers with W insertion layers is determined by magnetization measurements in a broad temperature range. A significant finding is that the exchange constant decreases significantly and abruptly with W insertion layer thickness. The perpendicular magnetic anisotropy shows the opposite trend; it initially increases with W insertion layer thickness and shows a broad maximum for approximately one monolayer (0.3 nm) of W. These results highlight the interdependencies of magnetic characteristics required to optimize the performance of magnetic tunnel junction devices.

A Study of Read Margin Enhancement for 3T2R Nonvolatile TCAM Using Adaptive Bias Training

In this paper, we propose an adaptive-bias-training circuit for enhancing the read reliability of ternary content-addressable memory (TCAM), which is implemented with resistive nonvolatile memories such as spin–torque transfer magnetic random access memory (STT-MRAM) and PRAM. The 3T2R nonvolatile-based TCAM (nvTCAM) is area-efficient, yet vulnerable to the process variation with fixed bias condition that affects the sensing margin. With adaptive bias training, the 3T2R nvTCAM cell can maintain a sufficient sensing margin when combined with a high-performance STT-MRAM with a resistance ratio (R-ratio) as low as 3.0. The foreground train followed by the on-the-fly track compensates for variations in the resistances of memory cells, threshold voltage, and substrate temperature. We evaluated the proposed bias technique using the 180-nm CMOS process with 1.8 V of VDD. The search speed is enhanced by 50% at a 64-bit word length, and the sensing margin is improved by 20%. Using our proposed bias technique, the read error rate induced by the variability is estimated to be contained below 1 ppb at an R-ratio of 2, indicating the decent productivity of gigabit density nvTCAM with STT-MRAM.

Design of Rate-Compatible Protograph LDPC Codes for Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)

Thanks to its superior features of non-volatility, fast read/write speed, high endurance, and low power consumption, spin-torque transfer magnetic random access memory (STT-MRAM) has become a promising candidate for the next generation non-volatile memories (NVMs) and storage class memories (SCMs). However, it has been found that the write errors and read errors caused by thermal fluctuation and process variation severely degrade the reliability of STT-MRAM. Moreover, process imperfection also causes a diversity of the raw bit error rate (BER) among different dies of STT-MRAM. In this paper, we propose the design of novel rate-compatible protograph low-density parity-check (RCP-LDPC) codes to correct memory cell errors and mitigate the raw BER diversity of STT-MRAM. In particular, to deal with the asymmetric property of the STT-MRAM channel, we first apply an independent and identically distributed (i.i.d.) channel adapter to symmetrize the STT-MRAM channel. We then present a modified protograph extrinsic information transfer (P-EXIT) algorithm for the symmetrized STT-MRAM channel. We further propose a combined guideline, including the modified P-EXIT algorithm, the asymptotic weight enumerator (AWE) analysis, as well as the actual error rate performance, for designing protograph LDPC codes with short information word lengths for STT-MRAM. By further applying a code extension approach, we design novel RCP-LDPC codes that can work with a single encoder/decoder. Simulation results show that our proposed RCP-LDPC codes outperform the well-known rate-compatible AR4JA protograph codes as well as the fixed-rate quasi-cyclic (QC) LDPC codes in terms of both the error rate performance and the convergence speed over the STT-MRAM channel.

A Multilevel Cell STT-MRAM-Based Computing In-Memory Accelerator for Binary Convolutional Neural Network

Due to additive operation’s dominated computation and simplified network in binary convolutional neural network (BCNN), it is promising for Internet of Things scenarios which demand ultralow power consumption. By means of fully exploiting the in-memory computing advantages and low current consumption design using multilevel cell (MLC) spin-toque transfer magnetic random access memory (STT-MRAM), this paper proposes an MLC-STT-computing in-memory-based computing in-memory architecture to achieve convolutional operation for BCNN to further reduce the power consumption. Simulation results show that compared with the resistive random access memory (RRAM)- and spin orbit torque-STT-MRAM-based counterparts, the architecture proposed in this paper reduces power consumption by ~ $35{\times}$ and 59% in Modified National Institute of Standards and Technology data set, respectively.

Polar Codes for Spin-Torque Transfer Magnetic Random Access Memory

Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising non-volatile memory (NVM) technology due to its superior performance in terms of power consumption, write/read speed, endurance, and scalability. However, the reliability of STT-MRAM is affected by the process variation and thermal fluctuation, leading to both the write errors and read errors. Hence, it is important to develop error correction coding schemes to correct the memory cell errors and improve the system reliability. In this paper, we propose, for the first time, the design and optimization of polar codes for the STT-MRAM channel. In particular, as the STT-MRAM channel is asymmetric by nature, we first adopt an approach to symmetrize the channel so as to facilitate the design of effective polar codes. We then apply the density evolution method to construct polar codes and optimize their performance for the STT-MRAM channel. Furthermore, in order to mitigate the raw bit error rate diversity of STT-MRAM cells caused by process variations, we propose a rate-adaptive polar coding scheme in conjunction with an adaptive decoding algorithm. Simulation results and the decoder complexity analysis show that the constructed polar codes outperform both the Bose–Chaudhuri–Hoquenghem codes and low-density parity-check codes with lower decoding complexity, thus demonstrating the great potential of polar codes for improving the reliability of emerging NVMs.

A spill data aware memory assignment technique for improving power consumption of multimedia memory systems

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation. This study describes a compiler optimization technique to overcome such disadvantages of a nonvolatile memory component in hybrid cache memories. A hybrid cache is proposed to overcome the disadvantages using a compiler. Specifically, to minimize the number of write operations for nonvolatile memory, we present a data replacement technique that considers the locations of the register spill data. Many portions of the memory accesses are yielded by the spill data of a register allocator in an optimizing compiler. Such spill data can be partially removed using a recalculation method. Thus, we implemented an optimization technique that rearranges the data placement with recalculation to minimize the write instructions on the nonvolatile memory. Our experimental results show that the proposed technique can reduce the average number of spill codes by 20%, and improves the energy consumption by 20.2% on average.

Dynamic Threshold Detection Based on Pearson Distance Detection

We consider the transmission and storage of encoded strings of symbols over a noisy channel, where dynamic threshold detection is proposed for achieving resilience against unknown scaling and offset of the received signal. We derive simple rules for dynamically estimating the unknown scale (gain) and offset. The estimates of the actual gain and offset so obtained are used to adjust the threshold levels or to re-scale the received signal within its regular range. Then, the re-scaled signal, brought into its standard range, can be forwarded to the final detection/decoding system, where optimum use can be made of the distance properties of the code by applying, for example, the Chase algorithm. A worked example of a spin-torque transfer magnetic random access memory with an application to an extended (72, 64) Hamming code is described, where the retrieved signal is perturbed by additive Gaussian noise and unknown gain or offset.

Ferromagnetic alloy material CoFeC with high thermal tolerance in MgO/CoFeC/Pt structure and comparable intrinsic damping factor with CoFeB

The thermal tolerance and perpendicular magnetic anisotropy (PMA) of ferromagnetic alloy Co40Fe40C20 in the structure MgO/CoFeC/Pt (or Ta) were investigated and compared with the commonly used CoFeB alloy. It is found that the PMA of CoFeC with , which is 59% higher than that of CoFeB, can be obtained after proper post-annealing treatment. Furthermore, CoFeC alloy provides better thermal tolerance to temperature of 400 °C than CoFeB. The studies on ferromagnetic resonance show that the intrinsic damping constant αin of Co40Fe40C20 alloy is 0.0047, which is similar to the reported value of 0.004 for Co40Fe40B20 alloy. The comprehensive comparisons indicate that CoFeC alloy is a promising candidate for the application of the integration of spin torque transfer magnetic random access memory with complementary metal-oxide semiconductor processes.

Perpendicular magnetic anisotropy in Mn2VIn (001) films: An ab initio study

First principles study of the magnetic anisotropy of Mn2VIn (001) films show perpendicular magnetic anisotropy (PMA), which increases as a function of the thickness of the film. Density functional theory (DFT) as implemented in the Vienna Ab initio simulation package (VASP) is employed here to perform a comprehensive theoretical investigation of the structural, electronic and magnetic properties of the Mn2VIn(001) films of varying thickness. Our calculations were performed on fully relaxed structures, with five to seventeen mono layers (ML). The degree of spin polarization is higher in the (001) Mn2VIn thin films as compared to the bulk in contrast to what is usually the case and as in Mn2VAl, which is isoelectronic to Mn2VIn as well as inCo2VIn (001) films studied for comparison. Tetragonal distortions are found in all the systems after relaxation. The distortion in the Mn2VIn system persists even for the 17ML thin film, resulting in PMA in the Mn2VIn system. This significant finding has potential to contribute to spin transfer torque (STT) and magnetic random access memory MRAM applications, as materials with PMA derived from volume magnetocrystalline anisotropy are being proposed as ideal magnetic electrodes.

Cascaded Channel Model, Analysis, and Hybrid Decoding for Spin-Torque Transfer Magnetic Random Access Memory

Spin-torque transfer magnetic random access memory (STT-MRAM) is a promising non-volatile memory technology widely considered to replace dynamic random access memory (DRAM). However, there still exist critical technical challenges to be tackled. For example, process variation and thermal fluctuation may lead to both write errors and read errors, severely affecting the reliability of the memory array. In this paper, we first propose a novel cascaded channel model for STT-MRAM that facilitates fast error rate simulations and more importantly the theoretical design and analysis of memory sensing and channel coding schemes. We analyze the raw bit error rate and probabilities of dominant error events, and derive the maximum likelihood decision criterion and the log-likelihood ratio of the cascaded channel. Based on these works, we further propose a two-stage hybrid decoding algorithm for extended Hamming codes for STT-MRAM. Simulation results demonstrate the effectiveness of the proposed hybrid decoding algorithm for improving the reliability of STT-MRAM in the presence of both write errors and read errors and supporting its potential applications, such as replacing DRAM.

Self‐adjusting sensing circuit without speed penalty for reliable STT‐MRAM

A self-adjusting sensing circuit spin-torque transfer magnetic random access memory (STT-MRAM) is proposed. STT-MRAM is considered to be the most promising candidate among the new emerging memories. However, read performance has emerged as a new bottleneck, because of its low tunnelling magneto-resistance ratio (TMR) and low read current. The proposed self-adjusting sensing circuit shows an improved sensing margin, overcoming the weaknesses of the STT-MRAM. The proposed circuit using Verilog-A model, a 65 nm complementary metal–oxide–semiconductor process also evaluated, and Monte Carlo analysis. The results of analysis show that the proposed circuit ensures a certain sensing margin, which is more than 200 mV in TMR 150% and about 50 mV in TMR 100%.

Analysis of self-heating of thermally assisted spin-transfer torque magnetic random access memory.

Thermal assistance has been shown to significantly reduce the required operation power for spin torque transfer magnetic random access memory (STT-MRAM). Proposed heating methods include modified material stack compositions that result in increased self-heating or external heat sources. In this work we analyze the self-heating process of a standard perpendicular magnetic anisotropy STT-MRAM device through numerical simulations in order to understand the relative contributions of Joule, thermoelectric Peltier and Thomson, and tunneling junction heating. A 2D rotationally symmetric numerical model is used to solve the coupled electro-thermal equations including thermoelectric effects and heat absorbed or released at the tunneling junction. We compare self-heating for different common passivation materials, positive and negative electrical current polarity, and different device thermal anchoring and boundaries resistance configurations. The variations considered are found to result in significant differences in maximum temperatures reached. Average increases of 3 K, 10 K, and 100 K for different passivation materials, positive and negative polarity, and different thermal anchoring configurations, respectively, are observed. The highest temperatures, up to 424 K, are obtained for silicon dioxide as the passivation material, positive polarity, and low thermal anchoring with thermal boundary resistance configurations. Interestingly it is also found that due to the tunneling heat, Peltier effect, device geometry, and numerous interfacial layers around the magnetic tunnel junction (MTJ), most of the heat is dissipated on the lower potential side of the magnetic junction. This asymmetry in heating, which has also been observed experimentally, is important as thermally assisted switching requires heating of the free layer specifically and this will be significantly different for the two polarity operations, set and reset.

Perpendicular Stt-Mram Scaling Challenges and Potential Solutions

Significant progresses have been made in recent years in perpendicular spin torque transfer magnetic random access memory (pSTT-MRAM) technology development by many companies or organizations. Commercialization of pSTT-MRAM is more real today than ever in the long history of MRAM technology development. We have recently reported fully functional pSTT-MRAM chips and macros with sub-5ns writing speed based on 90nm and 40nm node CMOS technologies [1,2]. These technologies can be potentially used to replace current embedded non-volatile memories such as embedded flash memories or SRAM and be applies to energy efficient applications such as internet of thing (IOT). In this presentation, we will review recent progresses and discuss STT-MRAM scaling challenges for product at 28nm technology node and beyond in terms of integration schemes as well as magnetic and electrical transport properties. We will also discuss the potential solutions that we see for these challenges.