Abstract

Thanks to its superior features of non-volatility, fast read/write speed, high endurance, and low power consumption, spin-torque transfer magnetic random access memory (STT-MRAM) has become a promising candidate for the next generation non-volatile memories (NVMs) and storage class memories (SCMs). However, it has been found that the write errors and read errors caused by thermal fluctuation and process variation severely degrade the reliability of STT-MRAM. Moreover, process imperfection also causes a diversity of the raw bit error rate (BER) among different dies of STT-MRAM. In this paper, we propose the design of novel rate-compatible protograph low-density parity-check (RCP-LDPC) codes to correct memory cell errors and mitigate the raw BER diversity of STT-MRAM. In particular, to deal with the asymmetric property of the STT-MRAM channel, we first apply an independent and identically distributed (i.i.d.) channel adapter to symmetrize the STT-MRAM channel. We then present a modified protograph extrinsic information transfer (P-EXIT) algorithm for the symmetrized STT-MRAM channel. We further propose a combined guideline, including the modified P-EXIT algorithm, the asymptotic weight enumerator (AWE) analysis, as well as the actual error rate performance, for designing protograph LDPC codes with short information word lengths for STT-MRAM. By further applying a code extension approach, we design novel RCP-LDPC codes that can work with a single encoder/decoder. Simulation results show that our proposed RCP-LDPC codes outperform the well-known rate-compatible AR4JA protograph codes as well as the fixed-rate quasi-cyclic (QC) LDPC codes in terms of both the error rate performance and the convergence speed over the STT-MRAM channel.

Highlights

  • In recent years, spin-torque transfer magnetic random access memory (STT-MRAM) has been considered as an ideal candidate for both the embedded non-volatile memory (NVM) and the storage class memory (SCM) [1]

  • SIMULATION RESULTS The simulations are based on the STT-MRAM channel model proposed by [3] without adding the i.i.d channel adapter, and a 3-bit capacity-maximizing quantizer used in the simulation work of [24]

  • We observe that the typical minimum distance ratio (TMDR) of all the codes are positive, which guarantees that all the codes to have linear minimum distance growth

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Summary

Introduction

Spin-torque transfer magnetic random access memory (STT-MRAM) has been considered as an ideal candidate for both the embedded non-volatile memory (NVM) and the storage class memory (SCM) [1]. Key advantages of STT-MRAM include high endurances, fast read/write speed, and low switching energy [2]. Read errors occur, leading to a detrimental effect on the reliability of data stored in the memory cells [3]. Due to the memory process imperfection, there exists a diversity of the raw bit error rate (BER) among different dies of STT-MRAM. It is critical to develop advanced error correction coding techniques to effectively correct memory cell errors and improve the reliability of STT-MRAM. To maintain the fast read/write speed of STT-MRAM for applications such as the SCMs, the error correction code (ECC) [4] adopted should have a short information

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