Transconductance Ratio Research Articles

Design and Implementation of Silicon-Doped Ferrogate Stacking JL-VTFET in MIC Sepic Convertor

This paper introduces a Ferro technique in the junctionless vertical tunnel field effect transistor in which the ferroelectric property in the [Formula: see text] is developed with the help of Silicon doping in it. The incorporation of the ferroelectric oxide stacking with [Formula: see text] results in low sub-threshold slope and high trans-conductance which is highly suitable for sensing of small voltage and converting it into strong drain current. The introduction of the high k-dielectric material with [Formula: see text] also leads to small lattice mismatch so that the losses can be reduced. The device shows ON current in the order of (2.62 × 10[Formula: see text]A/[Formula: see text]m) and the ratio of the ON to OFF drain current is noted as (of 2.031 × 10[Formula: see text]). Moreover, the device exhibits sub-threshold slope 35mV/dec and the ratio of trans-conductance to drain current (gm/[Formula: see text]) in the range of 150–350 V[Formula: see text]. Then the design structure is used to develop the circuit of multiple input converters (MIC) because the device shows high conversion rate (trans-conductance). For the converter, State-space analysis is used for the modeling of converter which was further followed with the design of converters’ energy storing apparatus with its voltage gain formulation. Interaction analysis is used to create a decentralized controller. The controllers’ robustness is tested using parametric uncertainty. A 175-watt experimental archetype with 36 volt and 24-volt sources is developed in the lab. The digital controller was implemented using the processor. The efficacy of controllers for regulating sources and loads has been verified. The controller’s strength is ensured by the satisfactory correlation between simulation and investigational results. For the result outcome one can validate Silicon Doped Ferro Gate Stacking JL-VTFET results for low power applications.

1 V Tunable High-Quality Universal Filter Using Multiple-Input Operational Transconductance Amplifiers.

This paper presents a new multiple-input single-output voltage-mode universal filter employing four multiple-input operational transconductance amplifiers (MI-OTAs) and three grounded capacitors suitable for low-voltage low-frequency applications. The quality factor (Q) of the filter functions can be tuned by both the capacitance ratio and the transconductance ratio. The multiple inputs of the OTA are realized using the bulk-driven multiple-input MOS transistor technique. The MI-OTA-based filter can also offer many filtering functions without additional circuitry requirements, such as an inverting amplifier to generate an inverted input signal. The proposed filter can simultaneously realize low-pass, high-pass, band-pass, band-stop, and all-pass responses, covering both non-inverting and inverting transfer functions in a single topology. The natural frequency and the quality factors of all the filtering functions can be controlled independently. The natural frequency can also be electronically controlled by tuning the transconductances of the OTAs. The proposed filter uses a 1 V supply voltage, consumes 120 μW of power for a 5 μA setting current, offers 40 dB of dynamic range and has a third intermodulation distortion of -43.6 dB. The performances of the proposed circuit were simulated using a 0.18 μm TSMC CMOS process in the Cadence Virtuoso System Design Platform to confirm the performance of the topology.

The Trade‐Off between Transconductance and Speed for Vertical Organic Electrochemical Transistors

AbstractThe high transconductance gm of organic electrochemical transistors (OECTs) has received widespread attention and made OECTs a valid candidate for wearable sensor systems. However, the large transconductance is often accompanied by large switching time constants, τ, making the transconductance an imperfect benchmark. For a fair assessment, the ratio of transconductance to switching time constant has to be considered instead of any single parameter in isolation. One approach put forward to optimize OECTs is a vertical design, in which the channel length can be scaled into the sub‐micrometer regime. Here, a new vertical device geometry is proposed, in which the active volume of the mixed conductor is confined to a small cavity between source and drain, yielding excellent performance and reproducibility. It is shown that this approach yields optimized ratios instead of maximized transconductance only. However, this scaling is effective only in a small range of device dimensions and requires careful optimization of the device to not be limited by parasitic effects such as excess volume of the mixed conductor or parasitic series resistances. Overall, the design considerations discussed here provide new guidelines to optimize OECTs, not only for high transconductance but for operation at high frequencies as well.

1 V Electronically Tunable Differential Difference Current Conveyors Using Multiple-Input Operational Transconductance Amplifiers.

This paper presents electronically tunable current conveyors using low-voltage, low-power, multiple-input operational transconductance amplifiers (MI-OTAs). The MI-OTA is realized using the multiple-input bulk-driven Metal Oxide Semiconductor transistor (MIBD-MOST) technique to achieve minimum power consumption. The MI-OTA also features high linearity, a wide input range, and a simple Complementary Metal Oxide Semiconductor (CMOS). Thus, high-performance electronically tunable current conveyors are obtained. With the MI-OTA-based current conveyor, both an electronically tunable differential difference current conveyor (EDDCC) and a second-generation electronically tunable current conveyor (ECCII) are available. Unlike the conventional differential difference current conveyor (DDCC) and second-generation current conveyor (CCII), the current gains of the EDDCC and ECCII can be controlled by adjusting the transconductance ratio of the current conveyors. The proposed EDDCC has been used to realize a voltage-to-current converter and current-mode universal filter to show the advantages of the current gain of the EDDCC. The proposed current conveyors and their applications are designed and simulated in the Cadence environment using 0.18 μm TSMC (Taiwan Semiconductor Manufacturing Company) CMOS technology. The proposed circuit uses ±0.5 V of power supply and consumes 90 μW of power. The simulation results are presented and confirm the functionality of the proposed circuit and the filter application. Furthermore, the experimental measurement of the EDDCC implemented in the form of a breadboard connection using a commercially available LM13700 device is presented.

Analytical drain current model development of twin gate TFET in subthreshold and super threshold regions

In this work, an analytical model for a twin gate Tunnel Field Effect Transistor's drain current operating in the subthreshold and superthreshold regions is proposed. Using this drain current model, the ratio of transconductance to drain current, a crucial metric for the integrated analog circuit design technique, has been retrieved. Due to the simplicity of this approach, it may be quickly implemented for any type of dual gate TFETs by adjusting a few parameters. Comparing the drain current calculated by this analytical model to the drain current simulated by the 2D-Sentaurus TCAD software demonstrates the Tunnel FET's authenticity. The proposed analytical method can be used to achieve the appropriate transconductance for operating Tunnel FETs in the gigahertz region with very low milliwatt power consumption.

A Broadband PVT-Insensitive All-nMOS Noise-Canceling Balun-LNA for Subgigahertz Wireless Communication Applications

A broadband process, voltage, and temperature (PVT)-insensitive noise-canceling balun-low-noise amplifier (LNA) was implemented in the 0.13-μm CMOS process for subgigahertz wireless communication applications. The proposed LNA is based on the traditional common-gate common-source (CGCS) balun-LNA topology, and it adopts the diode-connected loads to reduce the noise contribution originated from CGCS transistors and enhance the linearity due to post linearization. The auxiliary common-source (CS) amplifier with a diode-connected is added to reduce the overall noise figure (NF) of the LNA by sharing an input signal with CGCS transistors and applying its output signal to the diode-connected load of CS transistor. Because the voltage gain of the LNA is determined by the transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) ratio of the same types of nMOS transistors, its power gain (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> ) and NF are quite roust over PVT variations. In experiments, it showed S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> of 14 dB and NF of 4 dB with an input return loss (S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sub> ) of greater than 10 dB at 450 MHz. Concerning voltage variation (1.08-1.32 V) and temperature variation (-20 °C ~ +80 °C), the worst variations in S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> and NF were approximately 1.4 and 1.1 dB, respectively.

A 0.6-µW Chopper Amplifier Using a Noise-Efficient DC Servo Loop and Squeezed-Inverter Stage for Power-Efficient Biopotential Sensing.

To realize an ultra-low-power and low-noise instrumentation amplifier (IA) for neural and biopotential signal sensing, we investigate two design techniques. The first technique uses a noise-efficient DC servo loop (DSL), which has been shown to be a high noise contributor. The proposed approach offers several advantages: (i) both the electrode offset and the input offset are rejected, (ii) a large capacitor is not needed in the DSL, (iii) by removing the charge dividing effect, the input-referred noise (IRN) is reduced, (iv) the noise from the DSL is further reduced by the gain of the first stage and by the transconductance ratio, and (v) the proposed DSL allows interfacing with a squeezed-inverter (SQI) stage. The proposed technique reduces the noise from the DSL to 12.5% of the overall noise. The second technique is to optimize noise performance using an SQI stage. Because the SQI stage is biased at a saturation limit of 2VDSAT, the bias current can be increased to reduce noise while maintaining low power consumption. The challenge of handling the mismatch in the SQI stage is addressed using a shared common-mode feedback (CMFB) loop, which achieves a common-mode rejection ratio (CMRR) of 105 dB. Using the proposed technique, a capacitively-coupled chopper instrumentation amplifier (CCIA) was fabricated using a 0.18-µm CMOS process. The measured result of the CCIA shows a relatively low noise density of 88 nV/rtHz and an integrated noise of 1.5 µVrms. These results correspond to a favorable noise efficiency factor (NEF) of 5.9 and a power efficiency factor (PEF) of 11.4.

3D Stackable Synaptic Transistor for 3D Integrated Artificial Neural Networks.

Although they have attracted enormous attention in recent years, software-based and two-dimensional hardware-based artificial neural networks (ANNs) may consume a great deal of power. Because there will be numerous data transmissions through a long interconnection for learning, power consumption in the interconnect will be an inevitable problem for low-power computing. Therefore, we suggest and report 3D stackable synaptic transistors for 3D ANNs, which would be the strongest candidate in future computing systems by minimizing power consumption in the interconnection. To overcome the problems of enormous power consumption, it might be necessary to introduce a 3D stackable ANN platform. With this structure, short vertical interconnection can be realized between the top and bottom devices, and the integration density can be significantly increased for integrating numerous neuromorphic devices. In this paper, we suggest and show the feasibility of monolithic 3D integration of synaptic devices using the channel layer transfer method through a wafer bonding technique. Using a low-temperature processible III-V and composite oxide (Al2O3/HfO2/Al2O3)-based weight storage layer, we successfully demonstrated synaptic transistors showing good linearity (αp/αd = 1.8/0.5), a high transconductance ratio (6300), and very good stability. High learning accuracy of 97% was obtained in the training of 1 million MNIST images based on the device characteristics.

Graphene-based field effect transistor with ion-gel film gate

Graphene is a kind of two-dimensional material with high light transmittance, high mechanical properties and high carrier mobility. The energy band of graphene can be turned by doping and electric field. Researches on the application of graphene to electronic devices focused on field effect transistors. For improving the performance, one generally improves the fabrication process and device structure, but many researchers chose to change the material or structure of dielectric layer. Ion-gel is a kind of mixture of organic polymer mesh structure with good thermal stability and high dielectric value, prepared by macromolecule organic polymer and ionic salt electrolyte material. With the effect of electric field, cations and anions in ion-gel diffuse to form a double charge layer distribution with a charge layer on the surface of material. This capacitance characteristic is similar to that of traditional capacitor. In this paper, ion-gel (PVDF-[EMIM]TF2N) film is used as a dielectric layer material to prepare the bottom-gate graphene-based field effect transistor (GFET), which is compared with the GFET with SiO&lt;sub&gt;2&lt;/sub&gt; bottom-gate, according to electrical characteristic curves. The effect of the ion-gel film on the transconductance, switching ratio and Dirac voltage of the GFET are analyzed. The effect of the vacuum environment and temperature on the GFET performance with ion-gel film gate are also investigated. The results show that in the room-temperature environment, the switching ratio and transconductance of the ion-gel film gate GFET device increase to 6.95 and 3.68 × 10&lt;sup&gt;–2&lt;/sup&gt; mS, respectively, compared with those of the SiO&lt;sub&gt;2&lt;/sub&gt; gate GFET, while the Dirac voltage decreases to 1.3 V. The increase in transconductance and switching ratio of ion-gel film gate GFETs are mainly due to the high capacitance of ion-gel film compared with those of conventional SiO&lt;sub&gt;2&lt;/sub&gt; gate dielectrics. There will be more carriers inside the graphene while in the carrier accumulation region of GFET transfer characteristic curve, which makes graphene more conductive. The Dirac voltage of ion-gel film gate GFET can be reduced to 0.4 V in the vacuum environment; as the temperature increases, the transconductance of GFET can increase up to 6.11×10&lt;sup&gt;–2&lt;/sup&gt; mS. The results indicate that the ion-gel film-based graphene field effect transistor shows good electrical properties in serving as high dielectric constant organic dielectric materials.

A 37- $\mu \text{W}$ , Binary-Weighted PGA Based on a Novel Degeneration Transistor-Ladder

A programmable-gain amplifier with low power consumption is presented. The programmable gain function is achieved by varying the effective transconductance ratios of input and output stages, which is realized through innovative binary-weighted and triode-region transistor ladder. The proposed technique effectively overcomes the problems associated with the implementation of resistors ladder in these types of structures. The operational principle of this unique structure is discussed, its most important formulas are derived, and its outstanding performance is verified by post-layout simulations in TSMC 0.18- $\mu$ m N-well CMOS fabrication process. Owing to its unique construction, the proposed circuit combines the ever interesting constant bandwidth, linear-in-decibel, and fine-step programmable gain range merits all in a simple and low power structure. The core of proposed structure draws only 36.5 $\mu$ W from 1.8-V power supply. The circuit is capable of delivering a wide programmable range of about 37 dB and operating at frequencies up to 20 MHz. To approve the robustness of the structure, full process, voltage, and temperature variation analysis of the circuit is investigated through corner case and Monte Carlo simulations. Monte Carlo simulations show standard deviation values of less than 0.21 $\mu$ W and 0.5 dB in power consumption and voltage gain, respectively. These results indicate that the proposed structure would lend itself well for use in applications that demand high ratios of frequency over power consumption.

Unconditionally Stable Non-Foster Element Using Active Transversal-Filter-Based Negative Group Delay Circuit

This letter introduces a novel type of non-Foster element using a microwave transversal-filter-based negative group delay (NGD) circuit that can exhibit unconditional stability. The proposed device is realized by a distributed amplifier, in which the NGD response is synthesized by adjusting the ratio of transconductance of transistors in each stage. On top of this, by properly amending the in-band magnitude and phase characteristics, the NGD circuit can realize non-Foster elements within the operating band. Furthermore, thanks to the distributed topology, the proposed network has very good input and output matching characteristics. As proof-of-concept, a prototype of the proposed non-Foster element is built to validate the proposed scheme. The experimental results show that the proposed circuit can realize a unilateral non-Foster element composed of a −1 pF shunt capacitor and a −1.25 nH series inductor.

Improved Switching Characteristics Obtained by Using High-k Dielectric Layers in 4H-SiC IGBT: Physics-Based Simulation

Silicon Carbide (SiC) based MOS devices are one of the promising devices for high temperature, high switching frequency and high power applications. In this paper, the static and dynamic characteristics of an asymmetric trench gate SiC IGBT with high-k dielectrics- HfO2 and ZrO2 are investigated. SiC IGBT with HfO2 and ZrO2 exhibited higher forward transconductance ratio and lower threshold voltage compared to conventionally used SiO2. In addition, lower switching power losses have been observed in the case of high-k dielectrics due to reduced tail current duration.

Transistor Sizing for Bias-Stress Instability Compensation in Inkjet-Printed Organic Complementary Inverters

We present a design approach to maintain a stable voltage transfer characteristic in inkjet-printed complementary organic thin-film transistor logic inverters via device sizing. We use transistor-level design to help achieve stable logic gates, so that performance is less dependent on processing conditions and materials properties that are difficult to control for inkjet-printed electronics. Despite bias-stress instability in the individual p- and n-type transistors, a stable inverter switching threshold is achieved by equalizing the magnitudes of positive and negative threshold voltage shifts. Following a typical sizing approach for complementary logic, a p- to n-transistor transconductance ratio of 0.25 places the inverter switching threshold near the center of the voltage supply range. However, we show through calculations and measured results that a ratio closer to 2.5 prevents rapid shift of the switching threshold, which is equally important for reliable inverter operation. Furthermore, we provide a design approach to size digital logic gates with arbitrary probability of output states.

Development of a simulator for analyzing some performance parameters of nanoscale strained silicon MOSFET-based CMOS inverters

Owing to the persisting technological importance of Strained-Si (S–Si) metal-oxide-semiconductor field-effect transistors (MOSFETs) and the hurdles offered by source (S) and drain (D) series resistances in the nanometer regime, a simulator has been developed for evaluating the voltage transfer characteristics (VTC) and analyzing some performance parameters of such devices-based CMOS inverters. The algorithms used for framing the simulator are based on analytical equations which can accurately estimate the noise margin (NM), dynamic current, and so on. The effects of strain on the circuit performance have also been investigated, with emphasis on the variations of drain current dependent transconductance ratio. A scope of using high-k dielectric materials along with strain is also explored. The algorithms proposed in this work are not only restricted to strained-Si MOSFETs but can also be applied to any novel device structure and complex digital logics, presented as case studies.

Device Delay in GaN Transistors Under High Drain Bias Conditions

This letter studies the drain delay caused by the extension of the effective gate length in high-frequency GaN high electron mobility transistors. It is shown that the drain delay is mainly reflected in the gate-to-source capacitance (Cgs) of the device. The ratio of Cgs and transconductance (gm) is then used to accurately extract the drain delay and the result is compared with other extraction methods reported in the literature. Finally, we will use this new extraction technique to explain why short channel GaN devices show higher drain delay than longer channel transistors.

Influence of the Contact Thickness on Electrical Performance of Staggered and Planer &lt;i&gt;p&lt;/i&gt;-Channel Organic Field Effect Transistors

The influence of contact thickness on electrical performance of bottom gate Organic Field Effect Transistor (BG-OFET) with staggered and planer structures is studied in this paper. Two dimensional device simulation is performed with identical dimensions for both devices which show a good agreement between simulated and measured results. Contact thickness is varied from 0nm to 20nm for planer and staggered structures. The electrical characteristics are strongly affected by the contact thickness variation. With increasing contact thickness, the threshold voltage shifts from negative to positive. The simulation results indicate that saturation current value of staggered structure is higher than that of planer. Although the current does not increase in staggered structure due to its increasing contact thickness, while the current in planer structure increases up to three times. However, current in planer is still below the current in staggered structure. The extracted field effect mobility and current on-off ratio at 20nm electrode thickness for staggered structure is 0.67 cm2/V.s and 108, respectively. It has been observed that the field effect mobility, threshold voltage, sub-threshold slope, transconductance and current on-off ratio can be modified by varying contact thickness. Analysis of the results clearly demonstrates the significance of controlling the contact thickness in planer and staggered OFETs. It even offers a way to control OFETs parameters.

Electronically Tunable Single-Input Five-Output Voltage-Mode Universal Filter Using VDTAs and Grounded Passive Elements

This paper presents a possible usage of the voltage differencing transconductance amplifier (VDTA) for the design of an electronically tunable single-input five-output voltage-mode universal filter. The presented filter is constructed using two VDTAs, two capacitors and two resistors that are all grounded. The circuit simultaneously realizes lowpass (LP), bandpass (BP), highpass (HP), bandstop (BS) and allpass (AP) filtering responses, without changing the circuit topology. The circuit is capable of providing an independent electronic control of the natural angular frequency (ω0) and the quality factor (Q) through the transconductance gains of the VDTAs. By simply adjusting the transconductance ratio, a high-Q filter can also be obtained. Because of the high-input impedance of the circuit, it is advantageous for cascade connection. To support the theoretical analysis, the properties of the designed filter have been verified by PSPICE simulation results.

Experimental Comparative Study Between the Wave Layout Style and its Conventional Counterpart for Implementation of Analog Integrated Circuits

This paper performs an experimental comparative study between the Wave layout style (“S” shape gate geometry) and the Conventional (rectangular gate geometry) counterpart in order to verify and quantify the benefits that Wave structure can bring to improve the performance of devices in analog circuit, specially in trasconductance the ratio of transconductance between drain current as a function of the ratio of the drain current normalized by the geometric factor and frequency response (voltage gain and unit voltage gain frequency). By working with Wave structure instead of conventional counterpart, it can improve the device performance in terms of drain current in the triode and saturation regions, consequently better results in the transconductance and unit voltage gain frequency gains.

Designing bulk-driven MOSFETs for ultra-low-voltage analogue applications

This paper presents the design of an n-type bulk-driven MOSFET which is intended to facilitate the scaling of analogue circuitry down to 0.7 V, the minimum supply voltage predicted for the end of bulk CMOS. The bulk-driven MOSFET design will be carried out in two parts using the design rules of a standard 90 nm bulk CMOS technology. First, the impact of gate oxide scaling will be investigated to see how the bulk transconductance behaves as the oxide thickness is varied. Results will indicate that the oxide scaling requirements of a MOSFET can be relaxed by 0.4 nm when the bulk is used as the input terminal rather than the gate. Second, by taking advantage of a larger oxide thickness, it will be shown that a delta-doped profile is capable of improving the intrinsic gain and cut-off frequency of a bulk-driven MOSFET by as much as 429% and 71%, respectively, when compared to a uniformly doped bulk-driven device consistent with the specifications of a 90 nm bulk CMOS process. Overall, the delta-doped bulk-driven MOSFET will exhibit a long-channel bulk-to-gate transconductance ratio equal to 0.51, compared to 0.27 in the uniformly doped device (the gate transconductance was the same in both devices). The new delta-doped design will also increase the bulk-driven-to-gate-driven cut-off frequency ratio to 0.095–0.492 for channel lengths ranging from 80–800 nm, which is a 16–34% improvement over the uniformly doped case. When used in a differential amplifier circuit, the delta-doped bulk-driven MOSFET was found to have a dc voltage gain 185% higher than that of a similar amplifier utilizing uniformly doped devices.

A Subthreshold Low Phase Noise CMOS LC VCO for Ultra Low Power Applications

A subthreshold low power, low phase-noise voltage controlled oscillator (VCO) is demonstrated in a commercial 0.18 mum CMOS process. In subthreshold regime, MOS drain current is dominated by diffusion mechanism resulting in a high ratio of transconductance to drain current and suppressed phase noise. Therefore, low power and low phase noise characteristics are achieved without using nonconventional high passive components. The VCO measures a phase noise of -106 dBc/Hz at 400 kHz offset from 2.63 GHz oscillation frequency with 0.43 mW power dissipation drawn from 0.45 V power supply. Figures of merit for this VCO (power-frequency-normalized of 12 dB and power frequency-tuning-normalized of -10 dB) are among the best reported for CMOS oscillators.