A 37- $\mu \text{W}$ , Binary-Weighted PGA Based on a Novel Degeneration Transistor-Ladder

Abstract

A programmable-gain amplifier with low power consumption is presented. The programmable gain function is achieved by varying the effective transconductance ratios of input and output stages, which is realized through innovative binary-weighted and triode-region transistor ladder. The proposed technique effectively overcomes the problems associated with the implementation of resistors ladder in these types of structures. The operational principle of this unique structure is discussed, its most important formulas are derived, and its outstanding performance is verified by post-layout simulations in TSMC 0.18- $\mu$ m N-well CMOS fabrication process. Owing to its unique construction, the proposed circuit combines the ever interesting constant bandwidth, linear-in-decibel, and fine-step programmable gain range merits all in a simple and low power structure. The core of proposed structure draws only 36.5 $\mu$ W from 1.8-V power supply. The circuit is capable of delivering a wide programmable range of about 37 dB and operating at frequencies up to 20 MHz. To approve the robustness of the structure, full process, voltage, and temperature variation analysis of the circuit is investigated through corner case and Monte Carlo simulations. Monte Carlo simulations show standard deviation values of less than 0.21 $\mu$ W and 0.5 dB in power consumption and voltage gain, respectively. These results indicate that the proposed structure would lend itself well for use in applications that demand high ratios of frequency over power consumption.