Device Delay in GaN Transistors Under High Drain Bias Conditions

Abstract

This letter studies the drain delay caused by the extension of the effective gate length in high-frequency GaN high electron mobility transistors. It is shown that the drain delay is mainly reflected in the gate-to-source capacitance (Cgs) of the device. The ratio of Cgs and transconductance (gm) is then used to accurately extract the drain delay and the result is compared with other extraction methods reported in the literature. Finally, we will use this new extraction technique to explain why short channel GaN devices show higher drain delay than longer channel transistors.