Traditional SRAM Research Articles

Simulation based analysis of HK-Ge-Step-FinFET and its usage as inverter & SRAM

This paper deals with comparative simulation of High-k dielectrics -Germanium Step FinFET (HK-Ge-Step-FinFET) device with reference Step FinFET. For the first time we have investigated the impact of various dimensional parameters like oxide thickness tox, gate length Lg, drain bias voltage Vds on the performance of Proposed and Reference FinFET devices. These FinFET structures have been designed and simulated in Sentaurus TCAD and Cadence Virtuoso. The electrical parameters such as current ratio ION/IOFF, Sub-threshold Swing SS , Drain Induced Barrier Lowering (DIBL), threshold voltage Vth, gate capacitance, intrinsic delay and transconductance are extracted at 10 nm gate length. It is noticed that there is a significant improvement of 28 times and 23 times in ION for proposed device over reference FINFET at Vds = 1 V and Vds = 0.5 V respectively, improvement in ION/IOFF ratio from 8.05 × 108 to 6.65 × 1010, SS of 63.21 mV/decade to 61.5 mV/decade and excellent threshold voltage of 0.18 V in proposed FinFET. The characteristics of the proposed SRAM cell including, static noise margin (SNM), read/write delay, and subthreshold leakage power, are compared with the conventional 6 T SRAM cells. It is reported that the FinFET SRAM cell has RSNM, HSNM, and WNM of 285 mV, 360 mV, and 302 mV, respectively, at Vds = 1 V. Furthermore, the suggested device-based SRAM cell outperforms traditional SRAM cells at 1.0 V in terms of read noise margin, hold noise margin, and write noise margin, as well as leakage power. Thus, it may prove to be a viable option for lowering leakage components, making it effective for low-power and high-performance inverter and SRAM cell design in the nanoscale regime.

The Performance of SRAM Cell Topologies with 6 T, 7 T, 8 TAnd 9 T Technologies at 45 Nm Technology node

Numerous SRAM cell architectures employing 45nm technology were simulated in the Tanner tool used for this inquiry. In every arrangement, variables like read latency, write delay, power read, power write consumption, read static noise margin (RSNM), and write static noise margin (WSNM) were examined. Of all the designs, the 7T SRAM cell stands out for having the lowest power read utilization. Nevertheless, compared to the 6T SRAM cell, the 8T SRAM cell displayed a 44.15% reduction in power write power.The 9T SRAM cell exhibited the lowest write latency of all the cells tested.Among all the simulated devices, the traditional 6T SRAM cell also showed the highestRSNM value. There was discovered the 8T SRAM cell's WSNM.

Design and Analysis of XNOR-SRAM for In-Memory Computing

Abstract: The use of in-memory computing is a promising strategy with the potential to circumvent the von Neumann bottleneck and improve the overall performance of contemporary computer systems. In this study, the design and analysis of an innovative XNOR-SRAM cell for use in in-memory computing applications is presented. The performance of the suggested cell is assessed using crucial parameters such as cell ratio (CR), pull-up ratio (PR), static noise margin (SNM), write margin (WM), and read margin(RM)MA. Simulation and optimization of the proposed cell are carried out with the assistance of LTSPICE and the HSPICE tool . According to the findings, the XNOR-SRAM cell has greater performance when compared to the traditional 6T SRAM cell. This paves the way for the XNOR-SRAM cell to become a viable choice for in-memory computing.

HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache Hierarchy

In this article, we propose a “full-stack” solution to designing high-apacity and low-latency on-chip cache hierarchies by starting at the circuit level of the hardware design stack. We propose a novel half V DD precharge 2T Gain Cell (GC) design for the cache hierarchy. The GC has several desirable characteristics, including ~50% higher storage density and ~50% lower dynamic energy as compared to the traditional 6T SRAM, even after accounting for peripheral circuit overheads. We also demonstrate data retention time of 350 us (~17.5× of eDRAM) at 28 nm technology with V DD = 0.9V and temperature = 27°C that, combined with optimizations like staggered refresh, makes it an ideal candidate to architect all levels of on-chip caches. We show that compared to 6T SRAM, for a given area budget, GC-based caches, on average, provide 30% and 36% increase in IPC for single- and multi-programmed workloads, respectively, on contemporary workloads, including SPEC CPU 2017. We also observe dynamic energy savings of 42% and 34% for single- and multi-programmed workloads, respectively. Finally, in a quest to utilize the best of all worlds, we combine GC with STT-RAM to create hybrid hierarchies. We show that a hybrid hierarchy with GC caches at L1 and L2 and an LLC split between GC and STT-RAM is able to provide a 46% benefit in energy-delay product (EDP) as compared to an all-SRAM design, and 13% as compared to an all-GC cache hierarchy, averaged across multi-programmed workloads.

An energy-efficient cache replacement policy for ultra-dense racetrack memory

Racetrack memory (RTM) based caches provide improved energy and area efficiencies compared to traditional SRAM caches via multi-bit storage capability. The RTM cell arranges multiple bits in a magnetic nanowire track and is equipped with a shared port to access the data. Accessing a bit necessitates to shift the bit under the port. Since the serial access nature of the RTM cell induces energy penalty, it is crucial to reduce the number of shifts. To do so, we have devised an energy-efficient cache replacement policy that first calculates the shift cost of a group of rarely reused cache lines in a cache set. After that, it chooses a victim cache line from that group that incurs minimum shift cost. Employing 1MB RTM cache for single-programmed workloads, the proposed policy outperforms the state-of-the-art by 23.2% and 48.8% in terms of energy consumption and shift cost respectively. For multi-programmed workloads, the energy saving and shift improvement translates to 22.8% and 39.8% respectively using 4MB RTM shared cache.

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

Enhancing Energy Efficiency of Sram through Optimization of Sram Array Structures

Reliability is a major concern in the microprocessor industry. In terms of power consumption, SRAM plays a key role in improving processing performance. Improving SRAM efficiency requires changes to the array structure. A general method in which the SRAM array has more rows than columns.The above techniques are proposed to improve efficiency by 10% for 8kbit and 40% for 64kbit at the same SRAM byte density and supply voltage. Implement suggested deep submicron technology for better reliability. Many proposed designs focus on low power consumption, often with reduced response times.As the technology scales, the power consumption of on-chain system devices with gate leakage, subthreshold current, and tunneling increases significantly. Small SRAM capabilities are important.This task demonstrates the potential of using larger SRAM array structures to achieve better SRAM energy efficiency, especially when the number of rows is less than the number of low-power columns. Compared to traditional 8T SRAM, the proposed 10T cell uses less power, has a different temperature and better performance.

A novel low power hybrid cache using GC-EDRAM cells

In a typical embedded CPU, large on-chip storage is critical to meet high performance requirements. However, the fast increasing size of the on-chip storage based on traditional SRAM cells makes the area cost and energy consumption unsustainable for future embedded applications. Replacing SRAM with DRAM on the CPU’s chip is generally considered not worthwhile because DRAM is not compatible with the common CMOS logic and requires additional processing steps beyond what is required for CMOS. However a special DRAM technology, Gain-Cell embedded-DRAM (GC-eDRAM) [1–3] is logic compatible and retains some of the good properties of DRAM (small and low power). In this paper we evaluate the performance of a novel hybrid cache memory where the data array, generally populated with SRAM cells, is replaced with GC-eDRAM cells while the tag array continues to use SRAM cells. Our evaluation of this cache demonstrates that, compared to the conventional SRAM-based designs, our novel architecture exhibits comparable performance with less energy consumption and smaller silicon area, enabling the sustainable on-chip storage scaling for future embedded CPUs.

A Novel Darlington-Based 8T CNTFET SRAM Cell for Low Power Applications

The design of low power memory cells is the dream of engineers in memory design. A Darlington-based 8T CNTFET SRAM cell is suggested in this paper. It is called the proposed P_CNTFET Darlington 8T SRAM Cell. Compared with that of the traditional 6T and 8T CNTFET SRAM cells, the power and noise performances of the proposed SRAM cell are comparable. Compared to the traditional SRAM cells, the write, hold, read and dynamic power consumption of the proposed cell is much lower. The CNTFET parameters are optimized to boost the noise margin performance of the suggested bit cell. For optimized parameters, the power consumption and SNM of the proposed cell are compared with conventional cells. In contrast to the conventional cells, the HSNM and WSNM of the proposed cell are improved by 6.25% and 66.6%. The proposed cell’s RSNM is 38% greater than the traditional 6T SRAM cell. The proposed cell’s RSNM is 3.33% less than the traditional 8T SRAM cell. MOSFET is also used to implement the proposed SRAM cell and its noise margin and power performance are compared with traditional MOSFET-based SRAM cells. As with the conventional cells, the MOSFET-based implementation of the proposed cell power and SNM performance is also very good. The simulation is done with the HSPICE simulation tool using the Stanford University 32[Formula: see text]nm CNTFET model.

Performance Evaluation of Negative-Capacitance Fin-Type Field Effect Transistor-Based Static Random-Access Memory with Mixed-Mode Simulation

Electrical characteristics of fin-type field-effect transistor with negative capacitance effect (NCFinFET) are investigated coupled with the Landau-Khalatnikov equation for ferroelectric materials in this study. Moreover, Technology Computer Aided Design (TCAD) mixed-mode simulation is carried out to evaluate and compare the performance of NCFinFET-based static random access memory cell (NC-SRAM) with a traditional FinFETbased SRAM one. It is shown NC-SRAM has higher static noise margin (SNM) and better anti-interference capability than conventional SRAM with the same supply voltage. The static read, hold, and write noise margins (RSNM, HSNM, and WSNM, respectively) for NC-SRAM increased by 10%, 30%, and 15%, respectively, and the access disturb stability improved by 80%. Simulation results also reveal that the read stability increases with increasing ferroelectric layer thickness, while the write stability exhibits a non-monotonic trend with ferroelectric layer thickness for NC-SRAM.

Highly Stable Low Power Radiation Hardened Memory-by-Design SRAM for Space Applications

In space, due to high energy particles, which cause single event upsets (SEUs), the traditional 6T SRAM cell becomes more susceptible to soft-error. In order to address this, a radiation hardened memory-by-design 10T (RHMD10T) SRAM cell is proposed in this brief. The relative strength of RHMD10T is estimated by comparing it with other contemporary cells such as QUATRO10T, QUCCE10T, QUATRO12T, QUCCE12T, NS10T and PS10T over various major design metrics. RHMD10T exhibits 1.09×/ 1.16×/ 1.26× shorter read delay than QUCCE10T/ QUATRO10T/ NS10T. RHMD10T has the highest read stability and can tolerate the highest amount of critical charge than all other comparison cells. RHMD10T consumes the lowest hold power than all other comparison cells, except NS10T. In addition, RHMD10T is the least susceptible to SEU, except QUCCE12T. All these aforementioned improvements of RHMD10T are obtained at a cost of slightly longer write delay and lower write ability.

Efficient Cache Resizing policy for DRAM-based LLCs in ChipMultiprocessors

In today’s ChipMultiprocessors (CMPs), multiple cores share the common Last Level Cache (LLC), divided into multiple banks. As the data requirement is increasing the demand for larger LLC sizes is also increasing. The traditional SRAM technology is not area efficient to design such larger LLCs as demanded by the modern CMPs. From the last few years, DRAM technologies have been used to propose LLC. DRAM technology has almost 8 times density over the SRAM and hence larger cache size can be designed. Though DRAM is already considered as an alternative to design low cost, area-efficient larger size LLC, it must be used efficiently to get the benefits. Due to its overheads like access latency and refresh operations efficient techniques must be used to get better performance from DRAM LLC. In the existing works, it has been observed that though the larger LLC is required for the current as well as future data-intensive applications, the entire LLC may not be required while executing other applications. In such situations, some banks can be almost idle during a particular period of execution. These idle banks can be powered-off and restart later whenever required. The mechanism is called Cache Resizing as it resizes the cache (LLC) according to the current requirements. Cache resizing techniques are already proposed for SRAM based LLCs but due to the larger size of DRAM LLC, the same mechanisms cannot be used for DRAM LLCs. In this paper, we have proposed an efficient cache resizing policy for large sized LLC, especially for DRAM-based LLCs. We call our proposed cache resizing technique as Efficient Cache Resizing (ECR) which is implemented on top of a 3D Tiled CMP. Experimental analysis shows that ECR can reduce up to 44% more energy consumption as compared to the existing technique.

Efficient Acceleration of Stencil Applications through In-Memory Computing.

The traditional computer architectures severely suffer from the bottleneck between the processing elements and memory that is the biggest barrier in front of their scalability. Nevertheless, the amount of data that applications need to process is increasing rapidly, especially after the era of big data and artificial intelligence. This fact forces new constraints in computer architecture design towards more data-centric principles. Therefore, new paradigms such as in-memory and near-memory processors have begun to emerge to counteract the memory bottleneck by bringing memory closer to computation or integrating them. Associative processors are a promising candidate for in-memory computation, which combines the processor and memory in the same location to alleviate the memory bottleneck. One of the applications that need iterative processing of a huge amount of data is stencil codes. Considering this feature, associative processors can provide a paramount advantage for stencil codes. For demonstration, two in-memory associative processor architectures for 2D stencil codes are proposed, implemented by both emerging memristor and traditional SRAM technologies. The proposed architecture achieves a promising efficiency for a variety of stencil applications and thus proves its applicability for scientific stencil computing.

A Novel 8T Cell-Based Subthreshold Static RAM for Ultra-Low Power Platform Applications

Subthreshold SRAMs profit various energy-constrained applications. The traditional 6T SRAMs exhibit poor cell stability with voltage scaling. To this end, several 8T to 16T cell designs have been reported to improve the stability. However, they either suffer one of disturbances or consume large bit-area overhead. Furthermore, some cell options have a limited write-ability. This paper presents a novel 8T static RAM for reliable subthreshold operation. The cell employs a fully differential scheme and features cross-point access. An adaptive cell bias for each operating mode eliminates the read disturbance and enlarges the write-ability as well as the half-select stability in a cost-effective small bit-area. The bit-cell also can support efficient bit-interleaving. To verify the SRAM technique, a 32-kbit macro incorporating the proposed cell was implemented with an industrial 180 nm low-power CMOS process. At 0.4 V and room temperature, the proposed cell achieves 3.6× better write-ability and 2.6× higher dummy-read stability compared with the commercialized 8T cell. The 32-kbit SRAM successfully operates down to 0.21 V (~0.27 V lower than transistor threshold voltage). At its lowest operating voltage, the sleep-mode leakage power of entire SRAM is 7.75 nW. Many design results indicate that the proposed SRAM design, which is applicable to an aggressively-scaled process, might be quite useful in realizing cost-effective robust ultra-low voltage SRAMs.

Gain-Cell Embedded DRAM-Based Physical Unclonable Function

Physical unclonable functions (PUFs) are important elements in hardware-secured systems as they can generate chip identification and encryption keys based on random variables of the manufacturing process. Many previously proposed PUF implementations are based on SRAM memory technology, since it is embedded on-chip and can provide such randomness. Logic-compatible gain-cell embedded DRAM (GC-eDRAM) is a low density, low leakage alternative to traditional SRAM for the implementation of embedded memories that also provide an additional mechanism of randomness by means of the data retention time (DRT) of the bitcells. In this paper, we propose using the DRT of GC-eDRAM arrays as a source for the generation of an intrinsic PUF. We provide an in-depth analysis of the leakage mechanism of GC-eDRAM and demonstrate how it determines the DRT of the bitcell. Based on this analysis, we provide an authentication methodology for enrollment and evaluation of a GC-eDRAM based PUF. Monte Carlo simulations on a 1 kbit array in 28 nm technology demonstrate the high uniqueness of the PUF with an inter-die Hamming distance of 50%. Reliability analysis under a wide voltage range (0.4 V–1 V) and temperature (0 (0 °C−85 °C) variation demonstrate the statistical robustness of the proposed PUF less than a 6% error-rate.

Write energy reduction of STT-MRAM based multi-core cache hierarchies

ABSTRACTSpin transfer torque magnetoresistive random access memory (STT-MRAM) is a favourable memory technology for on-chip cache hierarchies in multi-core processors. STT-MRAM offers scalability, near zero leakage power, non-volatility, high density, etc., which makes it a good candidate for on-chip cache memory. However, write access latency and write energy consumption in STT-MRAM is relatively high as compared to traditional SRAM which results in high dynamic power consumption as well as performance degradation. In this paper, we have analysed the impact of write buffers on the STT-MRAM-based cache hierarchy. We have tried to optimise the write operations in L1 and L2 cache by exploiting the small static random access memory-based write buffers. The write operations are redirected to the write buffer and not to the L1 cache which mitigates the energy and performance overhead induced by STT-MRAM write operations. Experiment results on PARSEC benchmark show that STT-MRAM-based cache hierarchy improves 90% static energy. But due to large write energy and latency, the dynamic energy of STT-MRAM-based cache is 12.53% higher than the SRAM-based cache hierarchy. The normalised execution time is improved by 19.33% as compared to SRAM-based cache hierarchy.

Design of high performance, low power sub thresholds ram using source coupled logic for implantable applications.

Low power circuits functioning in sub threshold were proposed in earlier seventies. Recently, growing with the need of low power consumption, the low power circuits have became more attractive. However, the act of sub threshold design logics has become sensitive to the supply voltage & process variations like temperature and so on. In sub threshold region of operations the supply voltage (Vgs) is less than the threshold (Vth).This leads to less power dissipation in over all circuit, but drastically increment in propagation delay. The major intention of the paper is to offer new low power & less delay digital circuits. SRAM is the major power drawing element and dissipation is about 40% in total power. The primary objective is to design of sub threshold SRAM design, Functionality and performance is estimated from the power and delay.The second objective is to offer novel Source coupled logic based SRAM (ST-SC SRA) M & Operating these design under sub threshold operating region. Performance is analyzed through power and delay. Finally comparing the traditional sub threshold SRAM with source coupled based SRAM in power and delay on par with the performance. Discussing some of the applications, where there is a requirement of less power and delay.

Design & Analysis of Single Bit Sub-Threshold Sram Using Dtmos with Traditional Sram Design under 32nm Design

Design & Analysis of Single Bit Sub-Threshold Sram Using Dtmos with Traditional Sram Design under 32nm Design

Word- and Partition-Level Write Variation Reduction for Improving Non-Volatile Cache Lifetime

Non-volatile memory technologies are among the most promising technologies for implementing the main memories and caches in future microprocessors and replacing the traditional DRAM and SRAM technologies. However, one of the most challenging design issues of the non-volatile memory technologies is the limited write. In this article, we first propose to exploit the narrow-width values to improve the lifetime of non-volatile last-level caches with word-level write variation reduction. Leading zeros masking scheme is proposed to reduce the write stress to the upper half of the narrow-width data. To balance the write variations between the upper half and the lower half of the narrow-width data, two swapping schemes, the swap on write (SW) and swap on replacement (SRepl), are proposed. Two existing optimization schemes, the multiple dirty bit (MDB) and read before write (RBW), are adopted with our word-level swapping design. To further reduce the write variation on the partition level, we propose to exploit the cache partitioning design to improve the lifetime. Based on the observation that different applications demonstrate different cache access (write) behaviors, we propose to partition the last-level cache for different applications and balance the write variations by partition swapping. Both software-based and hardware-based partitioning and swapping schemes are proposed and evaluated for different situations. Our experimental results show that both our word- and partition-level designs can improve the lifetime of the non-volatile caches effectively with low performance and energy overheads.

Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing

This paper proposes a standard-cell based memory (SCM) as an alternative to a traditional on-chip SRAM for near-threshold voltage computing. It focuses on area- and energy-efficiency using minimum height standard-cells. Unlike conventional SCMs, the proposed SCM has standard-cells with a minimum possible cell height allowed by the logic design rule of the target technology. This paper also presents energy efficient readout and write schemes for reducing dynamic energy consumption. Post layout simulation using a 65-nm FD-SOI technology shows that the proposed SCM achieves area efficiency of 6.82μm2 per bit (682F2 per bit), which is 20% less than that of the state of the art SCMs. The results also show that the energy consumption of the proposed SCM is 31% less than that of the state of the art low voltage SRAMs.