Traditional CMOS Technology Research Articles

Progress on a Carbon Nanotube Field-Effect Transistor Integrated Circuit: State of the Art, Challenges, and Evolution.

As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore's era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis for achieving nanoscale ultra-large-scale analog/logic circuits. This paper summarizes the development status of the CNTFET compact model and digital/analog/RF integrated circuits. The challenges faced by SPICE modeling and circuit design are analyzed. Meanwhile, solutions to these challenges and development trends of carbon-based transistors are discussed. Finally, the future application prospects of carbon-based integrated circuits are presented.

Efficient 32-nm CNTFET-Based 1-Bit Adder: A Fast and Energy-Optimized Design

CNTFETs are a shows potential choice for traditional CMOS technology due to their potential for lesser power consumption and superior performance. In the present paper, a new 1-bit hybrid full adder has been deliberated and proposed using both pass transistor (PT) and transmission gate logics (TGL), which utilizes a total of 16 transistors. The combination of PT and TGL can lead to improved power efficiency, reduced delay, and enhanced circuit performance in various VLSI applications. For 0.9 V supply voltage at 32-nm CNTFET technology, the power consumption is 0.0748 μW, which is to be an exceptionally low value with a lesser delay of 7.586 Ps and the power-delay-product (PDP) of 0.5674 aJ. The results obtained from this analysis demonstrate the power efficiency, speed, and overall performance of the proposed full adder design. The combination of 32-nm CNTFET technology, deliberate circuit design choices, and the use of specific logic elements (CMOS inverters and strong transmission gates) contributes to the reported characteristics. Using a 0.9 V supply voltage and 32-nm Stanford CNTFET Model technology, the suggested 1-bit adder circuit's concert was investigated using the Mentor Graphics Tool. Finally, using the proposed 1-bit full adder circuit, an N-bit ripple carry adder (N=8, 16 & 32) is implemented and demonstrated. The Simulation results of the 8-bit RCA with a power consumption of 0.373 μW, the delay is 16.852 Ps and the PDP is 6.2857 aJ. These results show that proposed RCA’s have better performance compared to the already reported designs in terms of performance, speed, and power economy.

A new scheme of 2:1 photonic multiplexer and multiplexer-based NOT, OR, AND logic gates in electro-optic Mach–Zehnder interferometer

This paper introduces the development of NOT, OR, and AND logic gates utilizing a 2:1 Multiplexer (MUX) based on a titanium-diffused lithium niobate electro-optic Mach–Zehnder interferometer. The shift towards large-scale optical integrated circuits as an alternative to traditional CMOS technology has gained traction, driven by the growing demand for high-speed computation and data transfer rates, reaching up to the terahertz scale, along with the need for energy-efficient interconnects. To optimize the design and reduce the number of photonic MUX, we leverage Shannon decomposition and Reduced Binary Decision Diagram mapping in the creation of MUX-based combinational and logic circuits. The entire design undergoes comprehensive simulation and verification using OPTIBPM with a beam propagation method (BPM). The wafer dimensions for the 2:1 electro-optic MZI-MUX and MUX-based NOT, AND, OR gates are 33 mm × 100 μm, classifying them as integrated optics. The proposed photonic MUX-based combinational circuits exhibit rapid response times, making them particularly advantageous for communication systems, transmission networks, and various industrial applications. Key device parameters, including insertion loss (0.0012 dB), extinction ratio (ER) (28.97 dB), and contrast ratio (29.5 dB), fall within acceptable limits. The BPM simulated results align well with the mathematical computations based on PYTHON simulations.

Circuit Design of 3- and 4-Bit Flash Analog-to-Digital Converters Based on Memristors

Given its advantageous power- and area-efficiency characteristics and its compatibility with traditional CMOS technology, the memristor has emerged as a promising candidate for low-power applications. To leverage these capacities, a new edge-triggered DFF was proposed, feeding back the master latches’ output to the input of the memristor-based NOR two-stage inverse-phase memristor-based master–slave DFF. Then, a 3-bit flash ADC was designed using the new DFF and simulated to demonstrate its feasibility and correctness. Additionally, a 4-bit flash ADC was implemented and utilized to sample an analog signal, resulting in a correct digital signal. Herein, the 50 nm BSIM4 models were applied. The 3- and 4-bit flash ADCs, respectively, consumed 1.33 mw and 5.84 mw power at a 1 V supply with delay times of 17.8 ns and 70 ns. Compared with previous work, the new 4-bit flash ADC has fewer transistors and smaller power consumption, with about a 25.57% reduction according to the 90 nm process.

A Kind of Optoelectronic Memristor Model and Its Applications in Multi-Valued Logic

Memristors have been proved effective in intelligent computing systems owing to the advantages of non-volatility, nanometer size, low power consumption, compatibility with traditional CMOS technology, and rapid resistance transformation. In recent years, considerable work has been devoted to the question of how to design and optimize memristor models with different structures and physical mechanisms. Despite the fact that the optoelectronic effect inevitably makes the modelling process more complex and challenging, relatively few research works are dedicated to optoelectronic memristor modelling. Based on this, this paper develops an optoelectronic memristor model (containing mathematical model and circuit model). Moreover, the composite memristor circuit (series- and parallel-connected configuration) with a rotation mechanism is discussed. Further, a multi-valued logic circuit is designed, which is capable of performing multiple logic functions from 0–1, verifying the validity and effectiveness of the established memristor model, as well as opening up a new path for the circuit implementation of fuzzy logic.

Ion-Beam Synthesis of Gallium Oxide Nanocrystals in a SiO2/Si Dielectric Matrix.

A new method for creating nanomaterials based on gallium oxide by ion-beam synthesis of nanocrystals of this compound in a SiO2/Si dielectric matrix has been proposed. The influence of the order of irradiation with ions of phase-forming elements (gallium and oxygen) on the chemical composition of implanted layers is reported. The separation of gallium profiles in the elemental and oxidized states is shown, even in the absence of post-implantation annealing. As a result of annealing, blue photoluminescence, associated with the recombination of donor–acceptor pairs (DAP) in Ga2O3 nanocrystals, appears in the spectrum. The structural characterization by transmission electron microscopy confirms the formation of β-Ga2O3 nanocrystals. The obtained results open up the possibility of using nanocrystalline gallium oxide inclusions in traditional CMOS technology.

Design of an Efficient Multilayer Hybrid Reversible Spintronic Ripple Carry Adder Using Quantum Cellular Automata Technique

Quantum-Dot-Cellular-Automata (QCA) using Spintronic electrons is a promising alternative to the traditional CMOS technology in this modern era to design any nano-sized electronic structure. The majority of the current digital components are being designed using QCA-cell-interaction. In some cases, reversible logic with the Spintronic-QCA-technique is also being explored to design various digital components. Because of this, the various aspects for the design of a novel hybrid QCA-based Spintronic advance reversible adder and its efficiency measures are presented in this research work by investigating area-occupation, temperature-tolerance, delay, power dissipation, and output strength. The results obtained in this work establish that the proposed design is more efficient in all respect compared to existing designs reported in recent literature. In this paper, 18nm quantum cells are used to design the proposed structure and when the power dissipation based on the total occupied cell area is calculated (100W/cm2), it is found that there is an assurance to get an adder structure with the less occupied area, less power dissipation and higher speed compared to previously published referred design. The temperature-tolerance and output-strength increment with layer separation gap reduction in multilayer platforms are also some additional advancements of the proposed structure, which are also clearly reflected. In this paper, QCA-based “Ripple-Carry-Adder (RCA)” is designed using Spintronic reversible logic in multilayer mode with different composite elements along with a “3-input-majority-voter-gate (MG)” to make the design more compact. QCADesigner 4.0 tool is used as widespread simulation trains to validate the design outcomes and measure different parameters individually.

An energy efficient high-speed quantum-dot based full adder design and parity gate for nano application

Quantum-dot cellular automata (QCA) are novel prominent emerging nano-computational nanoelectronics technology at the nanoscale. It facilitated computation paradigms and promises an alternative good solution to traditional transistor CMOS technology with faster speed, very low energy dissipation, higher scale integration, small size, low latency/delay of circuits, and higher switching frequency. It is one of the most valuable nanotechnologies (or Nanotech) that effort to fabricate general computational at the nanoscopic-scale by commanding the position of electrons. In this paper, we have proposed the design of novel robust full adder, testable even and odd parity circuits using coplanar single layer in quantum-dots cellular automata nanotechnology. The proposed design of full adder circuits used only 36 quantum dots cells, occupied a design area of 0.04 µm2, and minimum delay count is 0.75 clock cycles. The proposed circuit’s investigated by novel QCADesigner-E (Energy) tool on using coherence vector (w/Energy) engine and optimized the energy-dissipation (ED) of full adder circuit. In the proposed design do not use coplanar multilayer and 45-degree rotated cells but used regular synchronized clock cycle and minimum quantum-dots cells. Therefore overall manufacturability of the robust full adder circuits significantly more improves as compared to the existing design. The presented robust full adder design have been calculated the total ED (Sum_Ebath) is 1.70e−002 eV (Error: +/- −1.63e−003 eV), and average ED/cycle (Avg_Ebath) is 1.54e−003 eV (Error: +/- −1.48e−004 eV).

IEEE Open Journal of the Solid-State Circuits Society Special Section on Integrated Circuits and Systems Based on Thin-Film Transistors

Thin-Film transistors (TFTs) are ubiquitous today as a backplane technology for various display and imager products. Those transistors act as switches in active-matrix liquid-crystal displays (AM-LCDs) or as full-pixel engines, including driving and threshold compensation, in active-matrix organic light-emitting diodes (AM-OLEDs) panels. TFT manufacturing requires only a limited amount of photolithographic steps, making it a relatively simple transistor technology, compared to the traditional Si CMOS technologies. The processing temperature of TFT technologies is sufficiently low to be compatible with glass and can even enable flexible substrates. Finally, these transistors have been developed specifically for large-area applications, such as televisions and X-ray scanners. Consequently, the backplane size for TFTs has evolved from the generation-1 glass panel of 270 mm by 360 mm to generation-10.5, which is manufactured on a glass panel of 2.94 m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times3.37$ </tex-math></inline-formula> m <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> . This is profoundly different from traditional Si CMOS integrated circuits, which are fabricated nowadays on 200 mm or 300 mm round wafers. The critical dimension of the TFT technology on glass or flexible substrate in production is in the range of a few micrometers. The TFT research in the display field focuses on enabling increasingly better pixel resolution, improved visual quality, larger panels for LED walls, flexible displays, camera-behind display, sensor integration, and many more.

Efficient designs of high-speed combinational circuits and optimal solutions using 45-degree cell orientation in QCA nanotechnology

To fabricate digital logic circuits withsmaller size, ultra-low power consumption, high-speed, and reliable operation at high frequencies like THz. The quantum-dot cellular automata (QCA) are a novel nanoelectronics nano-technology. It is considered a resolution to the scaling problems in CMOS and VLSI technology. This paper will implement nanoscale-based adder, subtractor, and 1-bit comparator structures using QCA nanotechnology. It is being researched as a possible replacement for traditional CMOS technology. In this paper, we have proposed and investigated the cell rotation problem and provided optimal solutions of 45-degree cell arrangement with its appropriate position. The proposed QCA design effectively reduces the cell count and required area inμm2propagation delay and the complexity of the circuits. The proposed simulation-results of a two-input adder, subtractor, and 1-bit comparator architecture were examined and compared with existing designs using the QCADesigner-E tool. The proposed adder, subtractor and 1-bit comparators occupy design area of 21240.00 nm2 (0.02 um2), 21182.00 nm2 (0.02 um2) and 31284.00 nm2 (0.03 um2) respectively. The observed latency is 0.5 clock cycles for adder and sub, and 0.75 clock cycles for 1-bit comparators. In terms of used equal four-dots QCA cell of 21 cells for adder, sub, and 33 cells for 1-bit comparators circuits with applied synchronized QCA clock cycles methodology. The presented design in this paper will be useful for designing and explaining nano-devices for usage in various nanotechnology applications.

32-bit Kogge-Stone based Hybrid Adder Implemented using Standard Cells of Different Logic Families

Adders performs a critical role in all computational operations, thereby optimizing them with respect to design constraints for a system is essential. In this paper, standard cells of different logic families, namely- CMOS, Pseudo NMOS, and MGDI, are designed in Cadence Design Suite Virtuoso 6.1.7 in 180nm technology and characterized using Liberate 15.1.3. The standard cell libraries thus created are then applied to 32-bit KSA (Kogge-Stone Adder) and KSA based proposed hybrid adder that are implemented in Verilog, functionally verified on Xilinx Vivado 2020.2 and synthesized on Cadence Genus 15.22. Pseudo NMOS logic shows 14.03% area savings and MGDI offers 54.43% power saving based on area per cell over the traditional CMOS technology. It is also seen that the proposed adder offers a decrease in power and delay by 32.13% and 13.75% over KSA, respectively, in CMOS logic. Further discussions are made and suitable applications for all designs are also discussed.

Guest Editors' Words

This special edition presents seven invited works that focus on different aspects of the design with emerging technologies. With silicon facing barriers to the future development of traditional CMOS technology, it is now time to think ahead and look for new alternatives that can add exciting new characteristics to future applications. In this sense, new materials and substrates must be investigated. Some of them enable the development of fast and low power switching devices that represents digital state by different physical properties, such as optical excitation, magnetic field, and phase state. Associated with that, new non-von Neumann computing architectures can be explored, including computing-in-memory that minimizes the problems associated to data transfer between memory and logic units. In the following, we present a short description of the papers appearing in this Special Issue.

Deep Pipeline Circuit for Low-Power Spintronic Devices

As the traditional CMOS technology encounters significant scaling challenges, many emerging beyond-CMOS devices have been proposed and developed to augment or even replace CMOS devices. Spintronic devices have received extensive attention due to several unique attributes, including a low operation voltage and nonvolatility. However, spintronic devices are intrinsically slow because of the long switching delay of the magnet. To overcome the drawback, in this article, we propose and develop a deep pipeline method for generic spintronic majority-gate-based circuits. A fast and efficient pipeline buffer insertion methodology is integrated into the industry-standard placement and routing design flow to ensure the correct functionality. The proposed framework can accurately capture 1) the timing of a multiphase clock-gated spintronic circuit and 2) the energy overhead associated with the supply clocking, which is one major overhead of spintronic circuits. Based on the proposed framework, we demonstrate that a spintronic circuit implemented with a deep pipeline can provide over $10\times $ reduction in energy-delay products compared to their traditional CMOS-based counterparts. In the case study, the proposed deep pipeline method is applied to three emerging spintronic devices. Results show that device-level parameters have significant impacts on circuit-level performance and optimal logic depth.

Wafer-level direct bonding of optimized superconducting NbN for 3D chip integration

3D integration has well-developed for traditional CMOS technology operating at room temperature, but few studies have been performed for cryogenic applications such as quantum computers. In this paper, a wafer-to-wafer bonding of superconductive joints based on niobium nitride (NbN) is performed to demonstrate the possibility of 3D integration of superconducting chips. The NbN thin films are deposited by magnetron sputtering. Its high critical temperature (15.2 K) is achieved by optimizing the sputtering recipe in terms of N2 flow rate and discharge voltage. Wafer-level bumping is bonded by the thermo-compression method. The sheet resistance of the thin film and the contact resistance of the joints are measured by the Greek-cross (4-point Kelvin method) and daisy chain structures at cryogenic temperature, respectively. Direct-bonding wafers with NbN superconductive joints avoid using adhesive layers and the bonding interface could still present superconducting electrical connections in a cryogenic environment above 4 K, which will allow us to use a smaller and high-cooling power cryostat. The contribution of this work could lead to the fabrication of multi-layered superconducting chip that operates beneficially in cryogenic temperature, which is essential in building scalable quantum processors.

An Ultra-Low Cost Multilayer RAM in Quantum-Dot Cellular Automata

Quantum-dot cellular automata (QCA) is an alternative nanotechnology to traditional CMOS technology. In theory, circuits in QCA have the advantages of lower power consumption, higher integration density and switching frequency than circuits based on CMOS. Random access memory (RAM) circuits that are critical in designing large memory circuits have been explored. In this brief, a novel loop-based RAM cell with asynchronous set and reset, by using a new 2-1 multiplexer and D-latch, is proposed. Efficient 1 $\times $ 4 RAM and 4 $\times $ 4 RAM with three-layer structure are constructed. The proposed RAM cell has 35% improvement in both circuit footprint and cost, compared with an existing best scheme. The 1 $\times $ 4 RAM has less cells, delay and area than the previous designs with the same circuit scheme. The 4 $\times $ 4 RAM and ${m}\,\,\times \,\,{n}$ RAM show that the proposed RAM cell has excellent scalability for designing complex circuits. Functional correctness of the proposed designs has been proved by using QCADesigner 2.0.3.

A Fully Programmable eFPGA-Augmented SoC for Smart Power Applications

This paper proposes a reconfigurable system on chip (SoC) for smart power applications. The system is composed of an ultra-low-power microcontroller for standard software programmability, coupled to an embedded-FPGA (eFPGA) to perform control-driven applications and lightweight digital signal processing, at lower power consumption and higher responsiveness than with processor-based execution. To the best of our knowledge, this is the first heterogeneous reconfigurable SoC targeting smart power applications. The SoC targets BCD technologies integrating bipolar, CMOS, and DMOS devices, typically featuring a small number of metal layers when compared with the traditional CMOS technologies. The added value of the proposed system is that the digital system is fully synthesizable since the eFPGA is based on a soft-core approach. This paper presents the results of integrating an eFPGA with a computational capability of $\simeq 1\text{k}$ equivalent gates in STMicroelectronics 90-nm BCD technology featuring five metal layers and high- $k$ transistors. We benchmarked our architecture on a wide range of applications relevant to the smart power domain. eFPGA integration in SoCs introduces a 20%–27% area overhead but has a straightforward benefit in terms of energy consumption, which proves reduction from about $10\times $ to $800\times $ . In terms of latency, the eFPGA implementation allows a gain from $8\times $ to $145\times $ comparing the pure cycles count.

An efficient design of CORDIC in Quantum-dot cellular automata technology

ABSTRACTPower dissipation of future-integrated systems, consisting of a numberless of devices, is a challenge that cannot be easily solved by classical technologies. Quantum-dot Cellular Automata (QCA) is a Field-Coupled Nanotechnology (FCN) and a potential alternative to traditional CMOS technologies. It offers various features like extremely low-power dissipation, very high operating frequency and nanoscale feature size. This study presents a novel design of CORDIC circuit based on QCA technology. The proposed circuit is based on several proposed QCA sub-modules as adder and Flip-Flop. To design and verify the proposed architecture, QCADesigner tool is employed and power consumption is estimated using QCAPro software. The proposed QCA CORDIC achieves about 69% reduction in power and area compared to previous existing designs. The outcome of this work can open up a new window of opportunity for the design of the CORDIC module and can be used in low-power signal and image processing systems.

A Carry Lookahead Adder Based on Hybrid CMOS-Memristor Logic Circuit

Memristor-based digital logic circuits open new pathways for exploring advanced computing architectures, which provide a promising alternative to conventional IC technology. In several memristor-based logic design methods, the memristor ratioed logic (MRL) is compatible with traditional CMOS technology. Two kinds of carry-lookahead adders (CLA) based on the hybrid CMOS-memristor structure are proposed, within which one is based on MRL logic, and the other is an improved one that is implemented by MRL universal gate (MRLUG). The proposed CLAs are verified by theoretical analyses and simulations, showing that the proposed design method requires fewer memristors and CMOSs than the IMP-based or CMOS-based CLAs, which means smaller circuit size and lower power consumption.

A Comprehensive Time-Dependent Dielectric Breakdown Lifetime Simulator for Both Traditional CMOS and FinFET Technology

This paper presents techniques for gate-oxide and middle-of-line (MOL) time-dependent dielectric breakdown (TDDB) lifetime assessment of microprocessors and digital circuits. Both traditional CMOS and the state-of-art FinFET technology are taken into consideration. A circuit’s lifetime distribution depends on its usage and the resulting temperature profile. Emulation of the circuit operation extracts the relevant usage parameters. These parameters are converted to state probabilities at the inputs of the standard cells. The lifetime distributions of standard cells are characterized by taking into account all possible input state probabilities and die-to-die process variations. Because MOL TDDB depends on the layout, a step involved in estimating the lifetime distributions of standard cells is the analysis of the layout for MOL TDDB. Two different methods to extract the layout features are presented for traditional CMOS and FinFET technologies. By precharacterizing the standard cell lifetime distribution, our simulator can find the lifetime limiting cells in a circuit, and thus, circuit designers can replace such cells with a combination of standard cells with a longer lifetime to make the circuit more robust. The results also indicate that we need to pay more attention to the newly emerging MOL TDDB when designing new standard cells for FinFET technology.

The Role of Magnetic Quantum Dot Cellular Automata In Replacing Traditional CMOS Technology

The Role of Magnetic Quantum Dot Cellular Automata In Replacing Traditional CMOS Technology