Abstract
3D integration has well-developed for traditional CMOS technology operating at room temperature, but few studies have been performed for cryogenic applications such as quantum computers. In this paper, a wafer-to-wafer bonding of superconductive joints based on niobium nitride (NbN) is performed to demonstrate the possibility of 3D integration of superconducting chips. The NbN thin films are deposited by magnetron sputtering. Its high critical temperature (15.2 K) is achieved by optimizing the sputtering recipe in terms of N2 flow rate and discharge voltage. Wafer-level bumping is bonded by the thermo-compression method. The sheet resistance of the thin film and the contact resistance of the joints are measured by the Greek-cross (4-point Kelvin method) and daisy chain structures at cryogenic temperature, respectively. Direct-bonding wafers with NbN superconductive joints avoid using adhesive layers and the bonding interface could still present superconducting electrical connections in a cryogenic environment above 4 K, which will allow us to use a smaller and high-cooling power cryostat. The contribution of this work could lead to the fabrication of multi-layered superconducting chip that operates beneficially in cryogenic temperature, which is essential in building scalable quantum processors.
Highlights
Superconducting integrated circuits (SIC) surpass complementary metal–oxide–semiconductor (CMOS) in the computing domain with many advantages including faster switching speed, low power dissipa tion, and information transfer at limited software complexity [1]
3D integration has well-developed for traditional CMOS technology operating at room temperature, but few studies have been performed for cryogenic applications such as quantum computers
A wafer-towafer bonding of superconductive joints based on niobium nitride (NbN) is performed to demonstrate the possibility of 3D integration of superconducting chips
Summary
Superconducting integrated circuits (SIC) surpass complementary metal–oxide–semiconductor (CMOS) in the computing domain with many advantages including faster switching speed, low power dissipa tion, and information transfer at limited software complexity [1]. As the field of superconducting quantum computing advances from the few-qubit stage to large-scale devices, scalability requirements will necessitate the use of standard 3D packaging and integration processes. Large-scale qubit arrays would require integration of high density I/O connections to external control circuits. It has advantages in comparison to wire bonding including better thermal and electrical performance, higher density I/O capability and wafer-scale bump process develop ment. Other advantages include minimising switching noise in sensitive signal paths and shielding the I/O bumps from noises by other compo nents [9]. Such industrial technique is yet to be developed with superconducting materials for integration of qubit arrays
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