Efficient designs of high-speed combinational circuits and optimal solutions using 45-degree cell orientation in QCA nanotechnology

Abstract

To fabricate digital logic circuits withsmaller size, ultra-low power consumption, high-speed, and reliable operation at high frequencies like THz. The quantum-dot cellular automata (QCA) are a novel nanoelectronics nano-technology. It is considered a resolution to the scaling problems in CMOS and VLSI technology. This paper will implement nanoscale-based adder, subtractor, and 1-bit comparator structures using QCA nanotechnology. It is being researched as a possible replacement for traditional CMOS technology. In this paper, we have proposed and investigated the cell rotation problem and provided optimal solutions of 45-degree cell arrangement with its appropriate position. The proposed QCA design effectively reduces the cell count and required area inμm2propagation delay and the complexity of the circuits. The proposed simulation-results of a two-input adder, subtractor, and 1-bit comparator architecture were examined and compared with existing designs using the QCADesigner-E tool. The proposed adder, subtractor and 1-bit comparators occupy design area of 21240.00 nm2 (0.02 um2), 21182.00 nm2 (0.02 um2) and 31284.00 nm2 (0.03 um2) respectively. The observed latency is 0.5 clock cycles for adder and sub, and 0.75 clock cycles for 1-bit comparators. In terms of used equal four-dots QCA cell of 21 cells for adder, sub, and 33 cells for 1-bit comparators circuits with applied synchronized QCA clock cycles methodology. The presented design in this paper will be useful for designing and explaining nano-devices for usage in various nanotechnology applications.