Track-and-hold Amplifier Research Articles

A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS

A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with a sample-and-hold (S/H) sharing technique and a gain-boosted voltage-to-time converter (VTC) is presented for high-speed wireline communication systems. By sharing one S/H between coarse and fine stages in the two-step flash ADC, the input bandwidth as well as area and power efficiency can be improved without a gain error between coarse and fine ADCs. Thanks to an eight-time interpolation using the gain-boosted VTC, the fine ADC has a small gate capacitance without a speed penalty, even in a small input voltage range. A prototype ADC implemented in a 40 nm CMOS process occupies a 0.1 mm2 active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset and gain calibrations were 0.45 and 0.39 least significant bit (LSB), respectively. With a 9.042 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were 30.12 and 40.23 dB, respectively. The small input capacitance of the sub-ADC enables a power-efficient track-and-hold amplifier (THA), resulting in a power consumption of 56.2 mW under a supply voltage of 0.9 V. The prototype ADC achieves a figure of merit (FoM) of 107.4 fJ/conversion-step at 20 GS/s.

Track and Hold Amplifier Investigation for 100-GHz Bandwidth, 200-GS/s ADC Front Ends

We report on the track and hold amplifier (THA) topology choice and design details of a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> time-interleaved 200-GS/s SiGe BiCMOS ADC front end with a measured SNDR > 25 dB up to 63 GHz, and with a large signal bandwidth of 58 GHz when subsampling at 5 GS/s. We show that by replacing the current-mode-logic (CML) MOS switch with a quasi-CML switch and increasing the tail current, a THA with a measured small-signal bandwidth of 101 GHz is obtained in the same 55-nm SiGe BiCMOS technology. The ADC front end bandwidth could thus be further improved at the same sampling rate.

A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With &gt;55-dBFS SNR and &gt;67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

In this article, a 3 GS/s Time-Interleaved (TI) RF Track-and-Hold (TaH) amplifier designed in a 22 nm SOI technology is presented. The TaH amplifier is designed to drive an ADC, which can be either two pipeline-ADCs or two rows of SAR-ADCs. Both TI TaH are driven by a single RF-matched wide-band bulk-controlled Front-End (FE) buffer. The measured TaH amplifier has a SFDR beyond 70 dBc up to 2.5 GHz and remains above 67 dBc till 3 GHz enabling sub-sampling. An overall system bandwidth of 4.5 GHz is achieved with a SNR above 55 dBFS. The ultra-low-jitter clock regeneration has only 45 fs rms jitter not limiting the SNR up to 3 GHz. Two-tone and multi-tone measurements reveal a third inter-modulation and inter-band non-linearity with >72 dBFS and >82 dBFS respectively. Off-chip calibration of offset/gain mismatch and time-skew between both TaH-lanes reduce interleaving spurs >75 dBFS utilizing a 37-tap fractional delay FIR filter. The efficient body-bias control of the technology is used to dynamically body-bias the TaH sample-switch increasing bandwidth by 10% improving settling performance while at the same time the leakage decreases. Static body-biasing is also applied to the common-mode-feedback by using the bulk as an control node. The TaH amplifier including the clock generation consumes only 178 mW from a triple 2 V/0.9 V/-0.8 V supply.

A 25-GSa/s InP DHBT Track-and-Hold Amplifier Using Active Peaking Input Buffer

In this letter, we present a 25-GSa/s wideband track-and-hold amplifier using 0.8- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mu }\text{m}$ </tex-math></inline-formula> indium phosphide (InP) process for high-speed analog sampling front-end. In this design, an active peaking input buffer is first used in the base–collector switching diode sampler. Moreover, it is carefully calculated and analyzed. The dominant pole in the signal path of the circuit is canceled by one zero produced by the active peaking structure; therefore, the bandwidth (BW) is extended. The experimental results show that a total harmonic distortion (THD) of less than −27 dBc and a spurious-free dynamic range (SFDR) of better than 32.5 dB are demonstrated at a 25-GSa/s sampling rate. In the hold mode, the isolation is better than −42 dB. In addition, it has an 0.156 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f_{T}}$ </tex-math></inline-formula> BW from dc to 25 GHz within 160-GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f_{T}}$ </tex-math></inline-formula> , which is a very competitive value compared with other reported track-and-hold amplifiers (THAs) using the InP process.

Optically Enabled ADCs and Application to Optical Communications

Electrical-optical signal processing has been shown to be a promising path to overcome the limitations of state-of-theart all-electrical data converters. In addition to ultra-broadband signal processing, it allows leveraging ultra-low jitter mode-locked lasers and thus increasing the aperture jitter limited effective number of bits at high analog signal frequencies. In this paper, we review our recent progress towards optically enabled time-and frequency-interleaved analog-to-digital converters, as well as their monolithic integration in electronic-photonic integrated circuits. For signal frequencies up to 65 GHz, an optoelectronic track-andhold amplifier based on the source-emitter-follower architecture is shown as a power efficient approach in optically enabled BiCMOS technology. At higher signal frequencies, integrated photonic filters enable signal slicing in the frequency domain and further scaling of the conversion bandwidth, with the reconstruction of a 140 GHz optical signal being shown. We further show how such optically enabled data converter architectures can be applied to a nonlinear Fourier transform based integrated transceiver in particular and discuss their applicability to broadband optical links in general.

A 12-b 18-GS/s RF Sampling ADC With an Integrated Wideband Track-and-Hold Amplifier and Background Calibration

We discuss a 12-b 18-GS/s analog-to-digital converter (ADC) implemented in 16-nm FinFET process. The ADC is composed of an integrated high-speed track-and-hold amplifier (THA) driving up to eight interleaved pipeline ADCs that employ open-loop inter-stage amplifiers. Up to 10 GS/s, the THA operates at the full sampling rate using a non-interleaved single sample network, thereby eliminating the interleaving sampling time and bandwidth mismatch. Above 10 GS/s, the THA is programmed to use two ping-ponged, or an optional (2 + 1) randomized, sample networks to spread the residual post-calibration interleaving spurs in the noise floor. The THA enables an input bandwidth of 18 GHz and employs dither injection and optional pseudorandom chopping. In the pipeline stages, dither-based background calibration detects and corrects gain, settling, memory, and kick-back errors. New dither-based background calibration algorithms are employed to detect and correct the arbitrary non-linearity in the form of integral non-linearity (INL) breaks and harmonic distortion up to the fifth order in the THA and in the references, DACs, and inter-stage open-loop amplifiers of the pipeline ADCs. Moreover, new dither-based background calibration is implemented to detect and correct the chopping non-idealities, memory errors, interleaving mismatches, and order-dependent randomization errors. Compared to the fastest state-of-the-art with similar performance, this ADC achieves 80% higher sample rate and 2.4× higher input bandwidth, and incorporates a THA that supports a 3.3× higher non-interleaved sample rate.

A Broadband InP Track-and-Hold Amplifier Using Emitter Capacitive/Resistive Degeneration

In this letter, we present a 24-GSa/s, >20-GHz wideband track-and-hold amplifier (THA) based on indium phosphide (InP) double-heterojunction bipolar transistor (DHBT) technology for high-speed sampling systems. In the proposed approach, the output pole of the input stage is canceled by the zero produced by the emitter capacitive/resistive degeneration, and the bandwidth is thereby extended without voltage drop. The compensation technique for $V_{\mathrm{be}}$ modulation in the output stage is introduced to reduce distortion. The monolithic microwave integrated circuit (MMIC) prototype occupies only 0.69 mm2, and the experimental results show that it has a 0.112– $f_{T}$ bandwidth from dc to 22.3 GHz, which is wider than any ratio reported compact THA solutions using the InP technology. In addition, a spurious-free dynamic range (SFDR) of better than 42 dB and total harmonic distortion (THD) of less than −25 dBc are demonstrated at a 24-GSa/s sampling rate. The THA consumes only 374 mW, which is among the lowest dc power dissipation reported for the InP technology.

A Low-Power Low-Distortion 20-GS/s Flash Analog-to-Digital Converter for Coherent Optical Receiver in 0.13-μm SiGe BiCMOS

High-speed, low-power analog-to-digital converter (ADC) is a critical element for 5-GBd, 20-Gb/s digital signal processing (DSP)-based coherent optical communication receiver. To satisfy high data transmission rate requirement of optical receiver, a single-core and open-loop flash ADC with a new proposed multiplexer-based encoder is presented in this paper. Compared with conventional encoder topology, the new proposed topology achieves the fastest encoding speed and lowest power consumption. The optimized distortion is achieved by utilizing a leakage current compensation technique and a local negative feedback method in switched-buffer track-and-hold amplifier (THA). Strict synchronization is obtained for clock signals by careful designing of layout in tree-based clock networks. Furthermore, a master–slave comparator incorporated with a preamplifier reduces signal-dependent kickback noise as well as offset voltage. By using master–slave comparators and proposed encoders, the sampling rate is up to 21.12[Formula: see text]GS/s. The 4-bit, 20-GS/s flash ADC is realized in 0.13-[Formula: see text]m SiGe BiCMOS technology and it only occupies 1.05[Formula: see text]mm[Formula: see text][Formula: see text][Formula: see text]1.46[Formula: see text]mm chip area. With a power consumption of 1.831[Formula: see text]W from 4-V supply, the ADC achieves an effective number of bits (ENOB) of 2.5 at 15[Formula: see text]GS/s.

An 8 GS/s 20 GHz bandwidth master‐slave track‐and‐hold amplifier in 65 nm CMOS

AbstractA 65 nm CMOS fully‐differential track‐and‐hold amplifier (THA) in master‐slave configuration is presented. For high‐speed operation, Cherry‐Hooper amplifier with input inductive‐peaking and switched‐source follower (SSF) circuit are used for the front‐end preamplifier and master/slave track‐and‐hold circuits, respectively. On‐wafer testing in single‐ended input/output configuration shows that the fabricated THA exhibits 20 GHz switched‐mode bandwidth and 11.9 dB conversion gain at 8 GS/s clock, with THD &lt; −36 dB and SFDR &gt;36 dB within the 3‐dB bandwidth, while consuming 361 mW of dc power at 2.6 V supply. This work represents the highest input bandwidth for master‐slave THA in CMOS, to the best of authors' knowledge. The chip area is 0.681 mm2 including pads (active chip area: 0.2 mm2).

DC‐16 GHz GaAs track‐and‐hold amplifier using sampling rate and linearity enhancement techniques

A DC-16 GHz track-and-hold amplifier (THA) using 0.15-μm enhancement-mode GaAs pseudomorphic high-electron mobility transistor process is presented. A switched source follower (SSF) track-and-hold (T/H) stage is modified to enhance the sampling rate and linearity. The input-dependent timing jitter is highly reduced using the modified topology as compared to the conventional SSF T/H stage. Moreover, the even harmonics are successfully suppressed using the differential topology, and the spurious-free dynamic range (SFDR) and total harmonic distortion (THD) are improved. To widen bandwidth (BW), the input and output buffers are designed using the distributed amplifier and source follower, respectively. With a sampling rate of 13.5 GS/s, the proposed THA features a measured 3-dB BW of 16 GHz, an SFDR of 46 dB, and a THD of −45 dB.

Silicon Millimeter-Wave, Terahertz, and High-Speed Fiber-Optic Device and Benchmark Circuit Scaling Through the 2030 ITRS Horizon

This paper reviews the technology requirements of future 100–300-GHz millimeter-wave (mm-wave) systems-on-chip (SOI) for high data rate wireless and sensor applications, as well as for 100–300-GBaud fiber-optic communication systems. Measurements of state-of-the-art silicon metal–oxide–semiconductor field-effect transistors (MOSFETs), SiGe heterojunction bipolar transistors (HBTs), and of a variety of HBT-HBT and MOS-HBT cascodes are presented from dc to 325 GHz. The challenges facing mm-wave MOSFET and SiGe HBT device and benchmark circuit scaling toward 2–3-nm gate length and beyond 2-THz transistor $f{\mathrm {MAX}}$ are discussed for the first time based on technology computer-aided design (TCAD) and atomistic simulations. Finally, simulations of the scaling of the SiGe HBT analog and mixed-signal mm-wave benchmark circuit performance across future technology nodes predict that PAs with 45% power added efficiency (PAE) at 220 GHz, track and hold amplifiers (THAs) with over 140-GHz bandwidth, and transimpedance amplifiers (TIAs) with 250-GHz bandwidth and less than 5-dB noise figure will become feasible by 2030. Comparison of simulations and measurements for representative benchmark circuits such as TIAs, THAs, linear modulator drivers, digital-to-analog converters (DACs), and power amplifiers (PAs), fabricated in advanced SiGe BiCMOS and nanoscale SOI complementary metal–oxide–semiconductor (CMOS) technologies, and operating at 120 Gb/s and above 100 GHz, respectively, are presented to support the credibility of the benchmark circuit scaling exercise.

A 2 GSps, 8-Bit Folding and Interpolation ADC with Foreground Calibration in 90 nm CMOS Technology

A single channel 2 GSps, 8-bit folding and interpolation (F&amp;I) analog-to-digital converter (ADC) with foreground calibration in TSMC 90 nm CMOS technology is presented in this paper. The ADC utilizes cascaded folding, which incorporates an interstage sample-and-hold amplifier between the two stages of folding circuits to enhance the quantization time. A master-slave track-and-hold amplifier (THA) with bootstrapped switch is taken as the front-end circuit to improve ADC’s performance. The foreground digital assisted calibration has also been employed to correct the error of zero-crossing point caused by the circuit offset, thus improving the linearity of the ADC. Chip area of the whole ADC including pads is 930 μm × 930 μm. Postsimulation results demonstrate that, under a single supply of 1.2 volts, the power consumption is 210 mW. For the sampling rate of 2 GSps, the signal to noise and distortion ratio (SNDR) is 45.93 dB for Nyquist input signal.

A 10-GS/s 6-Bit Track-and-Hold Amplifier for Time-Interleaved SAR ADCs in 65-nm CMOS

This paper presents a 10-GS/s 6-bit track-and-hold amplifier (THA), which is designed for a 16-way time-interleaved successive approximation register (SAR) analog to digital converter (ADC). To extend the bandwidth, a differential source-degenerated common-source amplifier with peaking inductance is adopted as an input buffer. A switched source follower master track-and-hold stage samples the 800-mVPP differential input signal at 10[Formula: see text]GHz. Moreover, the THA cancels the feed-through in hold mode by a clock-controlled transistor. The proposed THA is simulated in 65-nm CMOS technology. It operates with 1.8/1.2-V supply and consumes 84.8[Formula: see text]mW. At a sampling rate of 10[Formula: see text]GS/s, [Formula: see text]41-dB total harmonic distortion (THD) is achieved with input frequencies up to 5[Formula: see text]GHz.

A 55-GHz-Bandwidth Track-and-Hold Amplifier in 28-nm Low-Power CMOS

This brief presents a 25-GS/s track-and-hold amplifier (THA) implemented in a 28-nm low-power digital CMOS process. Given the intrinsic low-pass behavior of the THA core, a frequency compensation technique is employed to improve the bandwidth by increasing the input amplitude for higher frequencies. This enhances the small-signal bandwidth by almost 30% to 70 GHz. Large-signal measurements show a 3-dB corner frequency of 55 GHz, which enables a performance sufficient for time-interleaved analog-to-digital converter systems operating above 100 GS/s. At a peak-to-peak input amplitude of 400 mV, the total harmonic distortion is −32 dB for a 50-GHz input signal at a dc power consumption of 73 mW.

A 12-bit track and hold amplifier for giga-sample applications

The paper presents a track-and-hold amplifier (THA), based on the switched emitter follower topology, suitable for emerging receivers architectures and data acquisition systems. The THA exploits four concurrent techniques, all described in the paper, which allow to reduce the hold-mode feedthrough; to attenuate the differential droop rate; to improve the linearity of the input buffer; and to optimize the third order harmonic distortion for RF sampling operation. The effectiveness of this novel approach is demonstrated using a low cost 0.35 μm SiGe technology. The THA core draws about 145 mA from 3.5 V supply. The THA provides a spurious-free dynamic range (SFDR) better than 72 dB when it is used for sampling an incoming signal of 0.9 Vpp centered around 925 MHz at a sampling rate of 0.5 GS/s. The THA allows a max sampling frequency equal to 6 GS/s and a max input frequency equal to 2.5 GHz and provides a SFDR better than 50 dB in all the available working conditions.

A 6-bit 3-Gsps ADC implemented in 1 μm GaAs HBT technology

The design and test results of a 6-bit 3-Gsps analog-to-digital converter (ADC) using 1 μm GaAs heterojunction bipolar transistor (HBT) technology are presented. The monolithic folding-interpolating ADC makes use of a track-and-hold amplifier (THA) with a highly linear input buffer to maintain a highly effective number of bits (ENOB). The ADC occupies an area of 4.32 × 3.66 mm2 and achieves 5.53 ENOB with an effective resolution bandwidth of 1.1 GHz at a sampling rate of 3 Gsps. The maximum DNL and INL are 0.36 LSB and 0.48 LSB, respectively.

Switched Current Integrating Sampler for Time Interleaved ADCs

With the continued improvements in time-interleaved ADC (TIADC) performance, the power of voltage buffer in input track-and-hold amplifier (THA) driving the ADC input capacitor becomes a major component of the overall power consumption. To reduce the input buffer power consumption, switched current integrating sampler (CIS) is proposed. Switched CIS is analyzed and compared to the conventional THAs. To fairly compare the power consumption of both circuits under different operating conditions, power consumption equations are derived. Circuit level simulations are performed to validate these equations. The switched CIS is shown to consume approximately 50% of the conventional switched THA power for medium resolution (i.e., 8b) TIADCs.

A low-power 20 GSps track-and-hold amplifier in 0.18 μm SiGe BiCMOS technology

An open-loop 20 GSps track-and-hold amplifier (THA) using fully-differential architecture to mitigate common-mode noise and suppress even-order harmonics is presented. CMOS switch and dummy switches are adopted to achieve high speed and good linearity. A cross-coupled pair is used in the input buffer to suppress the charge injection and clock feedthrough. Both the input and output buffers use an active inductor load to achieve high signal bandwidth. The THA is realized with 0.18 μm SiGe BiCMOS technology using only CMOS devices at a 1.8 V voltage supply and with a core area of 0.024 mm2. The measurement results show that the SFDR is 32.4 dB with a 4 GHz sine wave input at a 20 GSps sampling rate, and the third harmonic distortion is −48 dBc. The effective resolution bandwidth of the THA is 12 GHz and the figure of merit is only 0.028 mW/GHz.

Computer Program Calculation for Distortion of Wide-Band Track and Hold Amplifier

Tow different computer calculation methods for distortion of the wide-band diode bridge track and hold amplifier (THA) are presented based on a high frequency Schottky diode model. One of the computer programs calculates the distortion of weekly nonlinear THA based on the KCL and the nonlinear-current method. The other calculates the weekly nonlinear distortion by using a Volterra series method and a nodal formulation. Comparative calculation results for the diode bridge THA have shown good agreement with these two computer program calculation methods, whereas the overall computational efficiency of the nonlinear-current method is better than that of the nodal formulation method in a special evaluation.

Design of a 1‐GSample/s 9‐b double sampling track‐and‐hold amplifier in BiCMOS technology

SUMMARYThis paper gives a detail presentation of a fully pseudo‐differential open‐loop BiCMOS track‐and‐hold amplifier (THA) for 9‐b operation up to 1 GSample/s. The proposed THA not only uses a double sampling technique to increase the achievable sampling frequency by a factor of two, but also employs a linearization technique to reduce the gain dependence of the THA input stage upon the input level. Moreover, timing mismatch between the clock signals of the two interleaved paths is minimized by means of a timing mismatch insensitive clock generator controlled by a common master sampling clock. The post‐layout simulation results using TSMC 75 GHz fT, 0.35‐µm SiGe BiCMOS technology show that the proposed architecture achieve a signal to noise and distortion ratio of 53.92 dB, equivalent to the effective number of bits of 8.66‐b for 58.11 MHz input frequency at 1 GSample/s. The power dissipation of the whole THA is 161.1 mW. Copyright © 2012 John Wiley &amp; Sons, Ltd.