A 3-GS/s RF Track-and-Hold Amplifier Utilizing Body-Biasing With >55-dBFS SNR and >67-dBc SFDR Up to 3 GHz in 22-nm CMOS SOI

Abstract

In this article, a 3 GS/s Time-Interleaved (TI) RF Track-and-Hold (TaH) amplifier designed in a 22 nm SOI technology is presented. The TaH amplifier is designed to drive an ADC, which can be either two pipeline-ADCs or two rows of SAR-ADCs. Both TI TaH are driven by a single RF-matched wide-band bulk-controlled Front-End (FE) buffer. The measured TaH amplifier has a SFDR beyond 70 dBc up to 2.5 GHz and remains above 67 dBc till 3 GHz enabling sub-sampling. An overall system bandwidth of 4.5 GHz is achieved with a SNR above 55 dBFS. The ultra-low-jitter clock regeneration has only 45 fs rms jitter not limiting the SNR up to 3 GHz. Two-tone and multi-tone measurements reveal a third inter-modulation and inter-band non-linearity with >72 dBFS and >82 dBFS respectively. Off-chip calibration of offset/gain mismatch and time-skew between both TaH-lanes reduce interleaving spurs >75 dBFS utilizing a 37-tap fractional delay FIR filter. The efficient body-bias control of the technology is used to dynamically body-bias the TaH sample-switch increasing bandwidth by 10% improving settling performance while at the same time the leakage decreases. Static body-biasing is also applied to the common-mode-feedback by using the bulk as an control node. The TaH amplifier including the clock generation consumes only 178 mW from a triple 2 V/0.9 V/-0.8 V supply.