Total Ionizing Dose Radiation Research Articles

Radiation effects on scientific complementary metal-oxide-semiconductor detectors for x-ray astronomy: II. Total ionizing dose irradiation

Radiation effects on scientific complementary metal-oxide-semiconductor detectors for x-ray astronomy: II. Total ionizing dose irradiation

Dynamic Degradation of Planar-Gate SiC MOSFETs After Total Ionizing Dose Radiation

Dynamic Degradation of Planar-Gate SiC MOSFETs After Total Ionizing Dose Radiation

Comparison Investigations on the Total Ionizing Dose Radiation of 4H-SiC MOS Structure Prepared With Different Nitrogen Annealing

Comparison Investigations on the Total Ionizing Dose Radiation of 4H-SiC MOS Structure Prepared With Different Nitrogen Annealing

Single event transient of SOI FinFET with total ionizing dose irradiation

Total ionizing dose (TID) irradiation impacts the device leakage currents or threshold voltage, which affects the single event transient (SET) vulnerability of electronics under radiation environment. SET response of SOI FinFET at 14 nm technology node after TID exposure is carried out at different dose level. Results show that the drain current peak presents a slight fluctuant with total dose, while the collected charge and the bipolar amplification coefficient first decrease with total dose and then increase. The potential reason is also discussed from competing mechanisms associated with decreasing threshold voltage from TID irradiation and increasing the drain diffuse current from the potential of the channel.

ОЦІНКА СУЧАСНИХ ФАКТОРІВ РАДІАЦІЙНО-АСОЦІЙОВАНОГО КАНЦЕРОГЕНЕЗУ

The widespread introduction of nuclear technologies in industry, medicine, science, etc. increases the number of professionals subjected to additional radiation exposure. Moreover, the problem of occupational cancer is the most complicated in occupational pathology due to the multifactorial nature of the etiology of this disease. The radiation accidents in Chornobyl and Fukushima-1 showed that nuclear reactors cannot guarantee absolutely safe operation. At present, the threat of nuclear terrorism is increasing. Occupational radiation exposure and its consequences are also of great concern worldwide. Based on the literature data and our own studies on the effects of various types of radiation exposure, especially stochastic effects of radiation, it seems reasonable to develop a scientific basis for the optimization of radiation protection of various categories of population, first of all, medical personnel and patients. The complex assessment of radiation risks and reconstruction of the total ionizing radiation dose from all types of irradiation will allow optimizing radiation protection of the population and reducing carcinogenic risk..

SOI FinFET Design Optimization for Radiation Hardening and Performance Enhancement

This work proposes Total Ionizing Dose (TID) hardening techniques compatible with conventional 14-nm-node silicon-on-insulator (SOI) FinFETsf process flows through performing 3-dimensional (3-D) simulations based on technology computer-aided design (TCAD) tools. The simulation results reveal a significantly critical TID impact induced by trapped charges in the buried oxide (BOX) and the spacer with calibration against 14 nm SOI FinFETfs experimental data (error < 6%). Inspired by the physical interpretation, an optimization technique featuring an optimized gate structure, spacer length, and substrate bias is designed. The optimized gate structure is utilized to enhance the local gate-to-channel coupling at the bottom and reduce the generation and capture of electron-hole pairs. By reducing the spacer length, a lower sensitive volume in the spacer can effectively suppress the TID response. The setting of the negative substrate bias greatly improves the subthreshold characteristics, weakening the TID effect in the BOX. By adopting the combined optimization including these techniques, the threshold voltage shift (VTH) induced by a 5 Mrad(SiO2) irradiation can be reduced to 21 mV, whereas VTH is 45 mV with only gate structure optimized and 97 mV without hardening. Meanwhile, the ION/IOFF after radiation increases to 1 × 107, which is at least four orders of magnitude better than the original device. Meanwhile, subthreshold swing (SS) is reduced from 81 mV/dec to 71 mV/dec, and Drain Induced Barrier Lowering (DIBL) is reduced from 120 mV/V to 99 mV/V, respectively. The combined optimization design is demonstrated as an effective method to improve the tolerance against TID irradiation without compromising performance, promoting 14 nm SOI FinFET’s application in future harsh space environments.

Aspect Ratio Modeling of Radiation-Hardened 8-Shape Enclosed Layout Transistor

The leakage current caused by the total ionizing dose (TID) effect remains a challenge for deep submicron technologies. The enclosed layout transistor (ELT) NMOS using the radiation hardening by design (RHBD) technique has a great potential for TID radiation hardening. Compared with the b-shape ELT that has a clear limitation on its aspect ratio, 8-shape ELT is preferable in the circuit design. The aspect ratio modeling of 8-shape ELT is proposed in this work for the first time. The basic principle is based on the 8-shape ELT equivalent circuit, composing one main transistor and two edge transistors. In accordance with the Sentaurus simulation result, the equivalent trapezium approximation is made for the edge transistor. A semi-empirical parameter is given to calculate the proposed model. The model is verified by the comparison between measured results of the fabricated 8-shape ELT in 180nm CMOS process and the pure calculation results. A further discussion is made to improve the accuracy of the proposed model, which is approved by the comparison between different models in previous work. Some modifications are also made to adjust the 8-shape ELT before the application.

Temperature and total ionizing dose effects of SiC MOSFET and their synergistic characteristics

In light of the extreme environmental conditions of temperature and radiation faced by silicon carbide Metal–Oxide-Semiconductor Field-Effect Transistor (SiC MOSFETs) in aerospace electronic systems, the damage characteristics induced by high-temperature stress and Total Ionizing Dose (TID) radiation were compared. Moreover, the synergistic effect of temperature stress and TID on the performance of SiC MOSFETs was studied. The impact of temperature stress and radiation on threshold voltage and static power current is consistent; However, the degradation trend of on-resistance is opposite. The research shows that after temperature stress removal, the change in device performance parameters can be recovered. The total ionizing dose radiation can cause permanent damage to the device; In the environment of temperature stress and radiation, the increase of temperature can weaken or restrain part of radiation damage.

Low-Frequency and Random Telegraph Noise in 14-nm Bulk Si Charge-Trap Transistors

Effects of programming/erasing (P/E) and total-ionizing dose (TID) are investigated on 2-and 40-fin charge-trap transistors (CTTs) fabricated in a 14-nm bulk-Si CMOS technology. Significant random telegraph noise (RTN) is observed in as-processed CTTs, especially for 2-fin devices. Trapped charge in programed devices does not significantly affect 1/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{f}$</tex-math> </inline-formula> noise magnitudes, but P/E leads to trap activation/deactivation, causing changes in border-trap energy and spatial distributions. TID irradiation activates a large number of stable radiation-induced traps.

Total-Ionizing-Dose Effects and Low-Frequency Noise in N-Type Carbon Nanotube Field-Effect Transistors With HfO₂ Gate Dielectrics

Total ionizing dose (TID) irradiation and low-frequency noise characterization are performed on carbon nanotube field-effect transistors (CNTFETs). Large hysteresis due to high border-trap densities is observed in as-processed and irradiated devices. TID irradiation also leads to significant radiation-induced charge trapping in the surrounding dielectrics resulting in parametric degradation. Percolation-path switching, and border traps contribute to low-frequency noise, with a relatively more prominent role for border traps after irradiation than before irradiation. These results show that process improvements are required to optimize both the initial operating characteristics and the radiation response of CNTFETs.

Total-ionizing dose irradiation induced degradation behavior and mechanism of the Cascode GaN HEMTs

In this article, the effects of total ionizing dose (TID) irradiation and the annealing treatment on the degradation of the commercial Cascode GaN high-electron-mobility transistors (HEMTs) were investigated, and low frequency noise method (LFN) was carried out to analyze the defects. The DC characteristics show that the device after TID irradiation with different doses exhibits a negative drift of threshold voltage (V th) and a remarkable increase of drain-source current (I ds) with respect to the fresh one. Meanwhile, with increasing doses of the TID irradiation, the off-state drain leakage current increases, while the drain-source resistance decreases. The gate-lag characteristic gets better for the Cascode GaN HEMTs after TID irradiation. The transfer characteristics, output characteristics, blocking characteristics and capacitance characteristics of the devices can partly be restored by annealing treatment, but there is no pronounced influence on the gate-lag characteristics and drain-source resistance. The trap density extracted by the LFN method decreases in the Cascode GaN HEMTs after TID irradiation. The degradation behavior and mechanism of the Cascode GaN HEMTs under TID irradiation are analyzed. The experimental results may provide a useful reference for the design and space application of the Cascode GaN HEMTs.

Study of the Within-Batch TID Response Variability on Silicon-Based VDMOS Devices

Silicon-based vertical double-diffused MOSFET (VDMOS) devices are important components of the power system of spacecraft. However, VDMOS is sensitive to the total ionizing dose (TID) effect and may have TID response variability. The within-batch TID response variability on silicon-based VDMOS devices is studied by the 60Co gamma-ray irradiation experiment in this paper. The variations in device parameters after irradiation is obtained, and the damage mechanism is revealed. Experimental results show that the standard deviations of threshold voltage, subthreshold swing, output capacitance, and diode forward voltage increase, while the standard deviation of maximum transconductance decreases after irradiation. The standard deviation of on-state resistance is basically unchanged before and after irradiation. By separating the trapped charges generated by TID irradiation, it is found that the deviation of the oxide trapped charges and the interface traps increase with the increase in the total dose. The reasons for the variation in device parameters after irradiation are revealed by establishing the relationship between the trapped charges and the electrical parameters before and after irradiation.

Effect of Trapped Charge Induced by Total Ionizing Dose Radiation on the Top-Gate Carbon Nanotube Field Effect Transistors

The excellent performance and radiation-hardness potential of carbon nanotube (CNT) field effect transistors (CNTFETs) have attracted wide attention. However, top-gate structure CNTFETs, which are often used to make high-performance devices, have not been studied enough. In this paper, the total ionizing dose (TID) effect of the top-gate structure CNTFETs and the influence of the substrate on top-gate during irradiation are studied. The parameter degradation caused by the irradiation- and radiation-damage mechanisms of the top-gate P-type CNTFET were obtained by performing a Co-60 γ-ray irradiation test. The results indicate that the transfer curves of the top-gate P-type CNTFETs shift negatively, the threshold voltage and the transconductance decrease when TID increases, and the subthreshold swing decreases first and then increases with the increase in TID. The back-gate transistor is constructed by using the substrate as a back-gate, and the influence of back-gate bias on the characteristics of the top-gate transistor is tested. We also test the influence of TID irradiation on the characteristics of back-gate transistors, and reveal the effect of trapped charge introduced by radiation on the characteristics of top-gate transistors. In addition, the CNTFETs that we used have obvious hysteresis characteristics. After irradiation, the radiation-induced trapped charges generated in oxide and the OH groups generated by ionization of the CNT adsorbates aggravate the hysteresis characteristics of CNTFET, and the hysteresis window increases with the increase in TID.

Total ionizing dose radiation hardening technology based on double-charge multiple-step ion implantation

This paper describes the total ionizing dose (TID) radiation hardening of buried oxide in separation by implantation of oxygen silicon on insulator (SOI) substrates. In this study, 0.5-μm partially depleted SOI complementary metal–oxide–semiconductor (CMOS) transistors and circuits were prepared using double-charge multiple-step ion implantation and annealing, and the changes in the drive current, leakage current, and threshold voltage of the CMOS transistor under different TID radiation conditions were compared. Under a TID of 500 k Rad(Si), radiation-hardened H-type N-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <100 mV in the worst case, and H-type P-channel metal–oxide–semiconductor transistors had a threshold voltage drift of <150 mV. Under a TID of 1 Mrad(Si), CMOS transistors showed no significant increase in leakage current caused by TID radiation. Under a TID of 500 k Rad(Si), the standby current of the radiation-hardened 32-bit DSP was <1.5 mA. The high-density integrated circuits prepared using this technology performed well under harsh ionizing radiation environments. Finally, this technology was compared with similar foreign technologies and TID-unhardened wafers with hardened wafers. This technology reached the international advanced level among equivalent technologies regarding hole capture cross section and maximum threshold voltage drift in the model. PACS85.30.De 85.30.-e.

A simulation result of trapped charge in PPD CIS induced by total ionizing dose effect

This paper describes a method for simulating the total ionizing dose (TID) radiation effect of a PPD CMOS image sensor (CIS) using TCAD. This paper takes the CIS pixel unit as the research object, modeling the device structure and combining it with a gamma radiation model to simulate the distribution of radiation-induced charge generation rate, electron concentration, and potential at each interface in the entire region before and after irradiation with TID equal to 5, 20, 50, 80, 100, 200, and 300 krad(Si). At the same time, the curves of the above parameters changed with the increase of TID radiation have been simulated. Furthermore, the influence of different TIDs on the parameters mentioned above at each interface has been investigated based on the two main damage mechanisms of the TID radiation effect: radiation-induced oxide trapped charge and radiation-induced interface trapped charge. It was also discovered that as the TID increases, the depletion region of the pinned photodiode (PPD) becomes broader, causing the dark current to increase.

Study of bias-induced total ionizing dose radiation damage mechanism in SiC MOSFETs

γ-ray irradiation experiments are conducted at different biases to investigate the differences in total ionizing dose damage of SiC MOSFET by the I-V and Split C-V curves. Combined with TCAD simulation, it is found that the total ionizing dose effect at different biases can generate positive charges at different locations in the oxide. For gate and motor-drive bias, the charges are uniformly located in the SiO2 layer, causing a negative shift of the C-V and I-V curves. For drain bias, charges are mainly in the JFET oxide due to the inhomogeneous distribution of the electric field in the oxide, resulting in a change in the shape of the C-V curve. The results further deepen our understanding of the radiation damage mechanism of SiC power MOSFETs.

Analog performance of the CROCv1 pixel readout chip for the CMS Phase-2 Tracker Upgrade

The CROCv1 front-end (FE) chip was designed by the RD53 collaboration for the CMS Phase-2 Inner Tracker Upgrade. It is designed to cope with the extreme radiation and hit rates of the HL-LHC and it is based on the 65 nm CMOS technology and a novel analog FE design featuring linear charge to Time-over-Threshold conversion. In this contribution, the characterization measurements of the analog part of the chip are presented with a special focus on the linear analog FE, including Total Ionizing Dose radiation damage studies.

Bias Dependence of Total Ionizing Dose Response in UTBB FD-SOI Transistors

The impact of continuous bias on the ultra-thin body and buried oxide fully-depleted silicon-on-insulator (UTBB FD-SOI) transistors during total ionizing dose (TID) irradiation is investigated by a device with the single transistor or multiple transistors in parallel. Experimental data of the single transistor shows that the TID bias effect is masked by TID response variation caused by process fluctuation between devices. While the device with multiple transistors in parallel still exhibits a similar TID bias effect as the traditional SOI transistor (TG > OFF > Ground > ON), the process fluctuations between devices are well controlled. Focusing on UTBB FD-SOI parallel transistors, by comparing the results of various bias conditions, the impacts of the drain, gate, and back-gate bias on the TID response of transistors are summarized in detail. Particularly, applying both positive and negative back-gate bias to transistors during TID radiation can obviously increase the TID damage of UTBB FD-SOI parallel transistors, which should be considered in the TID mitigation technique through dynamic back-gate bias. Combined with TCAD simulation, the generation process of oxide-trapped charges in buried oxide (BOX) under different biases is discussed. And, bias dependence of TID response is analyzed from three aspects: fraction of holes escaping initial recombination, holes capture cross section, and spatial distribution of oxide trapped charges. Finally, the TID mitigation calibration law of pMOSFETs is investigated by the empirical model of the back-gate radiation bias effect.

High-dose X-ray radiation induced MgO degradation and breakdown in spin transfer torque magnetic tunnel junctions

Magnetic tunnel junction (MTJ) with magnesium oxide (MgO) tunnel barrier is the core element of spin transfer torque-based magnetic random access memory. For the application in the space environment, the total ionizing dose radiation effects on MTJs need to be evaluated. In this work, the MTJs were exposed to X-ray radiation with different doses of up to 10 Mrad(Si). Measurements of current induced magnetization switching (CIMS) behavior of these MTJs were performed before and after radiation. The results show negligible changes in the tunneling magnetoresistance and current switching properties after 8 Mrad(Si) X-ray radiation. However, with a total dose of 9 Mrad(Si), a significant reduction in junction resistance of a fairly large number of MTJs was observed, which showed characteristics of MTJ breakdown. Moreover, in this study, all experimental MTJs became functionally disabled due to MgO breakdown under 10 Mrad(Si) X-ray radiation. The CoFeB/MgO/CoFeB interface microstructure was observed using X-ray photoelectron spectroscopy and high-resolution transmission electron microscopy (HRTEM). Interfacial structural results indicate that the MgO degradation and breakdown behavior caused by X-ray ionizing radiation can give rise to radiation-induced oxygen vacancies across the tunnel barrier oxide layer.

Study of TID radiation effects on the breakdown voltage of buried P-pillar SOI LDMOSFETs with P-top region

This article presents the numerical investigation on the total ionizing dose (TID) radiation induced breakdown voltage shifting behavior of the silicon-on-insulator (SOI) buried P-pillar (BP) lateral double-diffused metal-oxide semiconductor (LDMOS) with a P-top region (TP). We validate the employed simulation models and structure parameters by the experiments of the 200 V rated SOI BP-LDMOS devices. We also discuss the breakdown voltage (BV) analysis of the SOI BPTP-LDMOS under different doping concentrations in the drift region. Because the lateral breakdown voltage can be effectively enhanced by the P-top region under STI layer, the SOI BPTP-LDMOS behaves a wider Nd window for rated 200 V compared with the SOI BP-LDMOS. Finally, we perform the numerical investigation of the TID radiation effect on the BV shift. Using the TID hardening design with the electric field modulation method, the hardened BPTP-LDMOS can achieve a significant improvement in the TID tolerance compared with the hardened SOI BP-LDMOS, from 575 to 775 krad(Si).