Torque Magnetic Random Access Memory Research Articles

A Dual-Domain Dynamic Reference Sensing for Reliable Read Operation in SOT-MRAM

Although spin orbit torque magnetic random access memory (SOT-MRAM) is one of the strong candidates for next-generation embedded memories, the degradation of read margin due to low tunnel magnetoresistance ratio (TMR) with process variations has been a large concern. In this paper, we present the dual-domain dynamic reference (DDDR) sensing scheme, where the reference voltage can be dynamically changed based on the combined voltage and time domain sensing to increase the sensing margin. The Half Schmitt trigger and sample & hold circuits are efficiently employed to generate data-dependent reference voltages and to store the sampled voltage levels at different times, respectively. According to the simulations using 28nm CMOS technology with 128 by 128 SOT-MRAM array, the proposed DDDR approach achieves a 243mV of sensing margin under 6.08E-8 bit-error-rate (BER) at 1.76ns, which is 2X larger margin with more than 100 times lower BER compared to the conventional read scheme. When scaling down the pre-charge voltage, the proposed scheme achieves more than 50% of the read energy savings under 1E-5 target BER condition.

Field-Free Deterministic Writing of Spin-Orbit Torque Magnetic Tunneling Junction by Unipolar Current

We propose a field-free magnetic switching method in a perpendicular spin-orbit torque magnetic tunneling junction on a 200 mm wafer. The field-free switching can be achieved by unipolar current pulses via engineering the interlayer exchange coupling in the thin ferromagnetic films. The proposed device can reach a high writing speed of up to 1 ns and work properly at temperature of 100°C. This novel unipolar switching scheme offers an alternative writing approach for spin-orbit torque magnetic random access memory.

Fabrication and Individual Addressing of STT-MRAM Bit Array With 50 nm Full Pitch

Spin-transfer torque (STT) magnetic random access memory (MRAM) is gaining commercial traction in low-density embedded and standalone memories, but the available market opportunities would grow exponentially if STT-MRAM could approach dynamic random access memory (DRAM) bit density. Of course, achieving DRAM density will require, among other things, demonstrating the ability to pattern MRAM bits at an extremely tight pitch. Here, an experimental demonstration of fabrication and electrical testing of a STT-MRAM bit array are reported. By optimizing the hard mask and ion beam etching (IBE) processes, MRAM bit arrays with a full pitch down to 50 nm are fabricated, in which the bits are individually tested using a novel bottom-point-contact method.

In-Memory Computing Architecture for a Convolutional Neural Network Based on Spin Orbit Torque MRAM

Recently, numerous studies have investigated computing in-memory (CIM) architectures for neural networks to overcome memory bottlenecks. Because of its low delay, high energy efficiency, and low volatility, spin-orbit torque magnetic random access memory (SOT-MRAM) has received substantial attention. However, previous studies used calculation circuits to support complex calculations, leading to substantial energy consumption. Therefore, our research proposes a new CIM architecture with small peripheral circuits; this architecture achieved higher performance relative to other CIM architectures when processing convolution neural networks (CNNs). We included a distributed arithmetic (DA) algorithm to improve the efficiency of the CIM calculation method by reducing the excessive read/write times and execution steps of CIM-based CNN calculation circuits. Furthermore, our method also uses SOT-MRAM to increase the calculation speed and reduce power consumption. Compared with CIM-based CNN arithmetic circuits in previous studies, our method can achieve shorter clock periods and reduce read times by up to 43.3% without the need for additional circuits.

Giant Extrinsic Spin Hall Effect in Platinum-Titanium Oxide Nanocomposite Films.

Although the spin Hall effect provides a pathway for efficient and fast current‐induced manipulation of magnetization, application of spin–orbit torque magnetic random access memory with low power dissipation is still limited to spin Hall materials with low spin Hall angles or very high resistivities. This work reports a group of spin Hall materials, Pt1 −x (TiO2) x nanocomposites, that combines a giant spin Hall effect with a low resistivity. The spin Hall angle of Pt1 −x (TiO2) x in an yttrium iron garnet/Pt1 −x (TiO2) x double‐layer heterostructure is estimated from a combination of ferromagnetic resonance, spin pumping, and inverse spin Hall experiments. A giant spin Hall angle 1.607 ± 0.04 is obtained in a Pt0.94(TiO2)0.06 nanocomposite film, which is an increase by an order of magnitude compared with 0.051 ± 0.002 in pure Pt thin film under the same conditions. The great enhancement of spin Hall angle is attributed to strong side‐jump induced by TiO2 impurities. These findings provide a new nanocomposite spin Hall material combining a giant spin Hall angle, low resistivity and excellent process compatibility with semiconductors for developing highly efficiency current‐induced magnetization switching memory devices and logic devices.

Area and Energy Efficient Joint 2T SOT-MRAM-Based on Diffusion Region Sharing With Adjacent Cells

In this brief, we present a novel low area joint 2T spin orbit torque magnetic random access memory (SOT-MRAM) cell architecture. The proposed joint 2T cell achieves up to 15 % of SOT-MRAM cell area reduction by sharing the diffusion regions of transistors between adjacent cells. In addition, the small bit-line capacitance of the proposed SOT-MRAM can lead to 27% read energy reduction in comparison to the conventional SOT-MRAM. When the proposed 1 MB SOT-MRAM is used as L2 cache of X86 processor, the gem5 simulation results show the average of 18% dynamic energy savings in various workloads of SPEC2006 benchmarks.

Perspectives on spintronics technology development: Giant magnetoresistance to spin transfer torque magnetic random access memory

The discovery of the giant magnetoresistance (GMR) effect in 1988 started a new field called spintronics and was recognized with the 2007 Nobel Prize in Physics, which was awarded to Fert and Grunberg. Spintronics is based on the contribution of both electron spin and electron charges of materials to facilitate electronic functions, enabling one extra degree of freedom for device operations. Spintronics has grown rapidly during the past three decades with significant discoveries, technological advancements, and material and device developments that have led to numerous product applications. Furthermore, new research fields and technology areas have been discovered and continue to expand. In this Perspective, key technological advances in the field during the past three decades will be highlighted, starting with the developments that led to the first use of the GMR effect in hard disk drives and its impact in the spintronic ecosystem to currently used perpendicular magnetic tunnel junctions (pMTJs) for spin transfer torque magnetic random access memory (STT-MRAM) devices. The important aspects of the pMTJ characteristics for the application of STT-MRAM will be discussed. This Perspective will present perspectives on a new structure that enhances the efficiency of the pMTJ-based STT-MRAM and research directions that can drive further advances in spintronics.

Influence of ferromagnetic layer thickness on the Gilbert damping and magnetocrystalline anisotropy in PLD grown epitaxial Co2FeSi Heusler alloy thin films

In the present work, full Heusler alloy (FHA) Co2FeSi (CFS) epitaxial thin films with thickness (tCFS) ranging from 5–25 nm were grown by Pulse laser deposition (PLD) on MgO (001) substrates at an optimized deposition temperature of 600°C. Dynamic magnetization response of PLD-grown CFS thin films was systematically investigated as a function of tCFS. Thickness-dependent structural and magnetic correlation exhibit a non-monotonic variation in Gilbert damping parameter, α. The ferromagnetic resonance (FMR) investigation revealed that the presence of lattice strain and a lower degree of atomic ordering in the thinner FHA CFS films, results in additional enhancement of α. The lowest α value of 4×10−3 is obtained from the theoretical fit of experimental data in a 20 nm thick film. This low value of α is suitable in magnonic devices, such as spin-transfer torque magnetic random-access memories (STT-MRAMs) where an efficient spin injecting source from a FHA ferromagnet to a non-magnetic interface is required. Further, in-plane angle-dependent (φ-variation) FMR measurements of the sample yield an intrinsic four-fold magnetocrystalline anisotropy (MCA) along with the presence of uniaxial anisotropy that has non-monotonicity with tCFS. A significant value of cubic anisotropy constant of 5.16×105erg/cm3 has been obtained in the film with a thickness of around 15nm. Further investigation suggests that uniaxial anisotropy in the CFS/MgO film is a combination of strain-induced magneto-elastic and interface-related contribution that is intrinsic in nature. The experimental observations have been verified by using micromagnetic simulations run on the epitaxial crystal structure. FMR mode position and linewidth of varied thickness CFS films are generated by micromagnetic simulations utilizing the Landau–Lifshitz–Gilbert formalism.

A novel dual-reference sensing scheme for computing in memory within STT-MRAM

With the rapid development of the Internet of Things and artificial intelligence, it is more and more difficult for the existing hardware structure to process billions of data. In conventional Von-Neumann architectures, the well-known “memory wall” becomes a critical barrier to limit bandwidth. In order to solve this problem, computing in memory (CIM) within STT-MRAM (Spin Transfer Torque Magnetic Random Access Memory) emerges gradually. However, CIM requires multiple memory units in parallel, resulting in higher reading error rate. In this paper, a novel dual-reference sensing scheme (NDRS) is proposed for hybrid CMOS/MTJ logic circuits. By exploiting novel precharge scheme and adding inverter to amplify signals, NDRS scheme can improve CIM reliability significantly. Under the 40 nm technology node and a physics-based MTJ compact model, 1000 times Monte Carlo simulation shows that AND logic operation error rate is ∼7.42% and OR logic operation error rate is ∼2.67%.

Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation

It is questionable whether DRAM will continue to scale and will meet the needs of next-generation systems. Therefore, significant effort is invested in research and development of novel memory technologies. One of the candidates for next-generation memory is Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). STT-MRAM is an emerging non-volatile memory with a lot of potential that could be exploited for various requirements of different computing systems. Being a novel technology, STT-MRAM devices are already approaching DRAM in terms of capacity, frequency, and device size. Although STT-MRAM technology got significant attention of various major memory manufacturers, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing and current parameters of this novel technology, which are required to perform a reliable main memory simulation on performance and power estimation. This study demonstrates an approach to perform a cycle accurate simulation of STT-MRAM main memory, being the first to release detailed timing and current parameters of this technology from academia—essentially enabling researchers to conduct reliable system-level simulation of STT-MRAM using widely accepted existing simulation infrastructure. The results show a fairly narrow overall performance deviation in response to significant variations in key timing parameters, and the power consumption experiments identify the key power component that is mostly affected with STT-MRAM.

Process-Induced Magnetic Tunnel Junction Damage and its Recovery for the Development of Spin-Orbit Torque Magnetic Random Access Memory

Process-Induced Magnetic Tunnel Junction Damage and its Recovery for the Development of Spin-Orbit Torque Magnetic Random Access Memory

Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches

Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising emerging memory technology for on-chip caches. It has a low read access time and low leakage power. Unfortunately, however, STT-MRAM suffers from its long write latency and high write energy consumption. This paper proposes a cache management technique called Proactive Invalidation (PROI) that proactively invalidates dead blocks in advance to enable fast writes in the STT-MRAM caches. Experimental evaluation shows that the proposed technique improves performance by 14% on average compared to the baseline STT-MRAM cache. This paper also proposes two optimization techniques called Proactive Invalidation-aware Data Encoding (PIDE) and Narrowness-aware Partial Write (NPW) to minimize the energy overheads of Proactive Invalidation. Experimental results demonstrate that the total energy consumption of the STT-MRAM cache with PROI is only 1.8% higher than the baseline when PROI is applied with PIDE and NPW.

A Novel Workload-Aware and Optimized Write Cycles in NVRAM

With the emergence of the Internet of things (IoT), embedded systems have now changed its dimensionality and it is applied in various domains such as healthcare, home automation and mainly Industry 4.0. These Embedded IoT devices are mostly battery-driven. It has been analyzed that usage of Dynamic Random-Access Memory (DRAM) centered core memory is considered the most significant source of high energy utility in Embedded IoT devices. For achieving the low power consumption in these devices, Non-volatile memory (NVM) devices such as Parameter Random Access Memory (PRAM) and Spin-Transfer Torque Magnetic Random-Access Memory (STT-RAM) are becoming popular among main memory alternatives in embedded IoT devices because of their features such as high thickness, byte addressability, high scalability and low power intake. Additionally, Non-volatile Random-Access Memory (NVRAM) is widely adopted to save the data in the embedded IoT devices. NVM, flash memories have a limited lifetime, so it is mandatory to adopt intelligent optimization in managing the NVRAM-based embedded devices using an intelligent controller while considering the endurance issue. To address this challenge, the paper proposes a powerful, lightweight machine learning-based workload-adaptive write schemes of the NVRAM, which can increase the lifetime and reduce the energy consumption of the processors. The proposed system consists of three phases like Workload Characterization, Intelligent Compression and Memory Allocators. These phases are used for distributing the write-cycles to NVRAM, following the energy-time consumption and number of data bytes. The extensive experimentations are carried out using the IoMT (Internet of Medical things) benchmark in which the different endurance factors such as application delay, energy and write-time factors were evaluated and compared with the different existing algorithms.

Embedded Memories for Cryogenic Applications

The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

Phase-change-assisted spin-transfer torque switching in perpendicular magnetic tunnel junctions

Magnetic anisotropy modulation is an effective method to simultaneously reduce the switching current and extend the data retention of magnetic tunnel junction (MTJ), which is promising to be used in the next-generation spin transfer torque (STT) magnetic random-access memory. However, to meet the requirements of high storage life and harsh environments, the improved perpendicular magnetic anisotropy of MTJ makes the conventional modulation methods suffer from high breakdown risk owing to the relatively low efficiency. In this paper, a method of phase-change controlled magnetic anisotropy (PCMA) is introduced to a physical model of VO2/CoFeB/MgO/CoFeB perpendicular MTJ with superior modulation capability proved by systematical simulation. The time sequence of phase change pulse and STT pulse is studied, proving that there exists a specific interval to achieve both rapid and low-power switching. With the joint effect of PCMA and STT, low-energy (68.2 fJ), low-error-rate (0.08), and fast (2 ns) write operation can be achieved in the MTJ accompanied by a high thermal stability factor (78). The results demonstrate that the PCMA-STT switching strategy is most suitable for MTJ with large perpendicular magnetic anisotropy, paving a promising way to replace NOR flash memories.

Etching damage induced performance degradation in spin transfer torque magnetic random access memory fabrication

Damage mechanisms and related performance degradations induced by ion beam etching (IBE) process in the fabrication of magnetic tunnel junctions (MTJs) were studied systematically. The loss in tunneling magnetoresistance (TMR) and coercive field (Hc) was investigated with different MTJ pillar sizes and IBE incident angles. It is found that IBE-induced damage is the formation of a surficial amorphous shell in the outer rim of an MTJ pillar. This amorphous shell is of low conductivity and TMR, mainly arising from the lattice damage of MgO barrier and partial oxidation of free/reference layers. Based on experimental and theoretical findings, we optimized the IBE process to reduce the damage as well as recover from degradation. As a result, the TMR loss ratio in comparison with a blanket film is reduced from about 18% to 7%, and Hc is increased from 1490 to 2280 Oe for the same stack.

Spin-Torque-Triggered Magnetization Reversal in Magnetic Tunnel Junctions with Perpendicular Shape Anisotropy

The concept of perpendicular shape anisotropy spin-transfer torque magnetic random-access memory (PSA-STT-MRAM) consists in increasing the storage layer thickness to values comparable to the cell diameter, to induce a perpendicular shape anisotropy in the magnetic storage layer. Making use of that contribution, the downsize scalability of the STT-MRAM may be extended towards sub-20 nm technological nodes, thanks to a reinforcement of the thermal stability factor $\Delta$. Although the larger storage layer thickness improves $\Delta$, it is expected to negatively impact the writing current and switching time. Hence, optimization of the cell dimensions (diameter, thickness) is of utmost importance for attaining a sufficiently high $\Delta$ while keeping a moderate writing current. Micromagnetic simulations were carried out for different pillar thicknesses of fixed lateral size 20 nm. The switching time and the reversal mechanism were analysed as a function of the applied voltage and aspect-ratio (AR) of the storage layer. For AR $<$ 1, the magnetization reversal resembles a macrospin-like mechanism, while for AR $>$ 1 a non-coherent reversal is observed, characterized by the nucleation of a transverse domain wall at the ferromagnet/insulator interface which then propagates along the vertical axis of the pillar. It was further observed that the inverse of the switching time is linearly dependent on the applied voltage. This study was extended to sub-20 nm width with a value of $\Delta$ around 80. It was observed that the voltage necessary to reverse the magnetic layer increases as the lateral size is reduced, accompanied with a transition from macrospin-reversal to a buckling-like reversal at high aspect-ratios.

Low-Energy Picosecond Magnetic Switching for Synthetic Ferrimagnetic Free Layer Utilizing the Electric-Field-Tuned RKKY Effect

The processional switching mechanism governs magnetic switching in magnetic tunnel junctions (MTJs) in the sub-nanosecond range, which limits the application of spin transfer torque magnetic random access memory (STT-MRAM) in the ultrafast region. In this paper, we propose a new picosecond magnetic switching mechanism in a synthetic antiferromagnetic (SAF) structure using the adjustable Ruderman-Kittel-Kasuya-Yosida (RKKY) interaction controlled by an external electric field (E-field). It is shown that along with the sign change of the RKKY interaction in the SAF structure with an external E-field, the critical switching current density can be significantly reduced by one order of magnitude compared to that of a normal MTJ design at 100 ps; thus, this novel STT-MRAM can be written with a very low switching current density to avoid the MTJ breakdown problem and reduce the writing energy. To understand the physical origin of this abnormal phenomenon, a toy model is proposed in which the external-E-field-controlled sign change of the RKKY interaction in the SAF structure provides an extra contribution to the total energy that helps thespins overcome the energy barrier and break the processional switching mechanism.

Towards Enhanced System Efficiency while Mitigating Row Hammer

In recent years, DRAM-based main memories have become susceptible to the Row Hammer (RH) problem, which causes bits to flip in a row without accessing them directly. Frequent activation of a row, called an aggressor row , causes its adjacent rows’ ( victim ) bits to flip. The state-of-the-art solution is to refresh the victim rows explicitly to prevent bit flipping. There have been several proposals made to detect RH attacks. These include both probabilistic as well as deterministic counter-based methods. The technique of handling RH attacks, however, remains the same. In this work, we propose an efficient technique for handling the RH problem. We show that the mechanism is agnostic of the detection mechanism. Our RH handling technique omits the necessity of refreshing the victim rows. Instead, we use a small non-volatile Spin-Transfer Torque Magnetic Random Access Memory (STTRAM) that ensures no unnecessary refreshes of the victim rows on the DRAM device and thus allowing more time for normal applications in the same DRAM device. Our model relies on the migration of the aggressor rows. This accounts for removing blocking of the DRAM operations due to the refreshing of victim rows incurred in the previous solution. After extensive evaluation, we found that, compared to the conventional RH mitigation techniques, our model minimizes the blocking time of the memory that is imposed due to explicit refreshing by an average of 80.72% in the worst-case scenario and provides energy savings of about 15.82% on average, across different types of RH-based workloads. A lookup table is necessary to pinpoint the location of a particular row, which, when combined with the STTMRAM, limits the storage overhead to 0.39% of a 2 GB DRAM. Our proposed model prevents repeated refreshing of the same victim rows in different refreshing windows on the DRAM device and leads to an efficient RH handling technique.

DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect

As device integration density increases exponentially as predicted by Moore’s law, power consumption becomes a bottleneck for system scaling where leakage power of on-chip cache occupies a large fraction of the total power budget. Spin transfer torque magnetic random access memory (STT-MRAM) is a promising candidate to replace static random access memory (SRAM) as an on-chip last level cache (LLC) due to its ultralow leakage power, high integration density, and nonvolatility. Moreover, with the prevalence of edge computing and Internet-of-Things (IoT) applications, it can be beneficial to build a total nonvolatile cache hierarchy, including the L1 cache. However, building an L1 cache with STT-MRAM still faces severe challenges particularly because reducing its relatively high write latency by increasing write voltage can accelerate oxide breakdown of the MTJ device and threaten the L1 cache lifetime significantly due to intensive accesses. In our previous work, we proposed a dynamic overwriting voltage adjustment (DOVA) technique to deal with this challenge. In this article, we improve this technique by a DOVA promotion (DOVA PRO) technique for the STT-MRAM L1 cache, considering the cache write endurance and performance simultaneously. A high write voltage is used for performance-critical cache lines, while a low write voltage is used for other cache lines to approach an optimal tradeoff between reliability and performance. Experimental results show that the proposed technique DOVA PRO can improve cache performance by 23.5%, on average, compared to the DOVA technique. In the meantime, the average degradation of cache lifetime remains almost unchanged compared with the DOVA technique on average. Furthermore, DOVA PRO can support flexible configurations to achieve various optimization targets, such as higher performance or a longer lifetime.