Top Silicon Layer Research Articles

High temperature and frequency pressure sensor based on silicon-on-insulator layers

Based on silicon on insulator (SOI) technology, a novel high temperature pressure sensor with high frequency response is designed and fabricated, in which a buried silicon dioxide layer in the silicon material is developed by the separation by implantation of oxygen (SIMOX) technology. This layer can isolate leak currents between the top silicon layer for the detecting circuit and body silicon at a temperature of about 200 °C. In addition, the technology of silicon and glass bonding is used to create a package of the sensor without internal strain. A structural model and test data from the sensor are presented. The experimental results showed that this kind of sensor possesses good static performance in a high temperature environment and high frequency dynamic characteristics, which may satisfy the pressure measurement demands of the oil industry, aviation and space, and so on.

Carrier Accumulation in Silicon-On-Insulator Structures Containing Ge Nanocrystals in the Burried SiO<sub>2</sub> Layer

Electro-physical properties of metal-oxide-silicon (MOS) structures and MOS transistors, prepared in the top silicon layer of silicon-on-insulator (SOI) structures containing Ge nanocrystals in the buried SiO2 layers, have been studied. It was obtained that carrier accumulation in MOS structures depend on the direction of built-in electrical field in MOS structures. Accumulation of the excess negative charges in the case of p-channel transistors is associated with electron trapping on Ge nanocrystals synthesized in the buried dielectric. In the case of n-channel transistor, positive charge related to the Si/SiO2 interface or to the charged oxide is accumulated. The Ge atoms diffused to the SiO2/Si interface can stimulate the formation of the excess positive charge.

Сavity Effect in Hydrogen Ion Implanted Silicon-On-Insulator Structures

Cavity effect on the room-temperature (RT) photoluminescence (PL) from emitting centers in the top silicon layer of silicon-on-insulator (SOI) structure has been studied. The lightemitting centers were produced by the implantation of H+ ions and subsequent annealing at the temperatures Ta = 450-1000 oC for 5 h in an Ar ambient under pressure P = 1 - 1.2×104 bar. It has been obtained that annealing under hydrostatic pressure higher than 6 kbar prevented the outdiffusion of hydrogen in the form of gas bubbles, which took place after annealing at Ta≥600 oC under atmospheric conditions. Absence of micro-pores and gas bubbles in the top surface region creates the conditions to retain the mirror quality of the SOI/air interface. A wavelength-selective effect of the formed cavity on visible PL has been observed from the H+ ion implanted SOI structures annealed under pressure of 12 kbar. The cavity enhancement of PL emission for 23-40 times has been found at the wavelength of 515 and 560 nm.

Fabrication of strained silicon on insulator by strain transfer process

The fabrication of ultrathin strained silicon layer directly on insulator is demonstrated. 50nm strained silicon on insulator layers were fabricated by a method which includes four steps: Epitaxial growth of strained SiGe on ultrathin silicon on insulator (SOI) substrates, ion implantation, postannealing process, and etch-back process. Strain of the layer was observed by Raman spectroscopy. 0.72% tensile strain was maintained in the strained silicon layer even after removing the SiGe film. The strained layer was the result of strain equalization and transfer process between the SiGe film and top silicon layer.

Characterization of stress induced in SOS and Si/γ-Al 2O 3/Si heteroepitaxial thin films by Raman spectroscopy

Raman spectroscopy technique has been performed to investigate the stress induced in as-grown silicon-on-sapphire (SOS), solid-phase-epitaxy (SPE) re-grown SOS, and Si/γ-Al 2O 3/Si double-heteroepitaxial thin films. It was demonstrated that the residual stress in SOS film, arising from mismatch and difference of thermal expansion coefficient between silicon and sapphire, was reduced efficiently by SPE process, and that the stress in Si/γ-Al 2O 3/Si thin film is much smaller than that of as-grown SOS and SPE upgraded SOS films. The stress decrease for double heteroepitaxial film Si/γ-Al 2O 3/Si mainly arises from the smaller lattice mismatching of 2.4% between silicon top layer and the γ-Al 2O 3/Si epitaxial composite substrate, comparing with the large lattice mismatch of 13% for SOS films. It indicated that γ-Al 2O 3/Si as a silicon-based epitaxial substrate benefits for reducing the residual stress for further growth of silicon layer, compared with on bulk sapphire substrate.

Electron Field Emission from SiC/Si Heterostructures Formed by Carbon Implantation into Silicon and Etching of the Top Silicon Layer

AbstractHigh intensity electron field emissions were obtained from SiC/Si heterostructures formed by high temperature carbon implantation into silicon and subsequently etching of the top silicon layer. Implantation processes were performed at 700 °C with a dose of 3.0 to 8.0 x 1017 ions/cm2. Post-implantation annealing in argon at 1250 °C for 5h was done for partial samples. β-SiC precipitates were easily formed and embedded in silicon at the interface of SiC/Si heterostructures during high temperature carbon implantation for all samples. The densely distributed small protrusions led to efficient electron emission. Implantation dose scarcely impacted the electron emission characteristics when it reached to a definite value. After annealing, the density of protrusions at the interface of SiC/Si heterostructures became smaller since β-SiC precipitates were grown into larger sizes, which caused to a relatively inefficient electron emission.

Surface roughness in XeF2 etching of a-Si∕c-Si(100)

Single wavelength ellipsometry and atomic force microscopy (AFM) have been applied in a well-calibrated beam-etching experiment to characterize the dynamics of surface roughening induced by chemical etching of a ∼12nm amorphous silicon (a-Si) top layer and the underlying crystalline silicon (c-Si) bulk. In both the initial and final phase of etching, where either only a-Si or only c-Si is exposed to the XeF2 flux, we observe a similar evolution of the surface roughness as a function of the XeF2 dose proportional to D(XeF2)β with β≈0.2. In the transition region from the pure amorphous to the pure crystalline silicon layer, we observe a strong anomalous increase of the surface roughness proportional to D(XeF2)β with β≈1.5. Not only the growth rate of the roughness increases sharply in this phase, also the surface morphology temporarily changes to a structure that suggests a cusplike shape. Both features suggest that the remaining a-Si patches on the surface act effectively as a capping layer which causes the growth of deep trenches in the c-Si. The ellipsometry data on the roughness are corroborated by the AFM results, by equating the thickness of the rough layer to 6σ, with σ the root-mean-square variation of the AFM’s distribution function of height differences. In the AFM data, the anomalous behavior is reflected in a too small value of σ which again suggests narrow and deep surface features that cannot be tracked by the AFM tip. The final phase morphology is characterized by an effective increase in surface area by a factor of two, as derived from a simple bilayer model of the reaction layer, using the experimental etch rate as input. We obtain a local reaction layer thickness of 1.5 monolayer consistent with the 1.7ML value of Lo et al. [Lo et al., Phys. Rev. B 47, 648 (1993)] that is also independent of surface roughness.

Characterization of a high-density plasma immersion ion implanter with scaleable ECR large-area plasma source

A key issue for future high-performance CMOS techniques is the fabrication of 12 in. or larger silicon-on-insulator (SOI) wafers with thickness of the top silicon layer under 25 nm. The electron cyclotron resonance (ECR) plasma ion immersion implanters (ECR-PIII) are viable candidates to realize the above. We designed an ECR-PIII in which we integrated the new concept of a large-area plasma source. This new plasma source is an array of elementary ECR plasma sources created by an assembly of m linear microwave sources. Each linear microwave source has n radiating elements ( n> m) and includes a system of permanent magnets that create magnetic induction for ECR to occur in the processing chamber. An array of 90 elementary ECR plasma sources generate highly homogeneous dense plasma with dimensions permitting processing of 12-in. wafers. Since hydrogen implantation requiring high dose often results in blistering of the wafer surface, a new Smart-Cut™-like technology has been suggested (US Patent 6,352,909) where the one-step hydrogen implantation is replaced by a two-step process. The designed ECR-PIII can offer substantial advantage in providing the high yield of protons used for the micro-bubble formation in the two-step process.

Near-band edge light emission from silicon semiconductor on insulator diodes

Light-emitting diodes have been designed and fabricated on commercial crystalline silicon semiconductor on insulator wafers. Strong infrared light emission has been observed from these diodes under forward bias conditions with an external quantum efficiency of 2×10−6. The band edge phonon-assisted photoluminescence from the top single-crystalline silicon layer is responsible for such emission with a spectrum peaked at 1.135μm wavelength. Due to negligible reabsorption of spontaneously emitted photons within the extremely thin silicon layer, the short wavelength emission is significantly stronger in relative terms compared to emission from bulk-silicon light-emitting devices.

Buried tungsten silicide layer in silicon on insulator substrate by Smart-Cut®

A single-crystalline Si/SiO2/poly-WSix/Sub-Si structure has been successfully fabricated by a new method incorporating a standard smart-cut® technique and a high temperature reaction between tungsten and silicon. Annealing at 800–1100 °C does not only strengthen the bonding of the wafers but also induces solid phase reaction of deposited tungsten and silicon. A poly-crystalline WSix (1 < x < 2) layer with a tetragonal structure is formed below the buried oxide layer. Cross section images of TEM show three steep interfaces of the four layers. It is found that increasing the annealing temperature is in favour of decreasing the sheet resistance of tungsten silicide and improving the crystal quality of the top silicon layer. However, a spreading resistance profile measurement shows that annealing under high temperature (⩾1000 °C) will induce diffusion of tungsten into the Si substrate which is confirmed by the EDX results and the reason is presented.

Implant damage and redistribution of indium in indium-implanted thin silicon-on-insulator

The indium implant damage and diffusion behavior in thin silicon-on-insulator (SOI) with a 200 nm top silicon layer were studied for different implantation energies and doses. Rutherford backscattering spectrometry in the channeling mode (RBS/C) was used to characterize the implant damage before and after annealing. Secondary ion mass spectrometry (SIMS) was used to study the indium transient enhanced diffusion (TED) behavior in the top Si layer of the SOI structure. An anomalous redistribution of indium after relatively high energy (200 keV) and dose (1 × 10 14 cm −2) implantation was observed in both bulk Si and SOI substrates. However, there exist differences in these two substrates that are attributable to the more predominant out-diffusion of indium as well as the influence of the buried oxide layer in the SOI structure.

Effects of buried oxide layer on indium diffusion in separation by implantation of oxygen

The diffusion of indium in both the top silicon and the buried oxide (BOX) layers in separation by implantation of oxygen (SIMOX) is investigated. For all indium-implanted samples, there is a significant redistribution of indium atoms from the top Si-BOX interface toward the bottom BOX-Si interface, thereby affecting the indium concentrations in the two silicon-BOX interfaces. In the case of relatively high-dose and high-energy indium implantation (1×1014cm−2 at 200keV), an anomalous segregation of indium is observed in both the bulk Si and the SIMOX substrates. However, there is a notable transportation of indium atoms from the top Si layer toward the bottom BOX-Si interface in the SIMOX, thereby affecting not only the indium concentrations in the two silicon-BOX interfaces but also the indium distribution in the top silicon layer. The unique indium-diffusion behavior in the SIMOX is believed to be a composite effect of indium trapping by the two Si-BOX interfaces, indium atoms being drawn away from the top silicon layer by the buried oxide, as well as implant damages in the top silicon. The asymmetrical structure of the BOX layer with Si islands accumulating at the bottom BOX-Si interface and the abundance of oxygen-related defects in the BOX layer are also believed to be responsible for the indium-diffusion behavior in the BOX layer.

Vertically-coupled micro-resonators realized usingthree-dimensional sculpting in silicon

A modified separation by implantation of oxygen process has been developed to sculpt vertically coupled microdisk resonators in silicon. The approach involves the implantation of oxygen ions into a silicon substrate, patterned with thermal oxide, to define waveguides on the bottom silicon layer, and photolithography and reactive ion etching to define the microdisk resonators on the top silicon layer. The top and the bottom silicon layers are separated by the oxide layer that was formed after the oxygen implantation. Fabricated microdisk resonators show resonances with a Q value of 10 300 and a free spectral range of 5.4nm.

Transfer of Single Crystalline Silicon Nanolayer Onto Alien Substrate

Starting from the 60-nm node, future generations of mainstream semiconductor devices (i.e., CMOS) will be mostly manufactured from silicon-on-insulator (SOI) initial substrates with the top silicon layer having a thickness 50 nm or less. We describe a process that is capable for transfer of nanoscale thick layers. The layer is delaminated from a single crystalline silicon substrate and laminated onto another substrate, thus resulting in SOI. The process includes: 1) forming a trap layer for hydrogen in an initial substrate; 2) delivery of hydrogen to the traps by diffusion of monatomic hydrogen; 3) evolving the trapped hydrogen into a layer of hydrogen platelets; 4) stiffening of the surface of the initial substrate by laminating to another substrate; and 5) delaminating a layer from the initial substrate along the hydrogen platelet layer. Details of the new layer transfer process are described. A depth where the buried trap layer locates is critical for the process. An implantation of heavy ions is used to form the trap layer. A trap capacity for hydrogen is evaluated as a function of implantation conditions. Plasma hydrogenation is used to deliver atomic hydrogen to the traps. Electron cyclotron resonance, microwave, RF, and dc plasma are compared as the hydrogenation sources. Dependence of a thickness of a transferred layer as a function of the mass of implanted ions and implantation energy is described. Types of layer transfer faults are also described. Mechanisms of the layer transfer faults are suggested. We discuss limits of scaling down of the thickness of the layer that is transferred from one substrate to another. The scaling limit of our process is compared to the limits of other (SIMOX, Smart-Cut, and ELTRAN) processes.

DLTS study of silicon-on-insulator structures irradiated with electrons or high-energy ions

Results of deep-level transient spectroscopy (DLTS) study of radiation defects in silicon layers, Si/SiO/sub 2/ interface traps, and a charge in buried oxide formed under irradiation with 2.0 MeV electrons (10/sup 5/-10/sup 6/ rad.) or 245 MeV Kr (2.2/spl times/10/sup 8/ cm/sup -2/ and 1.4/spl times/10/sup 9/ cm/sup -2/) ions in silicon-on-insulator (SOI) structures are presented and discussed. SOI was fabricated by the wafer bonding and hydrogen cutting. It was found that electron irradiation leads to transformation of energy spectrum of the interface traps (relaxation of the bonded interface) in SOI. The main effect of high-energy Kr ion irradiation consists in formation of radiation defects in the top silicon layer as well as in the substrate. The fixed positive charge is introduced in the buried oxide under irradiation in both cases.

A novel back-shooting inkjet printhead using trench-filling and SOI wafer

A novel thermal inkjet printhead with monolithically fabricated nickel nozzle plate on SOI wafer has been proposed for the first time. A chamber and a restrictor are implemented on the 40 μm thick top silicon layer, and a nozzle plate covering heater layers is monolithically fabricated on them. Unlike the general back-shooters, the inkjet printhead reported here is a kind of back-shooter, which has a chamber and a restrictor with arbitrary shape by utilizing the silicon dioxide etch-stop layers in the bottom and sidewalls of chamber. Moreover, the electroplating process for nozzle, followed by placing the chamber underneath the heater layer, is performed on a planar surface, resulting in more uniform and reliable control of nozzle size. The new design was applied for monochrome inkjet printhead, which has 56 nozzles in two columns with real 600 NPI (nozzle per inch), and showed good performances such as a drop velocity of 12 m/s, a drop volume of 30 pl, and a maximum firing frequency of 12 kHz for single nozzle ejection. From nozzle by nozzle inspection, we observed the uniformity variation of less than 4% in drop speed as well as drop volume. The monolithic fabrication process resulted in a good uniformity and is expected to have superior manufacturing yield to the nozzle assembly process.

Fabrication of thick, high-quality strained SiGe layer on ultra-thin silicon-on-insulator and modeling of film strain

Fabrication of a thick strained SiGe layer on bulk silicon is hampered by the lattice mismatch and difference in the thermal expansion coefficients between Si and SiGe, and a high Ge content leads to severe strain in the SiGe film. When the thickness of the SiGe film is above a critical value (90 nm for 18% Ge), drastic deterioration of the film properties as well as dislocations will result. In comparison, a silicon-on-insulator (SOI) substrate with a thin top Si layer can mitigate the problems and so a thick SiGe layer with high Ge concentration can conceivably be synthesized. In the work reported here, a 110 nm thick high-quality strained Si 0.82Ge 0.18 layer was fabricated on an ultra-thin SOI substrate with a 30 nm top silicon layer using ultra-high vacuum chemical vapor deposition (UHVCVD). The thickness of the SiGe layer is larger than the critical thickness on bulk Si. Cross-sectional transmission electron microscopy (XTEM) reveals that the SiGe layer is dislocation-free and the atoms at the SiGe/Si interface are well aligned, even though X-ray diffraction (XRD) data indicate that the SiGe film is highly strained. The strain factors determined from the XRD and Raman results agree well.

Comparison of Electrical Properties of Silicon-on-Insulator Structures Fabricated with Use of Hydrogen Slicing and BESOI

The top silicon layers and the bonded Si/SiO 2 interfaces in silicon-on-insulator (SOI) structures fabricated by (i) wafer bonding and hydrogen slicing, and (ii) by wafer bonding and chemical mechanical thinning (back-etch SOI, BESOI) were investigated and compared by charge deep-level transient spectroscopy. The hydrogen slicing was provided by hydrogen implantation into one of the bonded wafers and led to the high hydrogen concentration during SOI fabrication. Hydrogen presented in SOI during the fabrication process partially neutralizes the traps at the Si/thermal SiO 2 interface, and completely neutralizes shallow acceptors and contamination with deep levels in the top silicon layer.

Electrical characterization of silicon-on-insulator structures with a nondamaging elastic–metal gate

This article explores electrical characterization methods for silicon-on-insulator (SOI) structures with a nondamaging elastic metal gate (EM gate). Important material electrical properties related to the top silicon layer, gate dielectric and interfaces, and buried oxide are addressed. The techniques utilized are currently under development for SOI and are based on EM-gate capacitance–voltage methods, current–voltage methods, and a back channel metal–oxide–semiconductor transistor that utilizes elastic probes to form a temporary source and drain.

Doping and Mobility Profiles in Defect-Engineered Ultra-shallow Junctions: Bulk and SOI

ABSTRACTSilicon on insulator (SOI - Smartcut®) wafers were implanted with 1MeV and 300keV silicon ions to doses of 3.8x1015 cm−2 and 3x1014 cm−2, respectively, in order to modify the vacancy concentration in a controlled way. Boron was then implanted at 2keV to a dose of 1×1015 cm−2 into the near-surface part of the vacancy-engineered region. Atomic profiles were determined using SIMS and electrical profiles were measured using a novel Differential Hall Effect (DHE) technique, which enables profiling of electrically active dopants with a nanometer depth resolution. The electrical profiles provide pairs of carrier concentration and mobility values as a function of depth. The buried oxide (BOX) is proven to restrict the back diffusing interstitials positioned below the BOX from entering the silicon top layer and interacting with the boron profile. Also an increase of ∼50% in boron activation is achieved when a co-implant is used. However, SOI shows a reduced degree of activation when compared to bulk silicon, with or without a co-implant.