Top-gated MoS2 Research Articles

Single-crystalline metal-oxide dielectrics for top-gate 2D transistors.

Two-dimensional (2D) structures composed of atomically thin materials with high carrier mobility have been studied as candidates for future transistors1-4. However, owing to the unavailability of suitable high-quality dielectrics, 2D field-effect transistors (FETs) cannot attain the full theoretical potential and advantages despite their superior physical and electrical properties3,5,6. Here we demonstrate the fabrication of atomically thin single-crystalline Al2O3 (c-Al2O3) as a high-quality top-gate dielectric in 2D FETs. By using intercalative oxidation techniques, a stable, stoichiometric and atomically thin c-Al2O3 layer with a thickness of 1.25 nm is formed on the single-crystalline Al surface at room temperature. Owing to the favourable crystalline structure and well-defined interfaces, the gate leakage current, interface state density and dielectric strength of c-Al2O3 meet the International Roadmap for Devices and Systems requirements3,5,7. Through a one-step transfer process consisting of the source, drain, dielectric materials and gate, we achieve top-gate MoS2 FETs characterized by a steep subthreshold swing of 61 mV dec-1, high on/off current ratio of 108 and very small hysteresis of 10 mV. This technique and material demonstrate the possibility of producing high-quality single-crystalline oxides suitable for integration into fully scalable advanced 2D FETs, including negative capacitance transistors and spin transistors.

Wafer-scale high-κ dielectrics for two-dimensional circuits via van der Waals integration

The practical application of two-dimensional (2D) semiconductors for high-performance electronics requires the integration with large-scale and high-quality dielectrics—which however have been challenging to deposit to date, owing to their dangling-bonds-free surface. Here, we report a dry dielectric integration strategy that enables the transfer of wafer-scale and high-κ dielectrics on top of 2D semiconductors. By utilizing an ultra-thin buffer layer, sub-3 nm thin Al2O3 or HfO2 dielectrics could be pre-deposited and then mechanically dry-transferred on top of MoS2 monolayers. The transferred ultra-thin dielectric film could retain wafer-scale flatness and uniformity without any cracks, demonstrating a capacitance up to 2.8 μF/cm2, equivalent oxide thickness down to 1.2 nm, and leakage currents of ~10−7 A/cm2. The fabricated top-gate MoS2 transistors showed intrinsic properties without doping effects, exhibiting on-off ratios of ~107, subthreshold swing down to 68 mV/dec, and lowest interface states of 7.6×109 cm−2 eV−1. We also show that the scalable top-gate arrays can be used to construct functional logic gates. Our study provides a feasible route towards the vdW integration of high-κ dielectric films using an industry-compatible ALD process with well-controlled thickness, uniformity and scalability.

A Monolayer MoS2 FET with an EOT of 1.1nm Achieved by the Direct Formation of a High-κ Er2 O3 Insulator Through Thermal Evaporation.

Achieving the direct growth of an ultrathin gate insulator with high uniformity and high quality on monolayer transition metal dichalcogenides (TMDCs) remains a challenge due to the chemically inert surface of TMDCs. Although the main solution for this challenge is utilizing buffer layers before oxide is deposited on the atomic layer, this method drastically degrades the total capacitance of the gate stack. In this work, weconstructed a novel direct high-κ Er2 O3 deposition system based on thermal evaporation in a differential-pressure-type chamber. A uniform Er2 O3 layer with an equivalent oxide thickness of 1.1nm wasachieved as the gate insulator for top-gated MoS2 field-effect transistors (FETs). The top gate Er2 O3 insulator without the buffer layer on MoS2 exhibited a high dielectric constant that reached 18.0, which is comparable to that of bulk Er2 O3 and is the highest among thin insulators (< 10nm) on TMDCs to date. Furthermore, the Er2 O3 /MoS2 interface (Dit ≈ 6 × 1011 cm-2 eV-1 ) is confirmed to be clean and is comparable with that of the h-BN/MoS2 heterostructure. These results prove that high-quality dielectric properties with retained interface quality can be achieved by this novel deposition technique, facilitating the future development of 2D electronics.

Pass-Transistor Logic Circuits Based on Wafer-Scale 2D Semiconductors.

2D semiconductors, such as molybdenum disulfide (MoS2 ), have attracted tremendous attention in constructing advanced monolithic integrated circuits (ICs) for future flexible and energy-efficient electronics. However, the development of large-scale ICs based on 2D materials is still in its early stage, mainly due to the non-uniformity of the individual devices and little investigation of device and circuit-level optimization. Herein, a 4-inch high-quality monolayer MoS2 film is successfully synthesized, which is then used to fabricate top-gated (TG) MoS2 field-effect transistors with wafer-scale uniformity. Some basic circuits such as static random access memory and ring oscillators are examined. A pass-transistor logic configuration based on pseudo-NMOS is then employed to design more complex MoS2 logic circuits, which are successfully fabricated with proper logic functions tested. These preliminary integration efforts show the promising potential of wafer-scale 2D semiconductors for application in complex ICs.

Top-Gated MoS₂ Negative-Capacitance Transistors Fabricated by an Integral-Transfer of Pulsed Laser Deposited HfZrO₂ on Mica

Top-gated (TG) molybdenum disulfide (MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) field-effect transistors (FETs) suffer from surface damage, unintentional doping, and other defects introduced to the MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> channel during the direct deposition of the gate dielectric. In addition, the delicate MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> cannot withstand high-temperature processing or annealing. To overcome these obstacles, a novel path to prepare TG MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> negative-capacitance (NC) FETs is proposed in this study. A ferroelectric HfZrO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (HZO) is first deposited on the mica flake by pulsed laser deposition (PLD) and then annealed by rapid thermal processing. Subsequently, the HZO/mica stack is integrally transferred onto the MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> surface, without needing to expose the MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> flake to harsh temperatures or PLD environments. TG multilayered MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> NCFETs with the HZO/mica stack are fabricated and demonstrate stable NC effects and superior performance with a subthreshold swing (SS) of 49 mV/dec, ON/OFF current ratio above 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> , and anticlockwise hysteresis voltages of 64 mV, which are attributed to vital contributions from the damage-free mica/MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> van der Waals heterojunction interface and reasonable capacitance matching between the mica dielectric and the ferroelectric HZO film. Moreover, the experimental results of the dual-gate MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> transistor modulated by the bottom gate show that a positive bottom-gate bias can increase drain current and decrease hysteresis voltage, and a negative bottom-gate bias can reduce SS. Therefore, the proposed approach changes the current situation that the PLD method is hardly used to fabricate TG MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> transistors and opens a new window for nanoelectronics.

Comparison of Ionic Liquid and Ion-Gel Top-Gate MoS2 Field-Effect Transistors

Comparison of Ionic Liquid and Ion-Gel Top-Gate MoS₂ Field-Effect Transistors

MoS2 transistors gated by ferroelectric HfZrO2 with MoS2/mica heterojunction interface

Two-dimensional (2D) molybdenum disulfide (MoS2) field-effect transistor (FET) gated by negative capacitance (NC) is a promising architecture to overcome the thermionic limit and thus reduce device consumption. Here, top-gated MoS2 NCFETs have been prepared by transferring a mica flake on MoS2 channel to form a van der Waals heterojunction interface, together with a ferroelectric HfZrO2 (HZO) deposited on mica. Stable NC effects are demonstrated for MoS2 NCFETs. The MoS2 NCFETs integrated with mica/HZO gate stack provide competitive electrical characteristics when they are applied with a gate voltage sweep-width in the range of 1−3 V and a sweep-rate from 0.01 to 0.2 V s−1, including steep-slope of sub 60 mV dec−1 in four orders of magnitude of drain current, on/off current ratio over 106, and small hysteresis-width less than 50 mV. Outstanding performance should be ascribed to damage-free properties of mica/MoS2 van der Waals interface and capacitance matching between the HZO ferroelectric and mica dielectric. The results confirm the promising nature of mica/HZO gate stack and potential applications for future electronics.

Influence of Si-Substrate Concentration on Electrical Properties of Back- and Top-Gate MoS₂ Transistors

The effects of the Si-substrate doping concentration on electrical characteristics of back-gate (BG) and top-gate (TG) MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> field-effect transistors (FETs) are investigated. The experimental results show that MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs fabricated on different-concentration Si substrates using the same processing have similar interface characteristics and surface roughness of gate dielectric but exhibit different carrier mobility, and the higher the doping concentration, the higher the carrier mobility. This is because the carriers in Si substrate can screen the phonon scattering from the low-energy surface optical phonon produced by the soft Hf-O bonds in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> dielectric, which will couple with the carriers in MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> channel, resulting in the reduction of the mobility, and the higher the Si-substrate concentration, the better the screening effect. Also, it is found that the BG dielectric scattering will impact on the mobility of the TG transistor, which causes a similar change trend of carrier mobility to that of the BG MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FET as the Si-substrate concentration increases. Therefore, it can be revealed that the Si-substrate concentration has an important influence on the carrier mobility of MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs, and the high Si-substrate concentration is beneficial for fabricating high-performance BG and TG MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs.

Surface functionalization toward top-gated monolayer MoS2 field-effect transistors with ZrO2/Al2O3 as composite dielectrics

Growth of high-k dielectrics on two-dimensional (2D) materials is vital for the fabrication of electronic and optoelectronic devices. In this work, the uniform high-k ZrO2 dielectric thin films were successfully grown by atomic layer deposition (ALD) on monolayer MoS2 with Al2O3 buffer layers. No significant variations appear for MoS2 after deposition of Al and ZrO2 thin films. The properties of composite dielectrics on MoS2 films have been studied by Cr-Au/ZrO2/Al2O3/MoS2 Metal-oxide-semiconductor (MOS) devices, in which H2O and O3 were used as the oxidants for ZrO2 growth, respectively. Moreover, the top-gated monolayer MoS2 field-effect transistors (FETs) with ZrO2/Al2O3 as composite dielectrics have been successfully fabricated. Importantly, the top-gated structure gives the transistors with a high mobility of 11.14 cm2 V−1 s−1, a high on/off-state current ratio of 107 at VDS = 0.1 V, a small subthreshold swing of 0.93 V dec−1, and a proper threshold voltage of 2.29 V. Hence, the integration of the high-k dielectrics on MoS2 develops the possibilities to prepare high-performance top-gated FETs based on 2D materials.

Improved Electrical Properties of Top-Gate MoS2Transistor With NH3-Plasma Treated HfO2as Gate Dielectric

The effects of NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treating HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate dielectric on electrical characteristics of top-gate (TG) MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs are investigated. The experimental results show that the increase of off-state current after growing HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> top-gate dielectric can be considerably decreased by NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treating HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , because the N incorporation from the NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treatment can effectively eliminate the oxygen vacancies and reduce the positive oxide charges in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . The fabricated TG MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs with the NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treated HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as gate dielectric achieve excellent electrical performances: high on-off ratio of 2.1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> , high carrier mobility of 78~87 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vs and near-ideal subthreshold swing of 72mV/dec. Therefore, the NH <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> -plasma treated HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> as gate dielectric is highly beneficial for fabricating high-performance TG MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> FETs.

Improving the electrical performance of monolayer top-gated MoS2 transistors by post bis(trifluoromethane) sulfonamide treatment

Due to the large surface to volume ratio of two-dimensional (2D) materials, the electrical performance of MoS2 is very sensitive to extrinsic ambient conditions. Post treatments are favorable to improve or recover the electrical performance of MoS2. In this work, the influence of post forming gas annealing (FGA) and bis(trifluoromethane) sulfonamide (TFSI) treatment on the electrical performance of monolayer top-gated MoS2 transistors is investigated. A negative shift of threshold voltage and an improvement in electron mobility are observed for both the post FGA and TFSI treatment. However, post TFSI treatment is more effective than the post FGA treatment in improving the electron mobility and gate controllability. Linear transmission-line-model measurement results indicate that the post FGA treatment is preferable in reducing the contact resistance, while post TFSI treatment is more effective in reducing the sheet resistance of MoS2. Raman and x-ray photoelectron spectroscopy reveal that water desorbs from MoS2 after the FGA and TFSI treatment and S vacancies are introduced into MoS2 after FGA. The results show that post TFSI treatment can be a simple and effective approach to improve the electrical property of MoS2 and may be used for other S-containing 2D transition metal dichalcogenides.

Channel-protecting fabrication of top-gate MoS2 transistor arrays

The surface passivation on MoS2 and other transition metal dichalcogenides (TMDs) has been widely studied and utilized to prevent contamination and oxygen/water vapor penetration. Such approaches are mostly applied on the back-gate transistors after the formation of source/drain electrodes, while the compatibility in constructing top-gate devices has not yet been experimentally explored. Here, based on the large-area MoS2 thin film prepared with the atomic layer deposition technique, we developed an experimental routine to fabricate top-gate MoS2 thin-film transistor arrays with the TMD channel protected by high-k dielectric during the entire device fabrication process. The channel protection is enabled by the high-quality Al2O3 dielectric with proper pretreatment. The transistors in the array have shown enhanced electrical performance compared to the non-protected devices. Such a robust and well-controlled fabrication technique is a typical case of developing functional electronic devices by leveraging the strength of top-down lithography and the unique advantage of bottom-up growth, which can be further extended to the wide application in higher-level systems based on TMD materials.

Long-term stability of multilayer MoS2 transistors with mica gate dielectric

To avoid surface damage of a MoS2 channel, a mica flake with high permittivity and atomically flat surface was dry transferred onto a multilayer MoS2 flake to prepare top-gated transistors. For the first time, the interface properties of mica/MoS2 and the long-term stability of devices were investigated when the transistors were exposed to ambient air. Results show that the electrical performance of the transistors is degraded significantly when the devices are exposed to ambient moisture for a long time, due to the strong hydrophilism of mica. The transfer curves of the transistors cannot be recovered to their initial states even after annealing. The adsorbed moisture can become trapped at the interface between the MoS2 channel and mica dielectric or on the MoS2 surface, resulting in enhanced carrier scattering and degraded device performance. However, the top-gated MoS2 transistor with Al2O3 encapsulation exhibits enhanced stability even after annealing or exposure to atmosphere for 200 days. The excellent stability should be attributed to the effective insulation of moisture from the ambient air by Al2O3 encapsulation. Therefore, a dense and hydrophobic encapsulation layer is indispensable for stable and high-performance top-gated MoS2 transistors with mica gate dielectric.

Spin-resolved transport properties in molybdenum disulfide superlattice

The effects of the perpendicular magnetic field on the multi-barriers system of 5-barriers to 100-barriers are studied. Considering the low-energy Hamiltonian of the system with spin-orbit coupling we modulate the external magnetic field as the Zeeman energy on the orbital magnetic moment. The transport of an incident electron passing through the superlattice created by the top-gated monolayer MoS2 based on the transfer matrix method is investigated and the spin-up and the spin-down transmissions and the spin-polarization for 5-barriers to 100-barriers are obtained. Comparing the results show that in the case of 30-barriers, we have both reliable transmissions for the system and a 100% spin-polarization so that the spin-flip can occur and gives us a desired spintronic device. We also sketched the variations of the transmissions and spin-polarization versus the relative barrier-widths over the well-widths, (D/W), which show the optimum value is 1 by 2, respectively. Finally, we calculate the spin-up and spin-down conductance and total conductivity of the system which shows the so-called resonant tunneling peaks and amplifying the internal spin-orbit coupling with the external magnetic field as the Zeeman energy.

Quantum-mechanical effect in atomically thin MoS2 FET

Two-dimensional (2D) layered materials-based field-effect transistors (FETs) are promising for ultimate scaled electron device applications because of the improved electrostatics to atomically thin body thickness. However, compared with the typical thickness of ~5 nm for Si-on-insulator (SOI), the advantage of the ultimate thickness limit of monolayer for the device performance has not been fully proved yet, especially for the on-state at the accumulation region. Here, we present much stronger quantum-mechanical effect at the accumulation region based on the C–V analysis for top-gate MoS2 FETs. The self-consistent calculation elucidated that the electrons are confined in the monolayer thickness, unlike in the triangle potential formed by the electric field for SOI, the gate-channel capacitance is ideally maximized to the gate insulator capacitance since the capacitive contribution of the channel can be neglected due to the negligible channel thickness. This quantum-mechanical effect agreed well with the experimental results. Therefore, monolayer 2D channels are suggested to be used to enhance the on-current as well as the gate modulation ability.

Improved performance of top-gated multilayer MoS2 transistors with channel fully encapsulated by Al2O3 dielectric

Multilayer two-dimensional molybdenum disulfide (MoS2) field-effect transistors with Al2O3 or HfO2 as top gate dielectric and bottom passivation layer have been comparatively studied. The top-gated MoS2 transistor with Al2O3 as both top gate dielectric and bottom passivation layer exhibits excellent electrical characteristics with an on-off ratio of ∼106, a subthreshold swing of 97 mV dec−1, a low interface-trap density of 1.66×1012 cm−2eV−1, and a high field-effect mobility of 105 cm2 V−1 s−1. All these should be attributed to superior interface quality between Al2O3 top gate dielectric and MoS2, and enhanced dielectric screening effect due to Al2O3 bottom passivation layer.

End-Bonded Metal Contacts on WSe2 Field-Effect Transistors.

Contact engineering has been the central issue in the context of high-performance field-effect transistors (FETs) made of atomic thin transition metal dichalcogenides (TMDs). Conventional metal contacts on TMDs have been made on top via a lithography process, forming a top-bonded contact scheme with an appreciable contact barrier. To provide a more efficient pathway for charge injection, an end-bonded contact scheme has been proposed, in which covalent bonds are formed between the contact metal and channel edges. Yet, little efforts have been made to realize this contact configuration. Here, we bridge this gap and demonstrate seeded growth of end-bonded contact with different TMDs by means of chemical vapor deposition (CVD). Monolayer WSe2 FETs with a CVD-grown channel and end contacts exhibit improved performance metrics, including an on-current density of 30 μA/μm, a hole mobility of 90 cm2/V·s, and a subthreshold swing of 94 mV/dec, an order of magnitude superior than those of top-contact FET counterparts that share the same channel material. A fundamental NOT logic gate constructed using top-gated and end-bonded WSe2 and MoS2 FETs is also demonstrated. Calculations using density functional theory indicate that the superior device performance stems mainly from the stronger metal-TMD hybridization and substantial gap states in the end-contact configuration.

Damage-free mica/MoS2 interface for high-performance multilayer MoS2 field-effect transistors

For top-gated MoS2 field-effect transistors, damaging the MoS2 surface to the MoS2 channel are inevitable due to chemical bonding and/or high-energy metal atoms during the vacuum deposition of gate dielectric, thus leading to degradations of field-effect mobility (μFE) and subthreshold swing (SS). A top-gated MoS2 transistor is fabricated by directly transferring a 9 nm mica flake (as gate dielectric) onto the MoS2 surface without any chemical bonding, and exhibits excellent electrical properties with an on–off ratio of ∼108, a low threshold voltage of ∼0.2 V, a record μFE of 134 cm2 V−1 s−1, a small SS of 72 mV dec−1 and a low interface-state density of 8.8 × 1011 cm−2 eV−1, without relying on electrode-contact engineered and/or phase-engineered MoS2. Although the equivalent oxide thickness of the mica dielectric is in the sub-5 nm regime, enhanced stability characterized by normalized threshold voltage shift (1.2 × 10−2 V MV−1 cm−1) has also been demonstrated for the transistor after a gate-bias stressing at 4.4 MV cm−1 for 103 s. All these improvements should be ascribed to a damage-free MoS2 channel achieved by a dry transfer of gate dielectric and a clean and smooth surface of the mica flake, which greatly decreases the charged-impurity and interface-roughness scatterings. The proposed transistor with low threshold voltage and high stability is highly desirable for low-power electronic applications.

Fabrication of Top-Gate MoS2 FET with Transferred Al2O3 Gate Dielectric

This study describes the fabrication of top-gate molybdenum disulfide (MoS2) field-effect transistor (FET) using transfer printing of an Al2O3 gate dielectric. Semiconducting MoS2 has been considerable attention for applications as channel materials of FETs because a two-dimensional (2D) crystal is free from dangling bonds at the surface [1]. On the other hand, atomic layer deposition (ALD) of high-k gate dielectric is incompatible with MoS2 since an ALD precursor cannot be chemisorbed onto the surface of MoS2 due to the absence of dangling bonds [2]. Furthermore, ALD disrupts the surface structure and induces the oxidation of the channel layer [2], leading to the degradation of FET characteristics or the failure of devices. This study addresses these issues by utilizing the transfer printing of a high-k gate dielectric on a MoS2 layer [2], [3]. Transfer printing can avoid the deposition of a high-k gate dielectric directly on a fragile MoS2 surface. An abrupt and sharp interface can be anticipated by implementing the transfer printing of high-k gate dielectric.A key component for developing the transfer printing of the Al2O3 gate dielectric is to find out an appropriate sacrificial layer on the handling substrate. In this study, nickel (Ni) metal was adopted as the sacrificial layer for the transfer printing of the Al2O3 gate dielectric. It was revealed that the adhesion strength at Ni and thermally grown SiO2 interface is reduced by immersion in deionized water (DIW) [3]. The penetration of water into the interface results in the separation of Ni from the SiO2 surface. This Ni layer can be etched by using dilute nitric acid (HNO3). On the other hand, HNO3, which is an oxidizing agent, cannot etch an oxide gate dielectric.A 50-nm-thick Ni layer was deposited on the SiO2 (400 nm)/Si substrate by thermal evaporation (Fig. 1 (a)). The Al2O3 gate dielectric was deposited on the Ni layer by ALD with trimethylaluminum (TMA) and a H2O oxidant at a substrate temperature of 300 oC. Polymethyl methacrylate (PMMA) was prepared on Al2O3 by spin-coating as a protective layer. Next, a thermal release tape was attached to the PMMA layer. Then, the entire substrate was immersed in DIW for 5 min to weaken the adhesion strength between Ni and SiO2. The laminated structure was peeled off from the SiO2 surface in DIW. After the etching of Ni layer with dilute HNO3 (60% HNO3 : H2O = 1 : 10), the Al2O3 gate dielectric was transferred on MoS2 flakes. The Al2O3 gate dielectric and PMMA bilayer can be released from the thermal release tape by baking on a hot plate. After the removal of PMMA by oxygen plasma ashing, Al (40 nm) for the gate and Au (40 nm)/Ti (10 nm) for the source/drain were fabricated by the lift-off process. Finally, forming gas annealing (FGA) was performed in ambient (H2 : N2 = 3% : 97%) at 300 oC for 30 min to improve the electrical contacts at source/drain.The fabricated FET has small hysteresis, low leakage current, a subthreshold slope of 120 mV/dec, and a carrier mobility of 7.3 cm2/Vs (Fig. 1 (b)). The abrupt and sharp interface was demonstrated for transfer printing of the Al2O3 gate dielectric on the MoS2 channel layer. Process mismatches including temperature and chemical compatibility are avoidable by adopting the transfer printing method. The use of transferred high-k gate dielectrics is not restricted to MoS2 FETs. It is also applicable to various 2D layered materials. This study opens up the interesting direction for the research and development of 2D material-based functional devices. AcknowledgmentsThe authors would like to thank Professor Y. Kawano, Professor T. Hoshii, Professor I. Muneta, Professor K. Kakushima, Professor K. Tsutsui, and Professor H. Wakabayashi of Tokyo Institute of Technology for their continuous support in the experiments. This study was supported by JST CREST (Grant No. JPMJCR16F4) and a JSPS Grant-in-Aid for Young Scientists (B) (Grant No. 17K14662).

Ultrathin monolithic HfO2 formed by Hf-seeded atomic layer deposition on MoS2: Film characteristics and its transistor application

For the fabrication of high-performance top-gated MoS2 transistors, a uniform atomic layer deposition (ALD) of an ultrathin high-k gate dielectric film without abnormal leakage paths on a MoS2 channel is required. In this study, we fabricated a ~5.2 nm-thick monolithic HfO2 gate dielectric film by utilizing an e-beam-evaporated Hf seed layer (target thickness of 3 nm) prior to the ALD of a HfO2 film (~2 nm). The Hf seed layer was fully converted to HfO2 without metallic residues during the following ALD process, without damages to the Raman and photoluminescence characteristics of the underlying MoS2. The conformal and pinhole-free ALD of the subsequent HfO2 film was verified using conductive atomic force microscopy. In addition, operation of a top-gated MoS2 transistor was demonstrated by integrating the Hf-seeded HfO2 gate dielectric film.