Top-gated Graphene Research Articles

Sub-10 nm graphene nano-ribbon tunnel field-effect transistor

We report a temperature independent subthreshold slope (SS) of ∼47 mV/dec at low temperature in a triple top gate graphene tunnel field-effect transistor (TFET). The outer gates are used to define the p and n-doped regions of the ∼9.4 nm wide graphene nanoribbon, while the middle gate is used to switch the device between the ON and OFF states. Due to the flexibility of electrostatic doping, the device characteristics are compared in different configurations, specifically, field-effect transistor (FET) mode and TFET mode. A minimum SS of ∼47 mV/dec along with a saturation current density of ∼8.51 μA/μm is realized in the case of TFET mode at 5 K. This low SS is found to be temperature independent up to 40 K, after which an exponential increase is observed with a slope of 8.4 V/dec at 300 K. In clear contrast, linear temperature dependence of the SS is found in the case of FET mode.

Atomic-Layer-Deposition Growth of an Ultrathin HfO2 Film on Graphene.

Direct growth of an ultrathin gate dielectric layer with high uniformity and high quality on graphene remains a challenge for developing graphene-based transistors due to the chemically inert surface properties of graphene. Here, we develop a method to realize atomic-layer-deposition (ALD) growth of an ultrathin high-κ dielectric layer on graphene through premodifying the graphene surface using electron beam irradiation. An amorphous carbon layer induced by electron beam scanning is formed on graphene and then acts as seeds for ALD growth of high-κ dielectrics. A uniform HfO2 layer with an equivalent oxide thickness of 1.3 nm was grown as a gate dielectric for top-gate graphene field-effect transistors (FETs). The achieved gate capacitance is up to 2.63 μF/cm2, which is the highest gate capacitance on a graphene solid-state device to date. In addition, the fabricated top-gate graphene FETs present a high carrier mobility of up to 2500 cm2/(V·s) and a negligible gate leakage current of down to 0.1 mA/cm2, showing that the ALD-grown HfO2 dielectric layer is highly uniform and of very high quality.

Reprint of: Improvements on thermal stability of graphene and top gate graphene transistors by Ar annealing

Thermal annealing of graphene was studied to improve the thermal stability. During the annealing under an Ar atmosphere with temperature from 100 °C to 600 °C, graphene exhibits partial removal of PMMA residues, low density of defect cracks in SEM images and relatively low ID/IG ratios in Raman spectrum probing. For a top-gated graphene transistor with thermal annealing, it performs high carrier mobility up to 3500 cm2 V−1 s−1 and slightly asymmetric bipolar behaviours as well as slight Dirac point variation within ±0.2 V.

Carrier-Number-Fluctuation Induced Ultralow 1/f Noise Level in Top-Gated Graphene Field Effect Transistor.

A top-gated graphene FET with an ultralow 1/f noise level of 1.8 × 10-12 μm2Hz1- (f = 10 Hz) has been fabricated. The noise has the least value at Dirac point, it then increases fast when the current deviates from that at Dirac point, the noise slightly decreases at large current. The phenomenon can be understood by the carrier-number-fluctuation induced low frequency noise, which caused by the trapping-detrapping processes of the carriers. Further analysis suggests that the effect trap density depends on the location of Fermi level in graphene channel. The study has provided guidance for suppressing the 1/f noise in graphene-based applications.

A triboelectric charge top-gated graphene transistor

A graphene channel with polymer polymethyl methacrylate (PMMA) or Polydimethylsiloxane (PDMS) passive layer were fabricated on a Si/SiO2 substrate. The gate-effect of triboelectric charges on a foreign stimulator and in situ generated triboelectric charges on the passive layer are tested by controlling the foreign stimulator (PDMS or Acrylic plate) touch or not with the passive layer. When the negatively charged PDMS (positively charged Acrylic) stimulator approach and leave the device without touching the passive layer, the channel resistance shows a pulsed decrease (increase) with amplitude less than 1%. When the stimulator has a temporary touch with the passive layer, the in situ generated triboelectric charges on the PMMA (PDMS) passive layer cause stepwise increase (decrease) of the channel resistance. The amplitude of the resistance change steps of the device with PMMA passive layer (2μm in thickness) is about one order larger for than that of the device with PDMS passive layer (about 60μm in thickness). The significant different response of the device depending on whether the stimulator touches or not with the passive layer suggests two possible operation models for the tribo-charge top-gated graphene channel. It may enable diverse design of tactile sensors and pressure sensors based on the tribotronic effect.

Improvements on thermal stability of graphene and top gate graphene transistors by Ar annealing

Thermal annealing of graphene was studied to improve the thermal stability. During the annealing under an Ar atmosphere with temperature from 100 °C to 600 °C, graphene exhibits partial removal of PMMA residues, low density of defect cracks in SEM images and relatively low ID/IG ratios in Raman spectrum probing. For a top-gated graphene transistor with thermal annealing, it performs high carrier mobility up to 3500 cm2 V−1 s−1 and slightly asymmetric bipolar behaviours as well as slight Dirac point variation within ±0.2 V.

Top-gated graphene field-effect transistors by low-temperature synthesized SiNx insulator on SiC substrates

Top-gated devices made from an epitaxial graphene film on a 4H-SiC substrate were fabricated. Atomic force microscopy and Raman spectroscopy results showed that a large-scale highly uniform monolayer graphene film was synthesized on the SiC substrate. A SiNx passivation film was deposited on a SiC graphene device as a top gate insulator by catalytic chemical-vapor deposition (Cat-CVD) below 65 °C. After the top gate electrode was formed on the SiNx film, no leakage current flowed between the gate and source electrodes. The transport characteristics showed clear ambipolar characteristics from 8 to 280 K, and the temperature dependences of the conductance and field-effect mobility of the devices implied that monolayer graphene devices can be successfully fabricated. Moreover, the position of the charge neutrality point after SiNx deposition was around 0 V, indicating p-doping characteristics. These results indicate that SiNx films synthesized by Cat-CVD can be used as gate insulators and that the carrier type may be controlled by adjusting the deposition conditions.

Electrical Characteristics of Top-Gated Graphene Field Effect Transistors Fabricated on Stainless Steel (STS) Substrate.

Top-gated Graphene transistors with Al2O3 gate-dielectric on the flexible stainless steel substrate have been demonstrated. Graphene was synthesized on copper foil using a chemical vapor deposition method and transferred onto the stainless steel substrate by wet transfer technique. The stainless steel substrate was polished by chemical mechanical polishing method and the spin-on-glass layer was coated on the surface to improve the surface roughness. The average surface roughness R(a) was as low as 5.9 nm from the AFM measurement. The measured hole and electron mobilities from the current-voltage characteristics at room temperature were calculated as high as 310 and 45 cm2/Vs, respectively. In addition, the effect of surrounding temperature up to 355 K on the electrical variations was investigated. The mobility was inversely proportional to the temperature with negligible hysteresis where the temperature coefficient was calculated as low as -0.65 %/K.

Characterization and preliminary application of top-gated graphene ion-sensitive field effect transistors

Graphene, a 2-dimensional material, has received increasing attention due to its unique physicochemical properties (high surface area, excellent conductivity, and high mechanical strength). Field-effect transistor is shown to be a very promising candidate for electrically detecting chemical and biological species. Most of the reports on graphene field-effect transistors show that solution-gated graphene field effect transistors have been used so far. Although the traditional solution-gated graphene field effect transistor has high sensitivity, but the graphene channel is contaminated easily. The stability of the device is reduced so that the device cannot be reused. Only very recently, has the top-gated graphene, which is potentially used for pH sensors, been reported. In the top-gated graphene the dielectrics is deposited at the top of graphene. However, the sensitivity is lower than other sensors. To improve the properties, we design and fabricate a top-gated graphene ion-sensitive field effect transistor by using large-area graphene synthesized by chemical vapor deposition. At the top of graphene, HfO2/Al2O3 thin film is deposited by atomic layer deposition. The Al2O3 film plays a role of sensitive membrane, and the HfO2/Al2O3 thin film protects the graphene from contamination of the solution. After depositing the top-gate, because of the shield of the insulation, the boundary between the graphene and the substrate is not clear. And the Raman spectrum indicates the presence of a defective top layer accompanied by an increase in the Raman D peak. After a series of electrical characterizations, compared with solution-gated graphene field effect transistor which directly contacts the graphene channel with the solution, the top-gated graphene ion-sensitive field effect transistor has a high resistance. This increase relative to uncovered grapheme, is attributed to the participation of the top -orbitals in van der Waals bonds to the insulation. The graphene -orbitals contributing to van der Waals bonds have less overlaps and thus result in reduced conductivity. However the output curves and transfer curves show that the top-gated graphene ion-sensitive field effect transistor has higher signal-to-noise ratio and better stability. In view of the biochemical detection, in this paper we also examine the adsorption of single-stranded DNA. Silane functionalization of metal oxide system is a versatile technique that can be used in DNA microarray and nanotechnology. The DNA immobilization process we have developed contains several steps: silanization (APTES), crosslinker attachment (EDC and NHS), reaction with carboxyl-DNA and removal of non-covalently bound DNA. We characterize the process with carboxyl-quantum dots. We also measure the transfer curves before and after the adsorption of DNA, and demonstrate the effectiveness of the functionalized process and the feasibility that the top-gated graphene ion-sensitive field effect transistor is used as the biosensor.

Graphene field effect transistor-based terahertz modulator with small operating voltage and low insertion loss

In this work, we report a broadband terahertz wave modulator based on a top-gate graphene field effect transistor with polyimide as the gate dielectric on a PET substrate. The transmission of the terahertz wave is modulated by controlling the Fermi level of graphene via the polyimide as the top-gate dielectric material instead of the traditional dielectric materials. It is found that the terahertz modulator can achieve a modulation depth of ∼20.9% with a small operating gate voltage of 3.5 V and a low insertion loss of 2.1 dB.

Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

Probing the extended-state width of disorder-broadened Landau levels in epitaxial graphene

We experimentally investigate the width of extended states in disorder-broadened Landau levels (LLs) in top-gated epitaxial graphene on silicon carbide using two different methods: gated transport spectroscopy and activation gap measurements on integer quantum Hall states. The transport spectroscopy reveals that the widths of the extended states in the zero-energy ($N=0$) and first excited ($N=1$) LLs are of similar magnitude over the ranges of magnetic field (4--16 T) and temperature studied (1.6--150 K). Under certain assumptions we find that the extended-state width follows a power-law temperature dependence with the exponent $\ensuremath{\eta}\ensuremath{\sim}0.3$ in the $N=0$ ($N=1$) LL, with almost no (very weak) magnetic-field dependence. Activation gap measurements at the filling factors of $\ensuremath{\nu}=2$ and 6 give results consistent with transport spectroscopy for the $N=1$ LL, but indicate a larger broadening for the $N=0$ LL than deduced from the spectroscopy.

(Invited) Excellent Wetting Behavior of Yttria on 2D Materials

A high quality yttrium oxide (yttria, Y2O3) dielectric has been grown on different carbon derivatives materials (carbon nanotubes, exfoliated graphene, chemical vapor deposition graphene).1-5 This opens the possibility to use such dielectric for the fabrication of graphene devices.4-5 In this talk, the good wettability of Y2O3 on graphene is demonstrated using various surface science methods. Furthermore, the favorable wetting behavior of yttria is exploited as an effective seeding layer for atomic layer deposition of Al2O3 on graphene.6 Moreover, we investigated the interface between Y2O3 and the transition metal dichalcogenide MoS2 as well as on highly ordered pyrolytic graphite (HOPG). The growth of the yttria film was monitored in-situ by monochromatic X-ray photoelectron spectroscopy and scanning tunneling microscopy (XPS and STM). Depositing yttrium metal results in a chemical interaction between the adlayer and the substrate. However, no indication of chemical interaction was detected for the Y2O3 growth, formed by evaporating yttrium in background O2 environment. This is due to the initial formation of Y-O bonds, before the weak Y-MoS2 and Y-C interaction occurs. The STM results indicate the formation of a uniform dielectric film on both MoS2 and HOPG surfaces, confirming the previous findings on graphene. In conclusions, our results reveal that the underlying MoS2and graphene remains intact following yttria seed deposition. Photoemission measurements of the graphene/oxide contacts indicate n-type doping of graphene with different doping levels caused by the charge transfer at the interfaces. This work was supported in part by the Southwest Academy on Nanoelectronics sponsored by the Nanoelectronic Research Initiative. -- [1] R. Addou, A. Dahal, and M. Batzill Growth of a Two-Dimensional Dielectric Monolayer on Quasi-Freestanding Graphene. Nature Nanotechnol. 8, 41-45 (2013). [2] A. Dahal, H. Coy-Diaz H, R. Addou, J. Lallo, E. Sutter, and M. Batzill Preparation and Characterization of Ni(111)/Graphene/Y2O3(111) Heterostructures. J. Appl. Phys. 113, 194305 (2013). [3] A. Dahal, R. Addou, H. Coy-Diaz, J. Lallo, and M. Batzill. Charge Doping of Graphene in Metal/Graphene/Dielectric Sandwich Structure Evaluated by C-1s Core Level Photoemission Spectroscopy. APL Mater. 1, 042107 (2013). [4] H. Xu, Z. Zhang, Z. Wang, S. Wang, X. Liang, and L. M. Peng Quantum capacitance limited vertical scaling of graphene field- effect transistor. ACS Nano 5, 2340–2347 (2011). [5] H. Xu, Z. Zhang, H. Xu, Z. Wang, S. Wang, and L. M. Peng Top-gated graphene field-effect transistors with high normalized transconductance and designable Dirac point voltage. ACS Nano 5, 5031–5037 (2011). [6] A. Dahal, R. Addou, A. Azcatl, H. Coy-Diaz, N. Lu, X. Peng, F. de Dios, J. Kim, M. J. Kim, R. M. Wallace, and M. Batzill. Seeding Atomic Layer Deposition of Alumina on Graphene with Yttria. ACS Appl. Mater. Interfaces 7, 2082-2087 (2015).

Spin filter and spin valve in ferromagnetic graphene

We propose and demonstrate that a EuO-induced and top-gated graphene ferromagnetic junction can be simultaneously operated as a spin filter and a spin valve. We attribute such a remarkable result to a coexistence of a half-metal band and a common energy gap for opposite spins in ferromagnetic graphene. We show that both the spin filter and the spin valve can be effectively controlled by a back gate voltage, and they survive for practical metal contacts and finite temperature. Specifically, larger single spin currents and on-state currents can be reached with contacts with work functions similar to graphene, and the spin filter can operate at higher temperature than the spin valve.

Extraction of the Interface State Density of Top-Gate Graphene Field-Effect Transistors

Novel electrical measurement method, discharge current analysis (DCA), is introduced to extract the density and energy distribution of charge traps at the dielectric interface of top-gate graphene field-effect transistors. Using DCA method, the highest charge trap density <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 10^{13}$ </tex-math></inline-formula> (cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-2}\cdot $ </tex-math></inline-formula> eV <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{-1}$ </tex-math></inline-formula> ) is extracted at Fermi level <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 0.4$ </tex-math></inline-formula> eV. This is the first quantitative estimation of trap density at a specific Fermi level of graphene.

Graphene field effect devices operating in differential circuit configuration

We study the concept of a basic building block for circuits using differential signaling and being based on graphene field effect devices. We fabricated a number of top-gated graphene FETs using commercially available graphene and employing electron beam lithography along with other semiconductor manufacturing processes. These devices were then systematically measured in an automated setup and their DC characteristics analyzed in terms of a simple but effective analytical model. This model together with the collected data allowed us to proceed further with both mathematical analysis of circuit characteristics as well as numerical simulation in a dedicated circuit analysis software.

Hydroxyl-free buffered dielectric for graphene field-effect transistors

Deposition of high quality dielectrics onto graphene is of significant challenge because of the chemically inert surface of the two-dimensional carbon lattice which cannot provide nucleating sites for high-κ oxide insulators. Here we utilize an ultrathin hydroxyl-free organic film, the benzocyclobutene (BCB) polymer, as a buffer layer between graphene and high-κ dielectrics in top-gate graphene transistors. By electrical measurements and Raman spectra, it has been demonstrated that the BCB-buffered dielectric stack does not significantly impact the electrical characteristics and doping level of graphene channel, allowing for high carrier mobility to be maintained in top-gate operation. Moreover, the application of the hydroxyl-free buffered dielectrics could remarkably decrease the density of interface state, and then suppress the hysteresis in graphene transistors, which is desirable for high performance graphene electronics.

Graphene nanoribbon field-effect transistors on wafer-scale epitaxial graphene on SiC substrates

We report the realization of top-gated graphene nanoribbon field effect transistors (GNRFETs) of ∼10 nm width on large-area epitaxial graphene exhibiting the opening of a band gap of ∼0.14 eV. Contrary to prior observations of disordered transport and severe edge-roughness effects of graphene nanoribbons (GNRs), the experimental results presented here clearly show that the transport mechanism in carefully fabricated GNRFETs is conventional band-transport at room temperature and inter-band tunneling at low temperature. The entire space of temperature, size, and geometry dependent transport properties and electrostatics of the GNRFETs are explained by a conventional thermionic emission and tunneling current model. Our combined experimental and modeling work proves that carefully fabricated narrow GNRs behave as conventional semiconductors and remain potential candidates for electronic switching devices.

Dirac point and transconductance of top-gated graphene field-effect transistors operating at elevated temperature

Top-gated graphene field-effect transistors (GFETs) have been fabricated using bilayer epitaxial graphene grown on the Si-face of 4H-SiC substrates by thermal decomposition of silicon carbide in high vacuum. Graphene films were characterized by Raman spectroscopy, Atomic Force Microscopy, Scanning Tunnelling Microscopy, and Hall measurements to estimate graphene thickness, morphology, and charge transport properties. A 27 nm thick Al2O3 gate dielectric was grown by atomic layer deposition with an e-beam evaporated Al seed layer. Electrical characterization of the GFETs has been performed at operating temperatures up to 100 °C limited by deterioration of the gate dielectric performance at higher temperatures. Devices displayed stable operation with the gate oxide dielectric strength exceeding 4.5 MV/cm at 100 °C. Significant shifting of the charge neutrality point and an increase of the peak transconductance were observed in the GFETs as the operating temperature was elevated from room temperature to 100 °C.

Antenna-integrated 0.6 THz FET direct detectors based on CVD graphene.

We present terahertz (THz) detectors based on top-gated graphene field effect transistors (GFETs) with integrated split bow-tie antennas. The GFETs were fabricated using graphene grown by chemical vapor deposition (CVD). The THz detectors are capable of room-temperature rectification of a 0.6 THz signal and achieve a maximum optical responsivity better than 14 V/W and minimum optical noise-equivalent power (NEP) of 515 pW/Hz(0.5). Our results are a significant improvement over previous work on graphene direct detectors and are comparable to other established direct detector technologies. This is the first time room-temperature direct detection has been demonstrated using CVD graphene, which introduces the potential for scalable, wafer-level production of graphene detectors.