Top-gated Graphene Research Articles

Capacitance of graphene in aqueous electrolytes: The effects of dielectric saturation of water and finite size of ions

We present a theoretical model for electrolytically top-gated graphene, in which we analyze the effects of dielectric saturation of water due to possibly strong electric fields near the surface of a highly charged graphene, as well as the steric effects due to the finite size of salt ions in an aqueous electrolyte. By combining two well-established analytical models for those two effects, we show that the total capacitance of the solution-gated graphene is dominated by its quantum capacitance for gating potentials $\ensuremath{\lesssim}1\phantom{\rule{0.28em}{0ex}}\mathrm{V}$, which is the range of primary interest for most sensor applications of graphene. On the other hand, at the potentials $\ensuremath{\gtrsim}1\phantom{\rule{0.28em}{0ex}}\mathrm{V}$ the total capacitance is dominated by a universal capacitance of the electric double layer in the electrolyte, which exhibits a dramatic decrease of capacitance with increasing gating potential due to the interplay of a fully saturated dielectric constant of water and ion crowding near graphene.

High performance graphene field effect transistors on an aluminum nitride substrate with high surface phonon energy

We demonstrate top-gate graphene field effect transistors (FETs) on an aluminum nitrite (AlN) substrate with high surface phonon energy. Electrical transport measurements reveal significant improvement of the carrier mobility of graphene FETs on AlN compared to those on SiO2. This is attributed to the suppression of surface phonon scattering due to the high surface phonon energy of the AlN substrate. The RF cut-off frequency of the graphene FET is also greatly increased when the AlN substrate is used. AlN can easily be formed on a Si or SiO2 substrate using a standard semiconductor process and thus provides a practical way to improve the performance of graphene FETs.

Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors

We measure top-gated graphene field effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-k dielectric or graphene imperfections, the drain current decreases ~10% over time scales of ~10 us, consistent with charge trapping mechanisms. Pulsed operation leads to hysteresis-free I-V characteristics, which are studied with pulses as short as 75 ns and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple DC characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/um. In addition, using modeling and capacitance-voltage measurements we extract charge trap densities up to 10^12 1/cm^2 in the top gate dielectric (here Al2O3). Our study illustrates important time- and field-dependent imperfections of top-gated GFETs with high-k dielectrics, which must be carefully considered for future developments of this technology

Nanoscale Device Modeling and Circuit-Level Performance Projection of Top-Gated Graphene Nanoribbon Field-Effect Transistor for Digital Logic Gates

Nanoscale Device Modeling and Circuit-Level Performance Projection of Top-Gated Graphene Nanoribbon Field-Effect Transistor for Digital Logic Gates

Fabrication of Transferable Al2O3 Nanosheet by Atomic Layer Deposition for Graphene FET

Without introducing defects in the monolayer of carbon lattice, the deposition of high-κ dielectric material is a significant challenge because of the difficulty of high-quality oxide nucleation on graphene. Previous investigations of the deposition of high-κ dielectrics on graphene have often reported significant degradation of the electrical properties of graphene. In this study, we report a new way to integrate high-κ dielectrics with graphene by transferring a high-κ dielectric nanosheet onto graphene. Al2O3 film was deposited on a sacrificial layer using an atomic layer deposition process and the Al2O3 nanosheet was fabricated by removing the sacrificial layer. Top-gated graphene field-effect transistors were fabricated and characterized using the Al2O3 nanosheet as a gate dielectric. The top-gated graphene was demonstrated to have a field-effect mobility up to 2200 cm(2)/(V s). This method provides a new method for high-performance graphene devices with broad potential impacts reaching from high-frequency high-speed circuits to flexible electronics.

Quasi-exact solution to the Dirac equation for the hyperbolic-secant potential

We analyze bound modes of two-dimensional massless Dirac fermions confined within a hyperbolic secant potential, which provides a good fit for potential profiles of existing top-gated graphene structures. We show that bound states of both positive and negative energies exist in the energy spectrum and that there is a threshold value of the characteristic potential strength for which the first mode appears. Analytical solutions are presented in several limited cases and supercriticality is discussed.

Tuning of quantum interference in top-gated graphene on SiC

We report on quantum-interference measurements in top-gated Hall bars of monolayer graphene epitaxially grown on the Si face of SiC, in which the transition from negative to positive magnetoresistance was achieved varying temperature and charge density. We perform a systematic study of the quantum corrections to the magnetoresistance due to quantum interference of quasiparticles and electron-electron interaction. We analyze the contribution of the different scattering mechanisms affecting the magnetotransport in the $-2.0 \times 10^{10}$ cm$^{-2}$ to $3.75 \times 10^{11}$ cm$^{-2}$ density region and find a significant influence of the charge density on the intravalley scattering time. Furthermore, we observe a modulation of the electron-electron interaction with charge density not accounted for by present theory. Our results clarify the role of quantum transport in SiC-based devices, which will be relevant in the development of a graphene-based technology for coherent electronics.

Looking behind the scenes: Raman spectroscopy of top-gated epitaxial graphene through the substrate

Raman spectroscopy is frequently used to study the properties of epitaxial graphene grown on silicon carbide (SiC). In this work, we present a confocal micro-Raman study of epitaxial graphene on SiC(0001) in top-down geometry, i.e. in a geometry where both the primary laser light beam as well as the back-scattered light is guided through the SiC substrate. Compared to the conventional top-up configuration, in which confocal micro-Raman spectra are measured from the air side, we observe a significant intensity enhancement in top-down configuration, indicating that most of the Raman-scattered light is emitted into the SiC substrate. The intensity enhancement is explained in terms of dipole radiation at a dielectric surface. The new technique opens the possibility to probe graphene layers in devices where the graphene layer is covered by non-transparent materials. We demonstrate this by measuring gate-modulated Raman spectra of a top-gated epitaxial graphene field effect device. Moreover, we show that these measurements enable us to disentangle the effects of strain and charge on the positions of the prominent Raman lines in epitaxial graphene on SiC.

Resonance broadening and tuning of split ring resonators by top-gated epitaxial graphene on SiC substrate

Split ring resonators (SRRs) are subwavelength structures that are able to localize and enhance the electromagnetic wave. Controlling the plasmonic resonance behavior of metallic nanostructures, such as SRRs, plays an important role in optoelectronics and nanophotonics applications. Electrically tunable carrier concentration of graphene provides hybrid devices, where the plasmonic structures and graphene are combined. In this paper, we report the design, fabrication, and measurement of a device comprising a SRR array on epitaxial graphene. We obtained resonance broadening and tuning of split ring resonators by utilizing an epitaxial graphene transistor with transparent top-gate.

Modeling Radiation-Induced Degradation in Top-Gated Epitaxial Graphene Field-Effect-Transistors (FETs)

This paper investigates total ionizing dose (TID) effects in top-gated epitaxial graphene field-effect-transistors (GFETs). Measurements reveal voltage shifts in the current-voltage (I-V) characteristics and degradation of carrier mobility and minimum conductivity, consistent with the buildup of oxide-trapped charges. A semi-empirical approach for modeling radiation-induced degradation in GFETs effective carrier mobility is described in the paper. The modeling approach describes Coulomb and short-range scattering based on calculations of charge and effective vertical field that incorporate radiation-induced oxide trapped charges. The transition from the dominant scattering mechanism is correctly described as a function of effective field and oxide trapped charge density. Comparison with experimental data results in good qualitative agreement when including an empirical component to account for scatterer transparency in the low field regime.

Theory of remote phonon scattering in top-gated single-layer graphene

We extend the theory of interfacial plasmon-phonon scattering to top-gated single-layer graphene. As with bottom-gated graphene, interfacial plasmon-phonon (IPP) modes are formed from the coupling between the graphene plasmon and the surface polar phonon modes in the top and bottom oxides. We study the effect of the top oxide thickness on dynamic screening and electron-IPP coupling. The remote phonon-limited electron mobility ${\ensuremath{\mu}}_{\mathrm{RP}}$ and electron scattering rates in a HfO${}_{2}$-covered, SiO${}_{2}$-supported single-layer graphene are computed at various electron densities $n$ for different dielectric thickness ${t}_{\mathrm{ox}}$. We find that ${\ensuremath{\mu}}_{\mathrm{RP}}$ is much more dependent on ${t}_{\mathrm{ox}}$ at low $n$. They also agree with the experimentally estimated room temperature ${\ensuremath{\mu}}_{\mathrm{RP}}$ from Zou et al. [Phys. Rev. Lett. 105, 126601 (2010)]. The electron density dependent ${\ensuremath{\mu}}_{\mathrm{RP}}$ is predicted to be between 5500 and $24\phantom{\rule{0.16em}{0ex}}200$ cm${}^{2}$V${}^{\ensuremath{-}1}$s${}^{\ensuremath{-}1}$ from $n={10}^{12}$ to ${10}^{13}$ cm${}^{\ensuremath{-}2}$ at 300 K.

Top oxide thickness dependence of remote phonon and charged impurity scattering in top-gated graphene

We have calculated the substrate-limited electron mobility in top-gated, SiO2-supported single-layer graphene from remote-phonon and charged impurity scattering rates. The mobility dependence on gate insulator thickness is explained in terms of the dielectric screening of remote phonons and charged impurities by the high-κ/metal gate. We also find that the effects of high-κ/metal gate screening are reduced at high carrier densities. Of the top gate dielectrics considered (h-BN, HfO2, and Al2O3), h-BN results in a better overall performance and most mobility improvement with a thinner top gate.

Density of States and Its Local Fluctuations Determined by Capacitance of Strongly Disordered Graphene

We demonstrate that fluctuations of the local density of states (LDOS) in strongly disordered graphene play an important role in determining the quantum capacitance of the top-gate graphene devices. Depending on the strength of the disorder induced by metal-cluster decoration, the measured quantum capacitance of disordered graphene can dramatically decrease in comparison with pristine graphene. This is opposite to the common belief that quantum capacitance should increase with disorder. To explain this counterintuitive behavior, we present a two-parameter model which incorporates both the non-universal power law behavior for the ADOS and a lognormal distribution of LDOS. We find excellent quantitative agreements between the model and measured quantum capacitance for three disordered samples in a wide range of Fermi energies. Thus, by measuring the quantum capacitance, we can simultaneously determine the ADOS and its fluctuations. It is the LDOS fluctuations that cause the dramatic reduction of the quantum capacitance.

Reducing Contact Resistance in Graphene Devices through Contact Area Patterning

Performance of graphene electronics is limited by contact resistance associated with the metal-graphene (M-G) interface, where unique transport challenges arise as carriers are injected from a 3D metal into a 2D-graphene sheet. In this work, enhanced carrier injection is experimentally achieved in graphene devices by forming cuts in the graphene within the contact regions. These cuts are oriented normal to the channel and facilitate bonding between the contact metal and carbon atoms at the graphene cut edges, reproducibly maximizing "edge-contacted" injection. Despite the reduction in M-G contact area caused by these cuts, we find that a 32% reduction in contact resistance results in Cu-contacted, two-terminal devices, while a 22% reduction is achieved for top-gated graphene transistors with Pd contacts as compared to conventionally fabricated devices. The crucial role of contact annealing to facilitate this improvement is also elucidated. This simple approach provides a reliable and reproducible means of lowering contact resistance in graphene devices to bolster performance. Importantly, this enhancement requires no additional processing steps.

Reply to 'Measurement of mobility in dual-gated MoS2 transistors'

In our previous paper, we reported on switchable monolayer MoS2 transistors with a high on-off ratio and we claim that dielectric screening can be used to increase the mobility of monolayer MoS2. We estimated its mobility using a method previously applied by Lemme et al. to top-gated graphene nanoribbons. We discuss here the comments raised by M. Fuhrer and J. Hone in their post 1301.4288 and give our own estimates of the possible errors in previous mobility measurements and their origins.

Pseudosaturation and Negative Differential Conductance in Graphene Field-Effect Transistors

We study theoretically the different transport behaviors and the electrical characteristics of a top-gated graphene field-effect transistor where boron nitride is used as the substrate and gate insulator material, which makes the ballistic transport realistic. Our simulation model is based on the Green's function approach to solving a tight-binding Hamiltonian for graphene, self-consistently coupled with Poisson's equation. The analysis emphasizes the effects of the chiral character of carriers in graphene in the different transport regimes including the Klein and band-to-band tunneling processes. In particular, the Klein tunneling is shown to have an important role on the onset of the current saturation which is analyzed in detail as a function of the device parameters. Additionally, we predict the possible emergence of negative differential conductance and investigate its dependence on the BN-induced bandgap, the temperature, and the gate insulator thickness. Short-channel effects are evaluated from the analysis of transfer characteristics as a function of gate length and gate insulator thickness. They manifest through the shift of the Dirac point and the appearance of current oscillations at short gate length.

Modification of electronic properties of top-gated graphene devices by ultrathin yttrium-oxide dielectric layers

We report the structure characterization and electronic property modification of single layer graphene (SLG) field-effect transistor (FET) devices top-gated using ultrathin Y(2)O(3) as dielectric layers. Based on the Boltzmann transport theory within variant screening, Coulomb scattering is confirmed quantitatively to be dominant in Y(2)O(3)-covered SLG and a very few short-range impurities have been introduced by Y(2)O(3). Both DC transport and AC capacitance measurements carried out at cryogenic temperatures demonstrate that the broadening of Landau levels is mainly due to the additional charged impurities and inhomogeneity of carriers induced by Y(2)O(3) layers.

Self-aligned graphene field-effect transistors with polyethyleneimine doped source/drain access regions

We report a method of fabricating self-aligned, top-gated graphene field-effect transistors (GFETs) employing polyethyleneimine spin-on-doped source/drain access regions, resulting in a 2X reduction of access resistance and a 2.5X improvement in device electrical characteristics, over undoped devices. The GFETs on Si/SiO2 substrates have high carrier mobilities of up to 6300 cm2/Vs. Self-aligned spin-on-doping is applicable to GFETs on arbitrary substrates, as demonstrated by a 3X enhancement in performance for GFETs on insulating quartz substrates, which are better suited for radio frequency applications.

Charged impurity scattering in top-gated graphene nanostructures

We study charged impurity scattering and static screening in a top-gated substrate-supported graphene nanostructure. Our model describes how boundary conditions can be incorporated into scattering, sheds light on the dielectric response of these nanostructures, provides insights into the effect of the top gate on impurity scattering, and predicts that the carrier mobility in such graphene heterostructures decreases with increasing top dielectric thickness and higher carrier density. An increase of up to almost 60$%$ in carrier mobility in ultrathin top-gated graphene is predicted.

Synthesis and Characterization of Hexagonal Boron Nitride Film as a Dielectric Layer for Graphene Devices

Hexagonal boron nitride (h-BN) is a promising material as a dielectric layer or substrate for two-dimensional electronic devices. In this work, we report the synthesis of large-area h-BN film using atmospheric pressure chemical vapor deposition on a copper foil, followed by Cu etching and transfer to a target substrate. The growth rate of h-BN film at a constant temperature is strongly affected by the concentration of borazine as a precursor and the ambient gas condition such as the ratio of hydrogen and nitrogen. h-BN films with different thicknesses can be achieved by controlling the growth time or tuning the growth conditions. Transmission electron microscope characterization reveals that these h-BN films are polycrystalline, and the c-axis of the crystallites points to different directions. The stoichiometry ratio of boron and nitrogen is close to 1:1, obtained by electron energy loss spectroscopy. The dielectric constant of h-BN film obtained by parallel capacitance measurements (25 μm(2) large areas) is 2-4. These CVD-grown h-BN films were integrated as a dielectric layer in top-gated CVD graphene devices, and the mobility of the CVD graphene device (in the few thousands cm(2)/(V·s) range) remains the same before and after device integration.