Top-gate Field-effect Transistors Research Articles

Selective-area growth and controlled substrate coupling of transition metal dichalcogenides

Developing a means for true bottom-up, selective-area growth of two-dimensional (2D) materials on device-ready substrates will enable synthesis in regions only where they are needed. Here, we demonstrate seed-free, site-specific nucleation of transition metal dichalcogenides (TMDs) with precise control over lateral growth by utilizing an ultra-thin polymeric surface functionalization capable of precluding nucleation and growth. This polymer functional layer (PFL) is derived from conventional photoresists and lithographic processing, and is compatible with multiple growth techniques, precursors (metal organics, solid-source) and TMDs. Additionally, we demonstrate that the substrate can play a major role in TMD transport properties. With proper TMD/substrate decoupling, top-gated field-effect transistors (FETs) fabricated with selectively-grown monolayer MoS2 channels are competitive with current reported MoS2 FETs. The work presented here demonstrates that substrate surface engineering is key to realizing precisely located and geometrically-defined 2D layers via unseeded chemical vapor deposition techniques.

Coupling Two-Dimensional MoTe2 and InGaZnO Thin-Film Materials for Hybrid PN Junction and CMOS Inverters.

We report the fabrication of hybrid PN junction diode and complementary (CMOS) inverters, where 2D p-type MoTe2 and n-type thin film InGaZnO (IGZO) are coupled for each device process. IGZO thin film was initially patterned by conventional photolithography either for n-type material in a PN diode or for n-channel of top-gate field-effect transistors (FET) in CMOS inverter. The hybrid PN junction diode shows a good ideality factor of 1.57 and quite a high ON/OFF rectification ratio of ∼3 × 104. Under photons, our hybrid PN diode appeared somewhat stable only responding to high-energy photons of blue and ultraviolet. Our 2D nanosheet-oxide film hybrid CMOS inverter exhibits voltage gains as high as ∼40 at 5 V, low power consumption less than around a few nW at 1 V, and ∼200 μs switching dynamics.

Trap Densities at Gate Dielectric/2D Channel Interface By Capacitance Measurements

The scaling of CMOS technology is reaching its saturation to the point where research for successors to silicon as the channel material has gained a high momentum. Two-dimensional (2-D) materials, such as transition metal dichalcogenides (TMDCs) and black phosphorus can be scaled down to a single atomic layer with uniformity, and without any out-of-plane dangling bond, thereby establishing them as potential candidates for beyond CMOS technologies.,. But the absence of out-of-plane bonds also prevents the atomic layer deposition (ALD) of dielectrics on them. An intermediate layer called the nucleation or seeding layer is required to be deposited on them for high quality uniform ALD of dielectrics as the gate material. However, the seeding layer introduces traps at the interface of the 2D channel and the gate dielectric, causing scattering of carriers and degrading the mobility of the channel. It is crucial to reduce the interface trap density in order to improve the device performance and reliability. Capacitance measurements on a top-gated 2-D field effect transistor (FET) can give valuable insight into the nature and density of the interface traps. We use capacitance-voltage and capacitance-frequency measurements to quantify the interface trap density (Dit ) for various types of nucleation layers for ALD. Also we compare the Dit for various ALD high-k dielectrics, including Al2O3, HfO2 and ZrO2. The change of Dit with the number of layers of 2D material constituting the channel is studied. We use the most commonly studied 2-D material, MoS2 as the channel material for our interface studies. MoS2 flakes are obtained by mechanical exfoliation with scotch tape on a p+ Si substrate with 260 nm thick thermally grown SiO2. Source and drain contacts are patterned on the MoS2 flakes by electron beam lithography followed by the electron-beam evaporation and lift-off of Ni/Au. The under-lapped top gate is patterned by e-beam lithography. The seeding layer for ALD is e-beam evaporated next. Three types of seeding layers are used, viz. Ti (1 nm), Al (1 nm) and SiOx (1 nm). The elemental metals used as seeding layer are allowed to oxidize in air before introducing into the ALD chamber. The high-k dielectrics are deposited by ALD at lower temperatures (~110 oC), which facilitates the lift-off of the resist used in e-beam lithography (PMMA). Then Ni is e-beam evaporated as the gate contact, followed by the lift-off of the gate stack in warm acetone. The characterization of the top-gated FETs is done in several stages. Firstly, the drain current vs. top gate voltage (VTG ) characteristics of an FET is measured at varying back gate voltages (VBG ). At high positive VBG, the underlapped regions in the FET are populated with electrons, and the series resistance is low. The subthreshold swing from the1 ID-VTG curves, gives an idea of the interface trap density. Our devices show an average subthreshold swing of ~70 mV/dec, indicating that interface traps, albeit being low in density, are present. Next, the capacitance is measured in a top-gated 2-D FET by which the interface trap density of 2D material/high-k dielectric stack is extracted. The source/drain electrodes are shorted and the capacitance form the gate to the source/drain electrodes are measured. The gate capacitance is extracted for a known thickness of the high-k dielectric layer in the accumulation region. The dependence of frequency in the C-V characteristics indicates the presence of the interface traps. The Dit is calculated by the conductance method, described by Takei et al.1 This method will be used to identify the seeding layer that contributes to the least Dit . The high-k gate dielectric material will be varied next, to evaluate its effect on the trap density. The interface trap densities in the case of HfO2, ZrO2 and Al2O3 will be extracted and compared. The effect of number of layers in the 2-D channel will be studied. The best combination of channel thickness, seeding layer and high-k gate dielectric producing the lowest Dit will be reported. 1 Kuniharu Takei, Rehan Kapadia, Hui Fang, E. Plis, Sanjay Krishna, and Ali Javey, Applied Physics Letters 102 (15) (2013).

Parylene based bilayer flexible gate dielectric layer for top-gated organic field-effect transistors

In this paper, we report on a bilayer insulating film based on parylene-c for gate dielectric layers in top-gate/bottom-contact inkjet-printed organic field-effect transistors (OFETs) with indacenodithiophene-co-benzothiadiazole (IDTBT) and poly([N,N’-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5’-(2,2’-bitthiophene)) (P(NDI2OD-T2)) as with p- and n-channel semiconductors. The thin parylene-c film (t = 210 nm) show large gate leakage density (2.52 nA/cm2 at 25 V) and low breakdown voltage (2.2 MV/cm). In addition, a degraded field-effect mobility (μ) was observed in printed IDTBT and P(NDI2OD-T2) OFETs with the parylene-c single-layered dielectric. X-ray photoelectron spectroscopy (XPS) analysis reveals that the degradation of μ is due to unwanted chemical interaction between parylene-c and the conjugated polymer surface during the parylene-c deposition process. By inserting 50-nm thick poly(methyl-methacrylate) (PMMA) and polystyrene (PS) layer in-between the parylene-c and conjugated polymer film, highly improved gate leakage density and breakdown voltage are achieved. The printed IDTBT and P(NDI2OD-T2) OFETs with a bilayer dielectric compose of parylene-c and PMMA and PS show significantly improved hole and electron μ of 0.47 cm2/Vs and 0.13 cm2/Vs, respectively, and better operation stability. In addition, we demonstrate inkjet-printed polymer complementary inverter with a high voltage gain of 25.7 by applying a PS/parylene-c bilayer dielectric.

High electron mobility and quantum oscillations in non-encapsulated ultrathin semiconducting Bi2O2Se.

High-mobility semiconducting ultrathin films form the basis of modern electronics, and may lead to the scalable fabrication of highly performing devices. Because the ultrathin limit cannot be reached for traditional semiconductors, identifying new two-dimensional materials with both high carrier mobility and a large electronic bandgap is a pivotal goal of fundamental research. However, air-stable ultrathin semiconducting materials with superior performances remain elusive at present. Here, we report ultrathin films of non-encapsulated layered Bi2O2Se, grown by chemical vapour deposition, which demonstrate excellent air stability and high-mobility semiconducting behaviour. We observe bandgap values of ∼0.8 eV, which are strongly dependent on the film thickness due to quantum-confinement effects. An ultrahigh Hall mobility value of >20,000 cm2 V-1 s-1 is measured in as-grown Bi2O2Se nanoflakes at low temperatures. This value is comparable to what is observed in graphene grown by chemical vapour deposition and at the LaAlO3-SrTiO3 interface, making the detection of Shubnikov-de Haas quantum oscillations possible. Top-gated field-effect transistors based on Bi2O2Se crystals down to the bilayer limit exhibit high Hall mobility values (up to 450 cm2 V-1 s-1), large current on/off ratios (>106) and near-ideal subthreshold swing values (∼65 mV dec-1) at room temperature. Our results make Bi2O2Se a promising candidate for future high-speed and low-power electronic applications.

Bis-Diketopyrrolopyrrole Moiety as a Promising Building Block to Enable Balanced Ambipolar Polymers for Flexible Transistors.

A bis-diketopyrrolopyrrole (DPP dimer, 2DPP) core is synthesized with much stronger electron deficiency than DPP by homocoupling of DPP. 2DPP-based polymers, P2DPP-BT, P2DPP-TT, P2DPP-TVT, and P2DPP-BDT, are obtained. Top-gated organic field-effect transistors on plastic substrate are fabricated. Compared with their mono-DPP-based polymers, remarkable improvement of electron mobilities of P2DPPs is achieved. Meanwhile, their p-channel performance becomes higher.

Ferroelectric FET for nonvolatile memory application with two-dimensional MoSe2 channels

Graphene and other two-dimensional materials have received considerable attention regarding their potential applications in nano-electronics. Here, we report top-gate nonvolatile memory field-effect transistors (FETs) with different layers of MoSe2 nanosheets channel gated by ferroelectric film. The conventional gate dielectric of FETs was replaced by a ferroelectric thin film that provides a ferroelectric polarization electric field, and therefore defined as an Fe-FET where the poly (vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) was used as the gate dielectric. Among the devices with MoSe2 channels of different thicknesses, the device with a single layer of MoSe2 exhibited a large hysteresis of electronic transport with an over 105 write/erase ratio, and displayed excellent retention and endurance performance. The possible mechanism of the device’s good properties was qualitatively analyzed using band theory. Additionally, a comprehensive study comparing the memory properties of MoSe2 channels of different thicknesses is presented. Increasing the numbers of MoSe2 layers was found to cause a reduced memory window. However, MoSe2 thickness of 5 nm yielded a write/erase ratio of more than 103. The results indicate that, based on a Fe-FET structure, the combination of two-dimensional semiconductors and organic ferroelectric gate dielectrics shows good promise for future applications in nonvolatile ferroelectric memory.

High performance top-gated ferroelectric field effect transistors based on two-dimensional ZnO nanosheets

High quality ultrathin two-dimensional zinc oxide (ZnO) nanosheets (NSs) are synthesized, and the ZnO NS ferroelectric field effect transistors (FeFETs) are demonstrated based on the P(VDF-TrFE) polymer film used as the top gate insulating layer. The ZnO NSs exhibit a maximum field effect mobility of 588.9 cm2/Vs and a large transconductance of 2.5 μS due to their high crystalline quality and ultrathin two-dimensional structure. The polarization property of the P(VDF-TrFE) film is studied, and a remnant polarization of >100 μC/cm2 is achieved with a P(VDF-TrFE) thickness of 300 nm. Because of the ultrahigh remnant polarization field generated in the P(VDF-TrFE) film, the FeFETs show a large memory window of 16.9 V and a high source-drain on/off current ratio of more than 107 at zero gate voltage and a source-drain bias of 0.1 V. Furthermore, a retention time of >3000 s of the polarization state is obtained, inspiring a promising candidate for applications in data storage with non-volatile features.

Scaling carbon nanotube complementary transistors to 5-nm gate lengths.

High-performance top-gated carbon nanotube field-effect transistors (CNT FETs) with a gate length of 5 nanometers can be fabricated that perform better than silicon complementary metal-oxide semiconductor (CMOS) FETs at the same scale. A scaling trend study revealed that the scaled CNT-based devices, which use graphene contacts, can operate much faster and at much lower supply voltage (0.4 versus 0.7 volts) and with much smaller subthreshold slope (typically 73 millivolts per decade). The 5-nanometer CNT FETs approached the quantum limit of FETs by using only one electron per switching operation. In addition, the contact length of the CNT CMOS devices was also scaled down to 25 nanometers, and a CMOS inverter with a total pitch size of 240 nanometers was also demonstrated.

High-Performance, Air-Stable Field-Effect Transistors Based on Heteroatom-Substituted Naphthalenediimide-Benzothiadiazole Copolymers Exhibiting Ultrahigh Electron Mobility up to 8.5 cm V-1 s-1.

Rational heteroatom engineering is applied to develop high-performance electron-transporting naphthalenediimide copolymers. Top-gate field-effect transistors fabricated from selenophene-containing polymers achieve an ultrahigh electron mobility of 8.5 cm2 V-1 s-1 and excellent air-stability. The results demonstrate that the incorporation of selenophene heterocycles into the polymers can improve the film-forming ability, intermolecular interaction, and carrier transport significantly.

Top-gate organic field-effect transistors fabricated on paper with high operational stability

We report on top-gate organic field-effect transistors (OFETs) fabricated on specialty paper, PowerCoat™ HD 230 from Arjowiggins Creative Papers coated with a buffer layer composed of a polyvinyl alcohol (PVA) and polyvinylpyrrolidine (PVP) blend. OFETs operate at low voltages and display average carrier mobility values of 1.7 ± 1.1 × 10−1 cm2/Vs, average threshold voltage values of −1.4 ± 0.2 V, and average on/off current ratio of 105. OFETs also display excellent operational stability demonstrated by stable 1000 scans of the transfer characteristics and by stable on-currents displaying less than 6% change during a DC bias stress test at VDS = VGS = −10 V for 1 h. Furthermore, OFETs on paper display a decrease of only 7% in their on-state current during a bending test. The performance of these OFETs on paper is comparable to that displayed by top-gate OFETs with the same geometry fabricated on glass substrates.

An Ultra-Short Channel Monolayer MoS2 FET Defined By the Curvature of a Thin Nanowire

In this letter, we demonstrate the first top-gated 10-nm scale field-effect transistor with chemical-vapor-deposition synthesized monolayer MoS2 as the channel material. Ultra-thin metallic Co2Si nanowires are employed to gate the MoS2 channel and thereby define the device feature size—gate/channel length, as well as to serve as a self-aligned mask for source/drain metallization. This process not only avoids using the high-cost and low-yield electron beam lithography to define the gate/channel length, but also enables a top-gate structure with ultrathin gate dielectric. The latter is required to suppress short channel effects, but difficult to achieve with conventional deposition techniques on 2D layered semiconductors. Moreover, low OFF-current of 10 pA/ $\mu \text{m}$ and high ON/OFF current ratio over six orders are achieved, which makes this device quite promising for next-generation CMOS technology.

Impact of uniaxial compressive strain on physical and electronic parameters of a 10 nm germanene nanoribbon field effect transistor

In this paper, a top-gated Germanene nanoribbon field effect transistor (GeNR-FET) with and without applying a compressive strain is investigated. Three strain strengths (ε = 3%, 5% and 10%) are applied to the different regions of the proposed GeNR-FET and the obtained transistor characteristics are compared with each other. Moreover, physical and electronic parameters of unstrained and strained GeNR are calculated. The results indicate that the bandgap and electron effective mass of GeNR increase firstly by increasing the strain strength but then decrease and this behavior affects on the transistor figures of merit. We find that the Ion/Ioff ratio and subthreshold swing (SS) of the unstrained FET improves when a 3% compressive strain is applied to the whole of the device. Also, applying a 10% strain to the device increases the ON current of the FET due to strain-induced self-doping behavior, but the obtained transistor parameters for this structure are not very satisfactory. Next, we apply the compressive strain either only to the channel or only to the source and drain of the devices. The obtained results show, due to high lattice mismatch between the channel and the leads, the transistor performance of the strained FETs are almost the same or even worse than that of the unstrained one. A novel engineered device is proposed and the transistor figures of merit and in particular, the analog performance are emphasized. It is found that the new proposed device has a better Ion/Ioff ratio and SS. In addition, negative differential resistance occurs in this transistor. The analog performance of the novel device is obtained and compared with the unstrained and 3% strained GeNR-FET in the subthreshold region. It is observed that the proposed device has a better transconductance and voltage gain so that it is a good candidate for analog applications.

A Study on Reducing Contact Resistance in Solution-Processed Organic Field-Effect Transistors

We report on the reduction of contact resistance in solution-processed TIPS-pentacene (6,13-bis(triisopropylsilylethynyl)pentacene) and PTAA (poly[bis(4-phenyl)(2,4,6-trimethylphenyl)amine]) top-gate bottom-contact organic field-effect transistors (OFETs) by using different contact-modification strategies. The study compares the contact resistance values in devices that comprise Au source/drain electrodes either treated with 2,3,4,5,6-pentafluorothiophenol (PFBT), or modified with an evaporated thin layer of the metal-organic molecular dopant molybdenum tris-[1,2-bis(trifluoromethyl)ethane-1,2-dithiolene] (Mo(tfd)3), or modified with a thin layer of the oxide MoO3. An improved performance is observed in devices modified with Mo(tfd)3 or MoO3 as compared to devices in which Au electrodes are modified with PFBT. We discuss the origin of the decrease in contact resistance in terms of increase of the work function of the modified Au electrodes, Fermi-level pinning effects, and decrease of bulk resistance by electrically doping the organic semiconductor films in the vicinity of the source/drain electrodes.

Tunable Ambipolar Polarization-Sensitive Photodetectors Based on High-Anisotropy ReSe2 Nanosheets.

Atomically thin 2D-layered transition-metal dichalcogenides have been studied extensively in recent years because of their intriguing physical properties and promising applications in nanoelectronic devices. Among them, ReSe2 is an emerging material that exhibits a stable distorted 1T phase and strong in-plane anisotropy due to its reduced crystal symmetry. Here, the anisotropic nature of ReSe2 is revealed by Raman spectroscopy under linearly polarized excitations in which different vibration modes exhibit pronounced periodic variations in intensity. Utilizing high-quality ReSe2 nanosheets, top-gate ReSe2 field-effect transistors were built that show an excellent on/off current ratio exceeding 10(7) and a well-developed current saturation in the current-voltage characteristics at room temperature. Importantly, the successful synthesis of ReSe2 directly onto hexagonal boron nitride substrates has effectively improved the electron motility over 500 times and the hole mobility over 100 times at low temperatures. Strikingly, corroborating with our density-functional calculations, the ReSe2-based photodetectors exhibit a polarization-sensitive photoresponsivity due to the intrinsic linear dichroism originated from high in-plane optical anisotropy. With a back-gate voltage, the linear dichroism photodetection can be unambiguously tuned both in the electron and hole regime. The appealing physical properties demonstrated in this study clearly identify ReSe2 as a highly anisotropic 2D material for exotic electronic and optoelectronic applications.

Chemical-free n-type and p-type multilayer-graphene transistors

A single-step doping method to fabricate n- and p-type multilayer graphene (MG) top-gate field effect transistors (GFETs) is demonstrated. The transistors are fabricated on soda-lime glass substrates, with the n-type doping of MG caused by the sodium in the substrate without the addition of external chemicals. Placing a hydrogen silsesquioxane (HSQ) barrier layer between the MG and the substrate blocks the n-doping, resulting in p-type doping of the MG above regions patterned with HSQ. The HSQ is deposited in a single fabrication step using electron beam lithography, allowing the patterning of arbitrary sub-micron spatial patterns of n- and p-type doping. When a MG channel is deposited partially on the barrier and partially on the glass substrate, a p-type and n-type doping profile is created, which is used for fabricating complementary transistors pairs. Unlike chemically doped GFETs in which the external dopants are typically introduced from the top, these substrate doped GFETs allow for a top gate which gives a stronger electrostatic coupling to the channel, reducing the operating gate bias. Overall, this method enables scalable fabrication of n- and p-type complementary top-gated GFETs with high spatial resolution for graphene microelectronic applications.

Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

Control of Threshold Voltage for Top-Gated Ambipolar Field-Effect Transistor by Gate Buffer Layer

The threshold voltage and onset voltage for p-channel and n-channel regimes of solution-processed ambipolar organic transistors with top-gate/bottom-contact (TG/BC) geometry were effectively tuned by gate buffer layers in between the gate electrode and the dielectric. The work function of a pristine Al gate electrode (-4.1 eV) was modified by cesium carbonate and vanadium oxide to -2.1 and -5.1 eV, respectively, which could control the flat-band voltage, leading to a remarkable shift of transfer curves in both negative and positive gate voltage directions without any side effects. One important feature is that the mobility of transistors is not very sensitive to the gate buffer layer. This method is simple but useful for electronic devices where the threshold voltage should be precisely controlled, such as ambipolar circuits, memory devices, and light-emitting device applications.

Large-area few-layer MoS2 deposited by sputtering

Direct magnetron sputtering of transition metal dichalcogenide targets is proposed as a new approach for depositing large-area two-dimensional layered materials. Bilayer to few-layer MoS2 deposited by magnetron sputtering followed by post-deposition annealing shows superior area scalability over 20 cm2 and layer-by-layer controllability. High crystallinity of layered MoS2 was confirmed by Raman, photo-luminescence, and transmission electron microscopy analysis. The sputtering temperature and annealing ambience were found to play an important role in the film quality. The top-gate field-effect transistor by using the layered MoS2 channel shows typical n-type characteristics with a current on/off ratio of approximately 104. The relatively low mobility is attributed to the small grain size of 0.1–1 μm with a trap charge density in grain boundaries of the order of 1013 cm–2.

Top-gated graphene field-effect transistors by low-temperature synthesized SiNx insulator on SiC substrates

Top-gated devices made from an epitaxial graphene film on a 4H-SiC substrate were fabricated. Atomic force microscopy and Raman spectroscopy results showed that a large-scale highly uniform monolayer graphene film was synthesized on the SiC substrate. A SiNx passivation film was deposited on a SiC graphene device as a top gate insulator by catalytic chemical-vapor deposition (Cat-CVD) below 65 °C. After the top gate electrode was formed on the SiNx film, no leakage current flowed between the gate and source electrodes. The transport characteristics showed clear ambipolar characteristics from 8 to 280 K, and the temperature dependences of the conductance and field-effect mobility of the devices implied that monolayer graphene devices can be successfully fabricated. Moreover, the position of the charge neutrality point after SiNx deposition was around 0 V, indicating p-doping characteristics. These results indicate that SiNx films synthesized by Cat-CVD can be used as gate insulators and that the carrier type may be controlled by adjusting the deposition conditions.