Top-gate Field-effect Transistors Research Articles

Top and Split Gating Control of the Electrical Characteristics of a Two-dimensional Electron Gas in a LaAlO3/SrTiO3 Perovskite

A top gate field effect transistor was fabricated using polymethyl methacrylate (PMMA) as a gate insulator on a LaAlO3 (LAO)/SrTiO3 (STO) hetero-interface. It showed n-type behavior, and a depletion mode was observed at low temperature. The electronic properties of the 2-dimensional electron gas at the LAO/STO hetero-interface were not changed by covering LAO with PMMA following the Au top gate electrode. A split gate device was also fabricated to construct depletion mode by using a narrow constriction between the LAO/STO conduction interface. The depletion mode, as well as superconducting critical current, could be controlled by applying a split gate voltage. Noticeably, the superconducting critical current tended to decrease with decreasing the split gate voltage and finally became zero. These results indicate that a weak-linked Josephson junction can be constructed and destroyed by split gating. This observation opens the possibility of gate-voltage-adjustable quantum devices.

Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10−2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

A High-Performance Top-Gated Graphene Field-Effect Transistor with Excellent Flexibility Enabled by an iCVD Copolymer Gate Dielectric.

A high-performance top-gated graphene field-effect transistor (FET) with excellent mechanical flexibility is demonstrated by implementing a surface-energy-engineered copolymer gate dielectric via a solvent-free process called initiated chemical vapor deposition. The ultrathin, flexible copolymer dielectric is synthesized from two monomers composed of 1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane and 1-vinylimidazole (VIDZ). The copolymer dielectric enables the graphene device to exhibit excellent dielectric performance and substantially enhanced mechanical flexibility. The p-doping level of the graphene can be tuned by varying the polar VIDZ fraction in the copolymer dielectric, and the Dirac voltage (VDirac ) of the graphene FET can thus be systematically controlled. In particular, the VDirac approaches neutrality with higher VIDZ concentrations in the copolymer dielectric, which minimizes the carrier scattering and thereby improves the charge transport of the graphene device. As a result, the graphene FET with 20 nm thick copolymer dielectrics exhibits field-effect hole and electron mobility values of over 7200 and 3800 cm2 V-1 s-1 , respectively, at room temperature. These electrical characteristics remain unchanged even at the 1 mm bending radius, corresponding to a tensile strain of 1.28%. The formed gate stack with the copolymer gate dielectric is further investigated for high-frequency flexible device applications.

High performance few-layer MoS2 transistor arrays with wafer level homogeneity integrated by atomic layer deposition

Wafer-level integration of 2D transition metal disulfide is the key factor for future large-scale integration of the continuously scaling-down devices, and has attracted great attention in recent years. Compared with other ultra-thin film growth methods, atomic layer deposition (ALD) has the advantages of excellent step coverage, uniformity and thickness controllability. In this work, we synthesized large-scale and thickness-controllable MoS2 films on sapphire substrate by ALD at 150 °C with molybdenum hexcarbonyl and hexamethyldisilathiane (HMDST) as precursors followed by high-temperature annealing in sulfur atmosphere. HMDST is introduced for the first time to enable a toxic-free process without hazardous sulfur precursors such as H2S and CH3SSCH3. The synthesized MoS2 retains the inherent benefits from the ALD process, including thickness controllability, reproducibility, wafer-level thickness uniformity, and high conformity. Finally, field-effect transistor (FET) arrays were fabricated based on the large-area ALD MoS2 films. The top-gate FETs exhibited excellent electrical performance such as high on/off current ratio over 103 and peak room-temperature mobility up to 11.56 cm2 V−1 s−1. This work opens up an attractive approach to realize the application of high-quality 2D materials with wafer scale homogeneity.

Charge carrier velocity in graphene field-effect transistors

To extend the frequency range of transistors into the terahertz domain, new transistor technologies, materials, and device concepts must be continuously developed. The quality of the interface between the involved materials is a highly critical factor. The presence of impurities can degrade device performance and reliability. In this paper, we present a method that allows the study of the charge carrier velocity in a field-effect transistor vs impurity levels. The charge carrier velocity is found using high-frequency scattering parameter measurements followed by delay time analysis. The limiting factors of the saturation velocity and the effect of impurities are then analysed by applying analytical models of the field-dependent and phonon-limited carrier velocity. As an example, this method is applied to a top-gated graphene field-effect transistor (GFET). We find that the extracted saturation velocity is ca. 1.4×107 cm/s and is mainly limited by silicon oxide substrate phonons. Within the considered range of residual charge carrier concentrations, charged impurities do not limit the saturation velocity directly by the phonon mechanism. Instead, the impurities act as traps that emit charge carriers at high fields, preventing the current from saturation and thus limiting power gain of the GFETs. The method described in this work helps to better understand the influence of impurities and clarifies methods of further transistor development. High quality interfaces are required to achieve current saturation via velocity saturation in GFETs.

Structure-Property Relationships of Semiconducting Polymers for Flexible and Durable Polymer Field-Effect Transistors.

We report high-performance top-gate bottom-contact flexible polymer field-effect transistors (FETs) fabricated by flow-coating diketopyrrolopyrrole (DPP)-based and naphthalene diimide (NDI)-based polymers (P(DPP2DT-T2), P(DPP2DT-TT), P(DPP2DT-DTT), P(NDI2OD-T2), P(NDI2OD-F2T2), and P(NDI2OD-Se2)) as semiconducting channel materials. All of the polymers displayed good FET characteristics with on/off current ratios exceeding 107. The highest hole mobility of 1.51 cm2 V-1 s-1 and the highest electron mobility of 0.85 cm2 V-1 s-1 were obtained from the P(DPP2DT-T2) and P(NDI2OD-Se2) polymer FETs, respectively. The impacts of the polymer structures on the FET performance are well-explained by the interplay between the crystallinity, the tendency of the polymer backbone to adopt an edge-on orientation, and the interconnectivity of polymer fibrils in the film state. Additionally, we demonstrated that all of the flexible polymer-based FETs were highly resistant to tensile stress, with negligible changes in their carrier mobilities and on/off ratios after a bending test. Conclusively, these high-performance, flexible, and durable FETs demonstrate the potential of semiconducting conjugated polymers for use in flexible electronic applications.

High performance top-gated multilayer WSe2 field effect transistors

In this paper, high performance top-gated WSe2 field effect transistor (FET) devices are demonstrated via a two-step remote plasma assisted ALD process. High-quality, low-leakage aluminum oxide (Al2O3) gate dielectric layers are deposited onto the WSe2 channel using a remote plasma assisted ALD process with an ultrathin (∼1 nm) titanium buffer layer. The first few nanometers (∼2 nm) of the Al2O3 dielectric film is deposited at relatively low temperature (i.e. 50 °C) and remainder of the film is deposited at 150 °C to ensure the conformal coating of Al2O3 on the WSe2 surface. Additionally, an ultra-thin titanium buffer layer is introduced at the WSe2 channel surface prior to ALD process to mitigate oxygen plasma induced doping effects. Excellent device characteristics with current on–off ratio in excess of 106 and a field effect mobility as high as 70.1 cm2 V–1 s–1 are achieved in a few-layer WSe2 FET device with a 30 nm Al2O3 top-gate dielectric. With further investigation and careful optimization, this method can play an important role for the realization of high performance top gated FETs for future optoelectronic device applications.

Atomic-Layer-Deposition Growth of an Ultrathin HfO2 Film on Graphene.

Direct growth of an ultrathin gate dielectric layer with high uniformity and high quality on graphene remains a challenge for developing graphene-based transistors due to the chemically inert surface properties of graphene. Here, we develop a method to realize atomic-layer-deposition (ALD) growth of an ultrathin high-κ dielectric layer on graphene through premodifying the graphene surface using electron beam irradiation. An amorphous carbon layer induced by electron beam scanning is formed on graphene and then acts as seeds for ALD growth of high-κ dielectrics. A uniform HfO2 layer with an equivalent oxide thickness of 1.3 nm was grown as a gate dielectric for top-gate graphene field-effect transistors (FETs). The achieved gate capacitance is up to 2.63 μF/cm2, which is the highest gate capacitance on a graphene solid-state device to date. In addition, the fabricated top-gate graphene FETs present a high carrier mobility of up to 2500 cm2/(V·s) and a negligible gate leakage current of down to 0.1 mA/cm2, showing that the ALD-grown HfO2 dielectric layer is highly uniform and of very high quality.

Controllable photoresponse behavior in a single InAs nanowire phototransistor

We demonstrate a single InAs nanowire phototransistor with controllable photoresponse behavior. The device is based on a top-gated nanowire field effect transistor with an electron mobility of 5790 cm2 V−1 s−1. In the absence of gate voltage, negative and positive photoresponses are observed under low and high illumination, respectively. By applying a relatively high negative/positive gate voltage, pure positive/negative photoresponse is obtained, respectively. The controllable photoresponse is attributed to a gate-voltage-induced barrier height modulation between the trap state energy level in the photogating layer and the conduction band of nanowire. The device is promising for optoelectronic applications.

Growth and optoelectronic property of two-dimensional semiconductors

Two-dimensional (2D) nanosheets of layered transition metal dichalcogenides (TMDs) have received significant attention because some of them are semiconductors with sizable band gaps and are naturally abundant. Here, we report the photolithographic-pattern transfer (PPT) technology used to fabricate FETs of two-dimensional materials. To explore the electrical properties and realize functional optoelectronics and electronics from semiconductors, the fabrication of devices (such as field-effect transistors (FET), diodes and Hall bars) and integrated circuits is necessary and important. An essential step in fabricating micro-/nanoelectronics is making the metal electrode arrays. Such a PPT method can be used to efficiently design and prepare complicated electrode arrays for electronics and optoelectronics, and is especially suitable for 2D materials. Few-layer MoS2 made by electron beam lithography (EBL), gold-wire mask moving (GWM), and this method are used as templates for comparison. The mobility of our thin MoS2 flake is comparable to the results of devices from EBL and better than the results of the GWM method. Further complicated device applications such as a top-gate FET, a Hall bar, and heterostructure transistors could also be easily realized based on such a method. We also report the growth and electric transport of Co doped MoS2 bilayer. As the initial loading of the sulfur increases, the morphology of the Co x Mo1– x S2 (0 x x Mo1− x S2 nanosheet gradually and forms hexagonal film induced by the nanosheet. Electrical transport measurements reveal that the Co x Mo1− x S2 nanosheets and CoS2 films exhibit n-type semiconducting transport behavior and half-metallic behavior, respectively. Theoretical calculations of their band structures agree well with the experimental results. These alloy nanosheets of Co x Mo1− x S2 should have large potential applications in the tunable optoelectronics. Then, we report the vapor phase growth and optoelectronic property of vertical bilayer SnS2/MoS2 heterostructure. 2D van der Waals heterostructures with different types of band alignment have recently attracted great attention due to their unique optical and electrical properties. Most 2D heterostructures are formed by transfer-stacking two monolayers together, but the interfacial quality and controllable orientation of such artificial structures are inferior to those epitaxial grown heterostructures. An extremely Type II band alignment exists in this 2D heterostructure, with band offset larger than any other reported. Consistent with the large band offset, distinctive optical properties including strong photoluminescence quenching in the heterostructure area are observed in the heterostructure. The SnS2/MoS2 heterostructures also exhibit well-aligned lattice orientation between the two layers, forming a periodic Moire superlattice pattern with high lattice mismatch. Electrical transport and photoresponsive studies demonstrate that the SnS2/MoS2 heterostructures exhibit an obvious photovoltaic effect and possess high on/off ratio (>106), high mobility (27.6 cm2 V−1 s−1) and high photoresponsivity (1.36 A W−1). Efficient synthesis of such vertical heterostructure may open up new realms in 2D functional electronics and optoelectronics. Finally we give some perspectives on studies of two-dimensional materials in future.

Influence of Simultaneous Tuning of Molecular Weights and Alkyl Substituents of Poly(thienoisoindigo-alt-naphthalene)s on Morphology and Change Transport Properties.

To simultaneously assess the impact of molecular weight (Mn) and alkyl substituent variations of polymers on the structural and optoelectronic properties, herein, we conduct a systematic study of a series of poly(thienoisoindigo-alt-naphthalene) (PTIIG-Np)-based polymers containing different alkyl substituents (2-hexyldecyl (HD), 2-octyldodecyl (OD), and 2-decyltetradecyl (DT) chains) and Mn's (low (L) and high (H)). All of the polymers produce almost identical energy levels, whereas their optical spectra show a clear dependence on Mn's and the alkyl substituents. Interestingly, increasing the alkyl substituent sizes of the polymers steadily increases the lamellar d-spacings (d100), ultimately leading to a densely packed lamellar structure for PTIIGHD-Np. In addition, both H-PTIIGOD-Np and H-PTIIGDT-Np exhibit larger π-stacking crystallites than the corresponding low-Mn polymers, while for PTIIGHD-Np, their size increases in the low-Mn batch. Ultimately, L-PTIIGHD-Np shows the best hole mobility of 1.87 cm2 V-1 s-1 in top-gate and bottom-contact organic field-effect transistors (OFETs) with a poly(methyl methacrylate), which is nearly 1 order of magnitude higher than other polymers tested in this study. Our results demonstrate that the simultaneous Mn and alkyl substituent engineering of the polymers can optimize their film morphology to produce high-performance OFETs.

Toward Sustainability in Organic Electronics: A Performance Check for DNA Complexes as Dielectric Layer in P3HT based OFET

Notwithstanding its manifold advantages the fast emerging area of organic electronics can invariably lead to the production of huge amounts of plastic waste and therefore developing ecofriendly organic electronic components to make it sustainable has become a priority task. Here an effort has been made in this direction where in a well-known bio material complex of deoxyribo nucleic acid and cetyltrimethylammonium chloride (DNA_CTMA) is applied as dielectric layer in a top-gate organic field effect transistor (OFET) with Poly 3-hexylthiophene (P3HT) as channel material. The DNA used was isolated from the leaf of Asteracea species plant by the biosynthesis mechanism. The device returned modest but promising operating parameters.

Impact of Metal Contacts on the Performance of Multilayer HfS2 Field-Effect Transistors.

HfS2 is one of the emerging transition metal dichalcogenides and is very promising for low-power nanoelectronics and high-sensitivity optoelectronic device applications. We studied the band structures of 1T-HfS2 with different thicknesses by first principles simulation, and the impact of different metal contacts to the HfS2 device performance has been experimentally studied. Back-gate and top-gate HfS2 field-effect transistors (FETs) were fabricated, and better electrical characteristics have been achieved with the FETs with the Ti/Au contact as compared with the Pt-contacted FETs. Thin layers of Pt and Ti/Au films were deposited on HfS2 flakes to investigate the metal/HfS2 interface by using scanning electron microscopy, atomic force microscopy, and Raman spectroscopy. A smoother Ti/Au film was formed on HfS2, resulting in higher carrier injection and transport efficiency. The phonon behavior being dominated by the interface chemical bonding at the Ti/Au contact region has been confirmed with the more sensitive A1g phonon mode from the bilayer HfS2.

Improvement in top-gate MoS2 transistor performance due to high quality backside Al2O3 layer

A high quality Al2O3 layer is developed to achieve high performance in top-gate MoS2 transistors. Compared with top-gate MoS2 field effect transistors on a SiO2 layer, the intrinsic mobility and subthreshold slope were greatly improved in high-k backside layer devices. A forming gas anneal is found to enhance device performance due to a reduction in the charge trap density of the backside dielectric. The major improvements in device performance are ascribed to the forming gas anneal and the high-k dielectric screening effect of the backside Al2O3 layer. Top-gate devices built upon these stacks exhibit a near-ideal subthreshold slope of ∼69 mV/dec and a high Y-Function extracted intrinsic carrier mobility (μo) of 145 cm2/V·s, indicating a positive influence on top-gate device performance even without any backside bias.

Carbon nanotube network film-based ring oscillators with sub 10-ns propagation time and their applications in radio-frequency signal transmission

We have fabricated top-gated ambipolar field-effect transistors (FETs) based on solution-derived carbon nanotube (CNT) network films, and then constructed inverters and ring oscillators (ROs) that can work under supply voltages as low as 0.2 V owing to the high uniformity of the devices. Significant improvements were achieved in the performance of these CNT-based ambipolar FETs and CMOS-like circuits by scaling down the gate length of the CNT FETs and optimizing the device structure and RO layout. In particular, the optimized five-stage RO is shown to present a record high oscillation frequency of up to 17.4 MHz with a propagation time of 5.6 ns at a 12-V working voltage. The CNT film-based ROs were used as carrier-wave generators in radio-frequency systems to demonstrate a complete signal transmission process. These results suggest that CNT thin film-based FETs and integrated circuits may soon find their way to radio-frequency applications with a frequency band of 13.56 MHz.

Uniform Growth of Sub-5-Nanometer High-κ Dielectrics on MoS2 Using Plasma-Enhanced Atomic Layer Deposition.

Regardless of the application, MoS2 requires encapsulation or passivation with a high-quality dielectric, whether as an integral aspect of the device (as with top-gated field-effect transistors (FETs)) or for protection from ambient conditions. However, the chemically inert surface of MoS2 prevents uniform growth of a dielectric film using atomic layer deposition (ALD)-the most controlled synthesis technique. In this work, we show that a plasma-enhanced ALD (PEALD) process, compared to traditional thermal ALD, substantially improves nucleation on MoS2 without hampering its electrical performance, and enables uniform growth of high-κ dielectrics to sub-5 nm thicknesses. Substrate-gated MoS2 FETs were studied before/after ALD and PEALD of Al2O3 and HfO2, indicating the impact of various growth conditions on MoS2 properties, with PEALD of HfO2 proving to be most favorable. Top-gated FETs with high-κ films as thin as ∼3.5 nm yielded robust performance with low leakage current and strong gate control. Mechanisms for the dramatic nucleation improvement and impact of PEALD on the MoS2 crystal structure were explored by X-ray photoelectron spectroscopy (XPS). In addition to providing a detailed analysis of the benefits of PEALD versus ALD on MoS2, this work reveals a straightforward approach for realizing ultrathin films of device-quality high-κ dielectrics on 2D crystals without the use of additional nucleation layers or damage to the electrical performance.

Transistors and tunnel diodes enabled by large-scale MoS2 nanosheets grown on GaN

We report growth, fabrication, and device results of MoS2-based transistors and diodes implemented on a single 2D/3D material platform. The 2D/3D platform consists of a large-area MoS2 thin film grown on SiO2/p-GaN substrates. Atomic force microscopy, scanning electron microscopy, and Raman spectroscopy were used to characterize the thickness and quality of the as-grown MoS2 film, showing that the large-area MoS2 nanosheet has a smooth surface morphology constituted by small grains. Starting from the same material, both top-gated MoS2 field effect transistors and MoS2/SiO2/p-GaN heterojunction diodes were fabricated. The transistors exhibited a high on/off ratio of 105, a subthreshold swing of 74 mV dec−1, field effect mobility of 0.17 cm2 V−1 s−1, and distinctive current saturation characteristics. For the heterojunction diodes, current-rectifying characteristics were demonstrated with on-state current density of 29 A cm−2 and a current blocking property up to −25 V without breakdown. The reported transistors and diodes enabled by the same 2D/3D material stack present promising building blocks for constructing future nanoscale electronics.

Thermally oxidized 2D TaS2 as a high-κ gate dielectric for MoS2 field-effect transistors

We report a new approach to integrating high-κ dielectrics in both bottom- and top-gated MoS2 field-effect transistors (FETs) through thermal oxidation and mechanical assembly of layered two-dimensional (2D) TaS2. Combined x-ray photoelectron spectroscopy (XPS), optical microscopy, atomic force microscopy (AFM), and capacitance–voltage (C–V) measurements confirm that multilayer TaS2 flakes can be uniformly transformed to Ta2O5 with a high dielectric constant of ~15.5 via thermal oxidation, while preserving the geometry and ultra-smooth surfaces of 2D TMDs. Top-gated MoS2 FETs fabricated using the thermally oxidized Ta2O5 as gate dielectric demonstrate a high current on/off ratio approaching 106, a subthreshold swing (SS) down to 61 mV/dec, and a field-effect mobility exceeding 60 cm2 V−1 s−1 at room temperature, indicating high dielectric quality and low interface trap density.

Solution Processed Top-Gate High-Performance Organic Transistor Nonvolatile Memory With Separated Molecular Microdomains Floating-Gate

In this letter, a top-gate high-performance floating-gate organic field-effect transistor nonvolatile memory (FG-OFET-NVM), where the four-layer stacked core architecture is processed by a successive solution spin-coating method, is demonstrated. The floating-gate layer is prepared by spin-coating from a blend solution consisting of poly(styrene) (PS) and 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-Pen). As a result of phase separation, TIPS-Pen aggregates and forms many separated microdomains, which uniformly distribute in thematrix of PS as the charge-trapping sites. The optimal FG-OFET-NVM exhibits excellent memory characteristics, with a large memory window of 26 V, a desired reading voltage of 0 V, a memory ON/OFF ratio larger than 3500, programming/erasing switching endurance over 500 cycles, and good charge-storage retention with a memory ON/OFF ratio larger than 103 over 5000 s.

Selective-area growth and controlled substrate coupling of transition metal dichalcogenides

Developing a means for true bottom-up, selective-area growth of two-dimensional (2D) materials on device-ready substrates will enable synthesis in regions only where they are needed. Here, we demonstrate seed-free, site-specific nucleation of transition metal dichalcogenides (TMDs) with precise control over lateral growth by utilizing an ultra-thin polymeric surface functionalization capable of precluding nucleation and growth. This polymer functional layer (PFL) is derived from conventional photoresists and lithographic processing, and is compatible with multiple growth techniques, precursors (metal organics, solid-source) and TMDs. Additionally, we demonstrate that the substrate can play a major role in TMD transport properties. With proper TMD/substrate decoupling, top-gated field-effect transistors (FETs) fabricated with selectively-grown monolayer MoS2 channels are competitive with current reported MoS2 FETs. The work presented here demonstrates that substrate surface engineering is key to realizing precisely located and geometrically-defined 2D layers via unseeded chemical vapor deposition techniques.