Top-gate Transistors Research Articles

Effect of Back-Gate Voltage on the High-Frequency Performance of Dual-Gate MoS2 Transistors

As an atomically thin semiconductor, 2D molybdenum disulfide (MoS2) has demonstrated great potential in realizing next-generation logic circuits, radio-frequency (RF) devices and flexible electronics. Although various methods have been performed to improve the high-frequency characteristics of MoS2 RF transistors, the impact of the back-gate bias on dual-gate MoS2 RF transistors is still unexplored. In this work, we study the effect of back-gate control on the static and RF performance metrics of MoS2 high-frequency transistors. By using high-quality chemical vapor deposited bilayer MoS2 as channel material, high-performance top-gate transistors with on/off ratio of 107 and on-current up to 179 μA/μm at room temperature were realized. With the back-gate modulation, the source and drain contact resistances decrease to 1.99 kΩ∙μm at Vbg = 3 V, and the corresponding on-current increases to 278 μA/μm. Furthermore, both cut-off frequency and maximum oscillation frequency improves as the back-gate voltage increases to 3 V. In addition, a maximum intrinsic fmax of 29.7 GHz was achieved, which is as high as 2.1 times the fmax without the back-gate bias. This work provides significant insights into the influence of back-gate voltage on MoS2 RF transistors and presents the potential of dual-gate MoS2 RF transistors for future high-frequency applications.

Study on dielectric properties of PVP and Al2O3 thin films and their implementation in low-temperature solution-processed IGZO-based thin-film transistors

In the present work, we investigated the dielectric properties of solution-processed Poly-(4-vinylphenol) (PVP), and atomic layer deposited (ALD) alumina (Al2O3) thin films. Later, we integrate these dielectric materials into a thin-film transistor (TFT) device fabricated on a glass substrate using solution-processed indium gallium zinc oxide (IGZO) as a semiconductor. Both PVP and Al2O3 films show good dielectric behavior with minimum leakage and capacitance densities of 7.0 nF/cm2 and $$1.034 \times {10}^{-7}$$ F/cm2, respectively. A bottom source/drain top-gate transistor based on PVP as gate insulator operates in the linear region and demonstrates highly negative threshold voltage values beyond − 40 V. On the other hand, the bottom-gate top source/drain transistor based on Al2O3 gate dielectric demonstrates good saturation behavior with saturation current and saturation mobility of $$4.16 \times {10}^{-4}$$ A and 2.203 cm2/Vs, respectively. Further, using the photochemical activation method, the processing temperature of IGZO thin films is reduced to 325 °C from 400 °C. Low-temperature processed IGZO TFTs also show good saturation behavior with low positive threshold voltage values. However, it is achieved at the expense of saturation mobility which decreases to 0.557 cm2/Vs. Our study presents the possibility of producing organic–inorganic hybrid low-cost, and high-performance devices for upcoming flexible electronics.

Alignment of linear polymeric grains for highly stable N-type thin-film transistors

Summary Temperature-insensitive properties are attractive for most electronics, including polymeric semiconducting devices. Especially, polymeric field-effect transistors (FETs) with high mobility have been important research targets due to their broad applications. However, polymeric FETs with stable charge transport operating at extremely cold or hot zones are faced with enormous challenges. In this study, the polyacrylonitrile was found to significantly tune the sizes of pre-aggregates of polymers in solutions and the crystallinity of the polymeric films. The orientation of 5–25 μm linear grains in the films were prepared through the bar-coating process with polyacrylonitrile as an additive, which stabilized the electron mobility over a wide range of temperatures. The linear-grain morphology of the film contributed to reducing the holes and grain boundaries in the transport paths of carriers. Typically, the top-gate FETs based on P(NDI2OD-T2) displayed a stable electron transporting behavior from 200 to 460 K, with mobility greater than 3.5 cm2V−1s−1.

Exceedingly High Performance Top-Gate P-Type SnO Thin Film Transistor with a Nanometer Scale Channel Layer.

Implementing high-performance n- and p-type thin-film transistors (TFTs) for monolithic three-dimensional (3D) integrated circuit (IC) and low-DC-power display is crucial. To achieve these goals, a top-gate transistor is preferred to a conventional bottom-gate structure. However, achieving high-performance top-gate p-TFT with good hole field-effect mobility (μFE) and large on-current/off-current (ION/IOFF) is challenging. In this report, coplanar top-gate nanosheet SnO p-TFT with high μFE of 4.4 cm2/Vs, large ION/IOFF of 1.2 × 105, and sharp transistor’s turn-on subthreshold slopes (SS) of 526 mV/decade were achieved simultaneously. Secondary ion mass spectrometry analysis revealed that the excellent device integrity was strongly related to process temperature, because the HfO2/SnO interface and related μFE were degraded by Sn and Hf inter-diffusion at an elevated temperature due to weak Sn–O bond enthalpy. Oxygen content during process is also crucial because the hole-conductive p-type SnO channel is oxidized into oxygen-rich n-type SnO2 to demote the device performance. The hole μFE, ION/IOFF, and SS values obtained in this study are the best-reported data to date for top-gate p-TFT device, thus facilitating the development of monolithic 3D ICs on the backend dielectric of IC chips.

Gate Stack Engineering in MoS2 Field‐Effect Transistor for Reduced Channel Doping and Hysteresis Effect

Abstract2D transition metal dichalcogenides (TMDs) are promising semiconductive films for applications in future devices due to their prosperous and tunable band structures. However, most TMD‐based top gate transistors suffer from a significant doping effect in the channel due to the subsequent deposition high‐k dielectric layer and metal gate, which limits their practical applications. In this work, the channel doping effect caused by various processing steps based on mechanical exfoliated MoS2 sheets is systematically investigated. This work illustrates a clear correlation among these steps and provides a simple and efficient methodology to realize high‐performance enhancement mode MoS2 field effect transistors, which can be extended to other 2D materials.

Uniform High-k Amorphous Native Oxide Synthesized by Oxygen Plasma for Top-Gated Transistors.

The integration of high-k gate dielectrics with two-dimensional (2D) semiconducting channel materials is essential for high-performance and low-power electronics. However, the conformal deposition of a uniform high-k dielectric with sub-1 nm equivalent oxide thickness (EOT) and high interface quality on high-mobility 2D semiconductors is still challenging. Here, we report a facile approach to synthesize a uniform high-k (εr ∼ 22) amorphous native oxide Bi2SeOx on the high-mobility 2D semiconducting Bi2O2Se using O2 plasma at room temperature. The conformal native oxide can directly serve as gate dielectrics with EOT of ∼0.9 nm, while the original properties of underlying 2D Bi2O2Se is preserved. Furthermore, high-resolution area-selective oxidation of Bi2O2Se is achieved to fabricate discrete electronic components. This facile integration of a high-mobility 2D semiconductor and its high-k native oxide holds high promise for next-generation nanoelectronics.

Improving the electrical performance of monolayer top-gated MoS2 transistors by post bis(trifluoromethane) sulfonamide treatment

Due to the large surface to volume ratio of two-dimensional (2D) materials, the electrical performance of MoS2 is very sensitive to extrinsic ambient conditions. Post treatments are favorable to improve or recover the electrical performance of MoS2. In this work, the influence of post forming gas annealing (FGA) and bis(trifluoromethane) sulfonamide (TFSI) treatment on the electrical performance of monolayer top-gated MoS2 transistors is investigated. A negative shift of threshold voltage and an improvement in electron mobility are observed for both the post FGA and TFSI treatment. However, post TFSI treatment is more effective than the post FGA treatment in improving the electron mobility and gate controllability. Linear transmission-line-model measurement results indicate that the post FGA treatment is preferable in reducing the contact resistance, while post TFSI treatment is more effective in reducing the sheet resistance of MoS2. Raman and x-ray photoelectron spectroscopy reveal that water desorbs from MoS2 after the FGA and TFSI treatment and S vacancies are introduced into MoS2 after FGA. The results show that post TFSI treatment can be a simple and effective approach to improve the electrical property of MoS2 and may be used for other S-containing 2D transition metal dichalcogenides.

Channel-protecting fabrication of top-gate MoS2 transistor arrays

The surface passivation on MoS2 and other transition metal dichalcogenides (TMDs) has been widely studied and utilized to prevent contamination and oxygen/water vapor penetration. Such approaches are mostly applied on the back-gate transistors after the formation of source/drain electrodes, while the compatibility in constructing top-gate devices has not yet been experimentally explored. Here, based on the large-area MoS2 thin film prepared with the atomic layer deposition technique, we developed an experimental routine to fabricate top-gate MoS2 thin-film transistor arrays with the TMD channel protected by high-k dielectric during the entire device fabrication process. The channel protection is enabled by the high-quality Al2O3 dielectric with proper pretreatment. The transistors in the array have shown enhanced electrical performance compared to the non-protected devices. Such a robust and well-controlled fabrication technique is a typical case of developing functional electronic devices by leveraging the strength of top-down lithography and the unique advantage of bottom-up growth, which can be further extended to the wide application in higher-level systems based on TMD materials.

Native Oxide Seeded Spontaneous Integration of Dielectrics on Exfoliated Black Phosphorus.

Two-dimensional (2D) semiconductors have been a central focus for next-generation electronics and optoelectronics owing to their great potential to extend the scaling limits in a silicon transistor. However, due to the lack of surface dangling bonds in most 2D semiconductors, such as graphene and transition metal dichalcogenides (TMDs), the direct growth of the high-κ film on these 2D materials via an atomic layer deposition (ALD) technique often produces dielectrics with poor quality, which hinders their integration in the modern semiconductor industry. Here, we comprehensively investigate the ALD growth of the Al2O3 layer on 2D exfoliated black phosphorus (BP). Intriguingly, we found that the 2D BP with "silicon-like" characteristics possesses a native surface oxide layer PxOy after air exposure. The PxOy-induced surface dangling bonds enable the spontaneous integration of the high-quality Al2O3 layer on the BP flake without any pretreatments to functionalize the surface. Additionally, the Al2O3 layer could effectively passivate BP to prevent its degradation in ambient conditions, which addresses the most serious problem of the BP material. Moreover, the Al2O3-encapsulated BP field-effect transistor (FET) exhibits good electrical transport performance, with a high hole mobility of ∼420 cm2 V-1 s-1 and electron mobility of ∼80 cm2 V-1 s-1. Moreover, the high-quality Al2O3 layer can also be integrated into the top-gated BP transistor and inverter. Our findings reveal the silicon-like characteristics of BP for the high-κ ALD dielectric growth technology, which promises the seamless integration of 2D BP in the modern semiconductor industry.

Tungsten Diselenide Top-gate Transistors with Multilayer Antimonene Electrodes: Gate Stacks and Epitaxially Grown 2D Material Heterostructures

We have demonstrated that with e-beam deposition of a thin Al2O3 layer before atomic layer deposition, a uniform Al2O3 film can be obtained on WSe2/sapphire samples. Device performances are observed for WSe2 top-gate transistors by using oxide stacks as the gate dielectric. By using thermal evaporation, epitaxially grown multilayer antimonene can be prepared on both MoS2 and WSe2 surfaces. With multilayer antimonene as the contact metal, a significant increase in drain currents and ON/OFF ratios is observed for the device, which indicates that high contact resistance between metal/2D material interfaces is a critical issue for 2D devices. The observation of multilayer antimonene grown on different 2D material surfaces has demonstrated less dependence on the substrate lattice constant of the unique van der Waals epitaxy for 2D materials. The results have also demonstrated that stacking 2D materials with different materials plays an important role in the practical applications of 2D devices.

Mobility improvement in CVD graphene by using local metal side-gate

It has been anticipated that using a side-gate helps in the improvement of mobility over more common top-gate or back-gate graphene transistors. In this work, we presented a method of quantifying the mobility improvement. Transistors are fabricated using chemical vapour deposition graphene on SiO2/Si substrate. Characteristics of two graphene transistors with slightly different geometry are presented. The transistors are fabricated with both, a back-gate and a side-gate. Using results from experiment and technology computer-aided design simulations, field effect mobility of majority carriers (holes) is calculated by two methods. It has been observed that switching from back-gate to side-gate operation on the same transistor results in a mobility improvement of at least 1.64 times. Simulation results presented in this work exhibit a non-perpendicular direction of majority side-gate electric field induced to the two-dimensional graphene channel. This could be one of the reasons behind the mobility improvement. Because in both cases (back-gate and side-gate) the graphene channel is in contact with ambient air on top and SiO2 substrate on bottom.

Long-term stability of multilayer MoS2 transistors with mica gate dielectric

To avoid surface damage of a MoS2 channel, a mica flake with high permittivity and atomically flat surface was dry transferred onto a multilayer MoS2 flake to prepare top-gated transistors. For the first time, the interface properties of mica/MoS2 and the long-term stability of devices were investigated when the transistors were exposed to ambient air. Results show that the electrical performance of the transistors is degraded significantly when the devices are exposed to ambient moisture for a long time, due to the strong hydrophilism of mica. The transfer curves of the transistors cannot be recovered to their initial states even after annealing. The adsorbed moisture can become trapped at the interface between the MoS2 channel and mica dielectric or on the MoS2 surface, resulting in enhanced carrier scattering and degraded device performance. However, the top-gated MoS2 transistor with Al2O3 encapsulation exhibits enhanced stability even after annealing or exposure to atmosphere for 200 days. The excellent stability should be attributed to the effective insulation of moisture from the ambient air by Al2O3 encapsulation. Therefore, a dense and hydrophobic encapsulation layer is indispensable for stable and high-performance top-gated MoS2 transistors with mica gate dielectric.

High-Mobility Flexible Oxyselenide Thin-Film Transistors Prepared by a Solution-Assisted Method.

Two-dimensional (2D) semiconductors hold great promise in flexible electronics because of their intrinsic flexibility and high electrical performance. However, the lack of facile synthetic and subsequent device fabrication approaches of high-mobility 2D semiconducting thin films still hinders their practical applications. Here, we developed a facile, rapid, and scalable solution-assisted method for the synthesis of a high-mobility semiconducting oxyselenide (Bi2O2Se) thin film by the selenization and decomposition of a precursor solution of Bi(NO3)3·5H2O. Simply by changing the rotation speed in spin-coating of the precursor solution, the thicknesses of Bi2O2Se thin films can be precisely controlled down to few atomic layers. The as-synthesized Bi2O2Se thin film exhibited a high Hall mobility of ∼74 cm2 V-1 s-1 at room temperature, which is much superior to other 2D thin-film semiconductors such as transition metal dichalcogenides. Remarkably, flexible top-gated Bi2O2Se transistors showed excellent electrical stability under repeated electrical measurements on flat and bent substrates. Furthermore, Bi2O2Se transistor devices on muscovite substrates can be readily transferred onto flexible polyvinyl chloride (PVC) substrates with the help of thermal release tape. The integration of a high-mobility thin-film semiconductor, excellent stability, and easy transfer onto flexible substrates make Bi2O2Se a competitive candidate for future flexible electronics.

Black Phosphorus High-Frequency Transistors with Local Contact Bias.

Having a sizable band gap and high carrier mobility, black phosphorus (BP) is a promising two-dimensional material for high-frequency electronic and optoelectronic devices. Further, for metal-oxide-semiconductor field-effect transistors (MOSFETs) operating at high frequencies, they must have a top gate of submicron length instead of the commonly used global back gate. However, without the global back gate to electrostatically induce doping in BP, top-gated submicron BP MOSFETs have not reached their full potential mainly due to large contact resistances. Here, we report top-gated submicron BP MOSFETs with local contact bias electrodes to induce doping in the contact region. This resulted in reduced contact resistance and, in turn, orders of magnitude improvement in current capacity (>500 μA/μm) and peak transconductance (>40 μS/μm), if compared with top-gated BP transistors without any back-gating scheme. In turn, these improvements resulted in a forward current gain cutoff frequency of 37 GHz and a maximum frequency of oscillation of 22 GHz at room temperature, the highest reported for BP MOSFETs up to date.

Performance enhancement of monolayer MoS2 transistors by atomic layer deposition of high-k dielectric assisted by Al2O3 seed layer

In this work, thermal atomic layer deposition (ALD) of HfO2 on monolayer (ML) MoS2 with 1 nm Al2O3 seed layer by e-beam evaporation was explored. With the 1 nm Al2O3 seed layer, a uniform HfO2 layer can be deposited on the ML MoS2 with bare influence on the ML MoS2 structure. After coating a uniform HfO2, abundant electrons are accumulated in MoS2 and SiO2 resulting in a high on/off current ratio of ~109 and a dramatic reduction of subthreshold swing (SS) from 1943 to 168 mV/dec of back-gated ML MoS2 transistor on 300 nm SiO2. A low SS of 103 mV/dec was further obtained from top-gated transistor with ~23.3 nm HfO2 as the gate oxide. The results manifest the beneficial influence of using 1 nm Al2O3 on the electrical performance of ML MoS2 transistors, suggesting a feasible strategy for ALD of high-k dielectric layer on ML 2D materials.

Graphene/fluorographene heterostructure for nano ribbon transistor channel

4H-SiC multilayer graphene/fluorographene heterostructures have been implemented to fabricate a 40 nm transistor channel. The plasma-assisted fluorination process with a carbon-to-fluorine ratio of ∼1 allows the passivation of the sidewalls with a substantial reduction in the channel width to form multilayer graphene nanoribbons (GNRs). A graphene channel is completely embedded in the passivated top and sidewalls of graphene. the gate leakage is in the nanoampere range, which makes the fluorinated dielectric robust enough for tunnel barrier. We have fabricated top gate transistors using this heterostructure and demonstrated the onset of rectification using this process. Despite the limited on/off ratio, I–V characteristics of GNRs of 40 nm channel width show a clear improvement compared to 50 μm device indicating that this process is a potential route to pattern nanoribbons.

Stability of pentacene-based top gate thin film transistor with thick parylene as dielectric under humid environment

This study presents the influence of humidity effect in top gate transistors using pentacene as active layer. The devices are made on a planarized kapton substrate, and 1 μm thick parylene has been used both as gate dielectric and encapsulating layer. Two series of measurement conditions have been used. First, the humidity rate was varied from 0 to 90% in a cell by setting exposure times of 15 min and device characterized, followed to 15 min vacuum. Secondly, humidity rate is fixed at 90% during 144 min and the electrical characteristics recorded successively. The main electrical parameters such as threshold voltage (VT), mobility (μ), on-current (Ion), depletion current (Ioff) and subthreshold slope (S) have been investigated. The results showed that only the electrical parameters in subthreshold region have been affected at different relative humidity (RH) levels for the first series. Under vacuum, the device exhibited stable electrical performances whereas in RH ranging from 24% to 90% we observe an increase of depletion current, and this Ioff increase was found to be reversible. After exposing the device with 90% of RH (second series), from 0 to 108 min in humid environment, threshold voltage, Ion current, VT and charge carrier mobility remain unchanged while Ioff and S are highly affected. Beyond 108 min, Ioff current keeps increasing with a noticeable Ion current degradation. Two effects have to be taken into account: (i) Ioff current increase without any change in on-state regime is the consequence of cumulative effect of Leakage current increase in the parylene dielectric and electrical conductivity increase in pentacene semiconductor, (ii) Ion current decrease is the consequence of absorbed water molecule diffusing and interacting with pentacene. All these parameters are reversible under vacuum after pumping down.

Improved performance of top-gated multilayer MoS2 transistors with channel fully encapsulated by Al2O3 dielectric

Multilayer two-dimensional molybdenum disulfide (MoS2) field-effect transistors with Al2O3 or HfO2 as top gate dielectric and bottom passivation layer have been comparatively studied. The top-gated MoS2 transistor with Al2O3 as both top gate dielectric and bottom passivation layer exhibits excellent electrical characteristics with an on-off ratio of ∼106, a subthreshold swing of 97 mV dec−1, a low interface-trap density of 1.66×1012 cm−2eV−1, and a high field-effect mobility of 105 cm2 V−1 s−1. All these should be attributed to superior interface quality between Al2O3 top gate dielectric and MoS2, and enhanced dielectric screening effect due to Al2O3 bottom passivation layer.

Hysteresis control by varying Ta2O5-nanoparticles concentration in PMMA-Ta2O5 bilayer gate dielectric of hybrid-organic thin film transistors

Abstract In this paper, we report the fabrication of a series of top-gate bottom-contact hybrid organic thin film transistors based on solution-processed semiconductors and dielectric layers on a glass substrate. Semiconductor active layers were based on a mixture of [6,6]-phenyl C61-butyric acid methyl ester (PCBM) mixture and poly (3-hexylthiophene) (P3HT), whereas gate dielectric layers were based on PMMA mixed with various concentrations of high-k Ta2O5 inorganic particles. Experimental investigation indicated that the hysteresis phenomenon of the devices can be governed by changing of the Ta2O5 concentration in PMMA-Ta2O5 nanocomposites gate dielectric layer. In addition, significant enhancement of electron transport was also observed with the increase of Ta2O5 inorganic particles concentration in the gate layer, which arises from the change of the charge transport from unipolar to ambipolar type. The fabricated OTFTs, with significant hysteresis variation as a function of Ta2O5 nanoparticles content in PMMA-Ta2O5 gate dielectrics, prove particularly promising in consideration of possible use for low-cost nonvolatile memory elements and sensing array applications.

Damage-free mica/MoS2 interface for high-performance multilayer MoS2 field-effect transistors

For top-gated MoS2 field-effect transistors, damaging the MoS2 surface to the MoS2 channel are inevitable due to chemical bonding and/or high-energy metal atoms during the vacuum deposition of gate dielectric, thus leading to degradations of field-effect mobility (μFE) and subthreshold swing (SS). A top-gated MoS2 transistor is fabricated by directly transferring a 9 nm mica flake (as gate dielectric) onto the MoS2 surface without any chemical bonding, and exhibits excellent electrical properties with an on–off ratio of ∼108, a low threshold voltage of ∼0.2 V, a record μFE of 134 cm2 V−1 s−1, a small SS of 72 mV dec−1 and a low interface-state density of 8.8 × 1011 cm−2 eV−1, without relying on electrode-contact engineered and/or phase-engineered MoS2. Although the equivalent oxide thickness of the mica dielectric is in the sub-5 nm regime, enhanced stability characterized by normalized threshold voltage shift (1.2 × 10−2 V MV−1 cm−1) has also been demonstrated for the transistor after a gate-bias stressing at 4.4 MV cm−1 for 103 s. All these improvements should be ascribed to a damage-free MoS2 channel achieved by a dry transfer of gate dielectric and a clean and smooth surface of the mica flake, which greatly decreases the charged-impurity and interface-roughness scatterings. The proposed transistor with low threshold voltage and high stability is highly desirable for low-power electronic applications.