Top-gate Field-effect Transistors Research Articles

Improvement of N-type carbon nanotube field effect transistor performance using the combination of yttrium diffusion layer in HfO2 dielectrics and metal contacts.

In this paper, we obtained n-type top-gate carbon nanotube thin film field effect transistors (CNTFET) with source/drain extensions structure through dielectrics optimization strategy, combining the yttrium layer with HfO2 dielectric argon annealing process and metal contacts. The mechanism for enhanced n-type conduction was explained as being due to the vertical diffusion of yttrium to the HfO2 dielectric during argon annealing. This diffusion causes abending of the energy band, which results in more positive fixed charges and a reduction in the electron injection barrier between the low work function source-drain Cr electrode and carbon nanotube. The optimized technology has great prospects for the low cost, large scale and high performance n-type CNTFET to be used in integrated electronic devices.&#xD.

Flexible p-Type WSe2 Transistors with Alumina Top-Gate Dielectric.

Tungsten diselenide (WSe2) field-effect transistors (FETs) are promising for emerging electronics because of their tunable polarity, enabling complementary transistor technology, and their suitability for flexible electronics through material transfer. In this work, we demonstrate flexible p-type WSe2 FETs with absolute drain currents |ID| up to 7 μA/μm. We achieve this by fabricating flexible top-gated FETs with a combined WSe2 and metal contact transfer approach using WSe2 grown by metal-organic chemical vapor deposition on sapphire. Despite moderate WSe2 crystal grain size, our devices show similar or higher |ID| and ID on/off ratio (∼105) compared to most devices with exfoliated single-crystal WSe2 from the literature. We analyze charge trapping in our devices using pulsed and bias stress measurements. Notably, the high |ID| values are preserved during pulsing, where charge trapping is minimized. Overall, we demonstrate a fabrication approach advantageous for high drain currents in flexible 2D transistors.

Achieving High-Performance Polymer-Wrapper-Free Aligned Carbon Nanotube Field-Effect Transistors Through Degradable Polymer Wrapping and Efficient Removal Techniques.

Semiconducting carbon nanotubes (s-CNTs) have emerged as a promising alternative to traditional silicon for ultrascaled field-effect transistors (FETs), owing to their exceptional properties. Aligned s-CNTs (A-CNTs) are particularly favored for practical applications due to their ability to provide higher driving current and lower contact resistance compared with individual s-CNTs or random networks. Achieving high-semiconducting-purity A-CNTs typically involves conjugated polymer wrapping for selective separation of s-CNTs, followed by self-assembly techniques. However, the presence of the polymer wrapper on A-CNTs can adversely impact electrical contact, gating efficiency, carrier transport, and device-to-device variations, necessitating its complete removal. While various methods have been explored for polymer removal, accurately characterizing the extent of removal remains a challenge. Traditional techniques such as absorption spectroscopy and X-ray photoelectron spectroscopy (XPS) may not accurately depict the remaining polymer content on A-CNTs due to their inherent detection limits. Consequently, the performance of FETs based on pure polymer-wrapper-free A-CNTs is unclear. In this study, we present an approach for preparing high-semiconducting-purity and polymer-wrapper-free A-CNTs using poly[(9,9-dioctylfluorenyl-2,7-dinitrilomethine)-(9,9-dioctylfluorenyl-2,7-dimethine)] (PFO-N-PFO), a degradable polymer, in conjunction with a modified dimension-limited self-alignment process (m-DLSA). Comprehensive transmission electron microscopy (TEM) characterizations, complemented by absorption and XPS characterizations, provide robust evidence of the successful near-complete removal of the polymer wrapper via a cleaning procedure involving acidic degradation, hot solvent rinsing, and vacuum annealing. Furthermore, top-gated FETs based on these high-semiconducting-purity and polymer-wrapper-free A-CNTs exhibit good performance metrics, including an on-current (Ion) of 2.2 mA/μm, peak transconductance (gm) of 1.1 mS/μm, low contact resistance (Rc) of 191 Ω·μm, and negligible hysteresis, representing a significant advancement in the CNT-based FET technology.

P/N-Type Conversion of 2D MoTe2 Controlled by Top Gate Engineering for Logic Circuits.

Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) are regarded as promising materials for next-generation logic circuits. Top gate field-effect transistors (FETs) have independent gate control ability and can be fabricated directly on TMDC materials without a transfer process. Therefore, it has the merits of device reliability and complementary metal-oxide semiconductor (CMOS) process compatibility, which are demanded in practical circuit-level integration. However, the fabrication of the top gate FET involves depositing an insulating dielectric layer and a gate electrode in sequence on the TMDC channel material, which may affect the device performance. Insightfully investigating the influences of different top-gate-deposition methods on the electrical properties of the TMDC channel and further harnessing these influences to realize a homogeneous CMOS device on an identical 2D TMDC platform are with practice significance. In this work, p/n-type controllable top gate FET arrays based on 2H-MoTe2 are fabricated by using different top-gate-deposition methods. The electron-beam evaporation (EBE) of top metal gate exhibits an obvious n-doping effect on the 2H-MoTe2 channel and converts it from p-type to n-type, whereas the thermal evaporation of top gate affects little to the channel. High-resolution transmission electron microscopy (HR-TEM) analysis reveals that the high-energy metal atoms from the EBE process can penetrate through the 30 nm gate dielectric layers (including 10 nm Al2O3 seeding layer), leading to multiple atomic defects in both MoTe2 and the interface between MoTe2 and Al2O3. Furthermore, by utilizing the top gate engineering, a large-scale double-top-gate MoTe2 homogeneous CMOS inverter array is fabricated. The CMOS inverters exhibit clear logic swing, negligible hysteresis, and high device yield (∼93%), indicating high device reliability and stability. Notably, the fabrication process is facile, free from transfer procedure, and compatible with traditional silicon technology. This work promotes the application of 2D TMDCs in nanoelectronics integration.

High Mobility Transistors and Flexible Optical Synapses Enabled by Wafer-Scale Chemical Transformation of Pt-Based 2D Layers.

Electronic devices employing two-dimensional (2D) van der Waals (vdW) transition-metal dichalcogenide (TMD) layers as semiconducting channels often exhibit limited performance (e.g., low carrier mobility), in part, due to their high contact resistances caused by interfacing non-vdW three-dimensional (3D) metal electrodes. Herein, we report that this intrinsic contact issue can be efficiently mitigated by forming the 2D/2D in-plane junctions of 2D semiconductor channels seamlessly interfaced with 2D metal electrodes. For this, we demonstrated the selectively patterned conversion of semiconducting 2D PtSe2 (channels) to metallic 2D PtTe2 (electrodes) layers by employing a wafer-scale low-temperature chemical vapor deposition (CVD) process. We investigated a variety of field-effect transistors (FETs) employing wafer-scale CVD-2D PtSe2/2D PtTe2 heterolayers and identified that silicon dioxide (SiO2) top-gated FETs exhibited an extremely high hole mobility of ∼120 cm2 V-1 s-1 at room temperature, significantly surpassing performances with previous wafer-scale 2D PtSe2-based FETs. The low-temperature nature of the CVD method further allowed for the direct fabrication of wafer-scale arrays of 2D PtSe2/2D PtTe2 heterolayers on polyamide (PI) substrates, which intrinsically displayed optical pulse-induced artificial synaptic behaviors. This study is believed to vastly broaden the applicability of 2D TMD layers for next-generation, high-performance electronic devices with unconventional functionalities.

A scalable top-gate graphene field effect transistor with a polydimethylsiloxane dielectric

The limitations of modern CMOS technology have created a call to action for novel devices with great scalability potential. Graphene has been recognized as a suitable material for an enhanced transistor channel based on its incredibly large conductivity while also being easily scaled. Previous research has noted the importance of a top gate device structure, which is difficult to accomplish for graphene transistors due to graphene's incompatibility with oxide growth processes. A novel process flow for graphene field effect transistors with scalability is presented. The emphasis is on the growth of multilayer graphene using chemical vapor deposition and the implementation of polydimethylsiloxane as a gate dielectric. Polydimethylsiloxane gate insulator thickness of 815 nm and 570 nm were successfully developed on 4in large-scale wafers. Two devices of similar channel dimensions and different dielectric were compared and mobilities of 14.57cm2V−1s−1 and 0.44 cm2V−1s−1 were measured. Gate voltage sweeps from -20 V to 20 V also demonstrated channel current modulation with a charge neutrality point between 5 V and 8 V, indicating achievement of expected device operation.

Study of High-Energy Proton Irradiation Effects in Top-Gate Graphene Field-Effect Transistors

In this article, the effects of high-energy proton irradiation on top-gate graphene field-effect transistors (GFETs) were investigated by using 20 MeV protons. The basic electrical parameters of the top-gate GFETs were measured before and after proton irradiation with a fluence of 1 × 1011 p/cm2 and 5 × 1011 p/cm2, respectively. Decreased saturation current, increased Dirac sheet resistance, and negative drift in the Dirac voltage in response to proton irradiation were observed. According to the transfer characteristic curves, it was found that the carrier mobility was reduced after proton irradiation. The analysis suggests that proton irradiation generates a large net positive charge in the gate oxide layer, which induces a negative drift in the Dirac voltage. Introducing defects and increased impurities at the gate oxide/graphene interface after proton irradiation resulted in enhanced Coulomb scattering and reduced mobility of the carriers, which in turn affects the Dirac sheet resistance and saturation current. After annealing at room temperature, the electrical characteristics of the devices were partially restored. The results of the technical computer-aided design (TCAD) simulation indicate that the reduction in carrier mobility is the main reason for the degradation of the electrical performance of the device. Monte Carlo simulations were conducted to determine the ionization and nonionization energy losses induced by proton incidence in top-gate GFET devices. The simulation data show that the ionization energy loss is the primary cause of the degradation of the electrical performance.

Top-gate engineering of field-effect transistors based on single layers of MoS2 and graphene

Field-effect transistors (FETs) were fabricated with use of vertical heterostructures of graphene and MoS2 monolayers with top-gate and back-gate configurations. Nanodiamonds/poly(vinylidene difluoride) (1:1) and SiO2 were used as the top-gate and back-gate dielectric, respectively. The novel top-gate electrode and gate dielectric assembly consisting of polyaniline and nanodiamonds/poly(vinylidene difluoride) were synthesized by a chemical oxidative polymerization approach. Our MoS2 FETs showed a high linear mobility of approximately 212 cm2/V s and a high on/off current ratio of up to 107 at 10 V for top-gated FETs, which is much greater than for conventional back-gated FETs. The devices were stable under elevated temperatures up to 100 °C, with a decrease in the on/off current ratio. The devices showed good stability without any additional encapsulation after an elapsed time of 10 days, as the results on the first and tenth days were identical. This work will pave the way for the design of high-performance FETs for applications in electronics and optoelectronics.

Three-Dimensional Surface Treatment of MoS2 Using BCl3 Plasma-Derived Radicals.

The realization of next-generation gate-all-around field-effect transistors (FETs) using two-dimensional transition metal dichalcogenide (TMDC) semiconductors necessitates the exploration of a three-dimensional (3D) and damage-free surface treatment method to achieve uniform atomic layer-deposition (ALD) of a high-k dielectric film on the inert surface of a TMDC channel. This study developed a BCl3 plasma-derived radical treatment for MoS2 to functionalize MoS2 surfaces for the subsequent ALD of an ultrathin Al2O3 film. Microstructural verification demonstrated a complete coverage of an approximately 2 nm-thick Al2O3 film on a planar MoS2 surface, and the applicability of the technique to 3D structures was confirmed using a suspended MoS2 channel floating from the substrate. Density functional theory calculations supported by optical emission spectroscopy and X-ray photoelectron spectroscopy measurements revealed that BCl radicals, predominantly generated by the BCl3 plasma, adsorbed on MoS2 and facilitated the uniform nucleation of ultrathin ALD-Al2O3 films. Raman and photoluminescence measurements of monolayer MoS2 and electrical measurements of a bottom-gated FET confirmed negligible damage caused by the BCl3 plasma-derived radical treatment. Finally, the successful operation of a top-gated FET with an ultrathin ALD-Al2O3 (∼5 nm) gate dielectric film was demonstrated, indicating the effectiveness of the pretreatment.

Geometrical Characterisation of TiO2-rGO Field-Effect Transistor as a Platform for Biosensing Applications.

The performance of the graphene-based field-effect transistor (FET) as a biosensor is based on the output drain current (Id). In this work, the signal-to-noise ratio (SNR) was investigated to obtain a high-performance device that produces a higher Id value. Using the finite element method, a novel top-gate FET was developed in a three-dimensional (3D) simulation model with the titanium dioxide-reduced graphene oxide (TiO2-rGO) nanocomposite as the transducer material, which acts as a platform for biosensing application. Using the Taguchi mixed-level method in Minitab software (Version 16.1.1), eighteen 3D models were designed based on an orthogonal array L18 (6134), with five factors, and three and six levels. The parameters considered were the channel length, electrode length, electrode width, electrode thickness and electrode type. The device was fabricated using the conventional photolithography patterning technique and the metal lift-off method. The material was synthesised using the modified sol-gel method and spin-coated on top of the device. According to the results of the ANOVA, the channel length contributed the most, with 63.11%, indicating that it was the most significant factor in producing a higher Id value. The optimum condition for the highest Id value was at a channel length of 3 µm and an electrode size of 3 µm × 20 µm, with a thickness of 50 nm for the Ag electrode. The electrical measurement in both the simulation and experiment under optimal conditions showed a similar trend, and the difference between the curves was calculated to be 28.7%. Raman analyses were performed to validate the quality of TiO2-rGO.

Wafer-scale floating-gate field effect transistor sensor built on carbon nanotubes film for Ppb-level NO2 detection

NO2 is served as an air pollutant and a specific biomarker for disease diagnosis, which becomes a major detection object in environmental protection and health medical fields. Transition metal dichalcogenides (TMDs) materials have attracted considerable attention for their ability to detect NO2 without heating conditions. The requirements in the above fields for the lower limit of NO2 concentration detection are as low as ppb-level, but the trace gas is difficult to cause the large electrical signal changes, which becomes the bottleneck for TMDS materials in NO2 detection. Moreover, TMDs-based conductance sensors are susceptible to humidity interference at room temperature, which also have challenges in device size, batch fabrication, and reproducibility. How to achieve miniaturization and integration of TMDs-based gas sensors will provide a boost to portable detection of NO2 in environmental protection and health medical fields. Herein, on the basis of the principle of top-gate field effect transistor (FET), a strategy of using gas-sensing materials as the floating-gate (FG) in FET sensor is proposed to realize the detection of trace gas. The channel, dielectric layer, and FG are formed by carbon nanotubes, Y2O3, and Pd/WS2 respectively. The unique amplification effect of carbon-based FET on the gas-sensing signal is utilized to achieve NO2 detection down to 20 ppb. Furthermore, visible-light-assisted detection mode is applied to the FG FET sensor, achieving stable anti-humidity property and 100% recoverability at 10%–70% RH. We expect our work can provide a significant approach to developing micro gas sensor chips for environmental detection and portable medical applications.

Switching limits of top-gated carbon nanotube field-effect transistors

The performance limits of carbon nanotube field-effect transistors (CNFETs) based on a recently reported process are studied by computational techniques at temperatures between 300 K and 4 K. The impact of band-to-band tunneling (BTBT) and source-to-drain tunneling (SDT) is examined for devices with varying gate length through the use of simulations based on the non-equilibrium Green’s function (NEGF) formalism, and calibrated to measurements. Additionally, the case of junctionless chemical doping profiles is analyzed in contrast to electrostatic doping recently reported for test structures. The switching limits of CNFETs are further explored for devices based on carbon nanotubes (CNTs) with more favorable electronic structures.

Impact of Dielectric Environment on Trion Emission from Single-Walled Carbon Nanotube Networks.

Trions are charged excitons that form upon optical or electrical excitation of low-dimensional semiconductors in the presence of charge carriers (holes or electrons). Trion emission from semiconducting single-walled carbon nanotubes (SWCNTs) occurs in the near-infrared and at lower energies compared to the respective exciton. It can be used as an indicator for the presence of excess charge carriers in SWCNT samples and devices. Both excitons and trions are highly sensitive to the surrounding dielectric medium of the nanotubes, having an impact on their application in optoelectronic devices. Here, the influence of different dielectric materials on exciton and trion emission from electrostatically doped networks of polymer-sorted (6,5) SWCNTs in top-gate field-effect transistors is investigated. The observed differences of trion and exciton emission energies and intensities for hole and electron accumulation cannot be explained with the polarizability or screening characteristics of the different dielectric materials, but they show a clear dependence on the charge trapping properties of the dielectrics. Charge localization (trapping of holes or electrons by the dielectric) reduces exciton quenching, emission blue-shift and trion formation. Based on the observed carrier type and dielectric material dependent variations, the ratio of trion to exciton emission and the exciton blue-shift are not suitable as quantitative metrics for doping levels of carbon nanotubes.

A Monolayer MoS2 FET with an EOT of 1.1nm Achieved by the Direct Formation of a High-κ Er2 O3 Insulator Through Thermal Evaporation.

Achieving the direct growth of an ultrathin gate insulator with high uniformity and high quality on monolayer transition metal dichalcogenides (TMDCs) remains a challenge due to the chemically inert surface of TMDCs. Although the main solution for this challenge is utilizing buffer layers before oxide is deposited on the atomic layer, this method drastically degrades the total capacitance of the gate stack. In this work, weconstructed a novel direct high-κ Er2 O3 deposition system based on thermal evaporation in a differential-pressure-type chamber. A uniform Er2 O3 layer with an equivalent oxide thickness of 1.1nm wasachieved as the gate insulator for top-gated MoS2 field-effect transistors (FETs). The top gate Er2 O3 insulator without the buffer layer on MoS2 exhibited a high dielectric constant that reached 18.0, which is comparable to that of bulk Er2 O3 and is the highest among thin insulators (< 10nm) on TMDCs to date. Furthermore, the Er2 O3 /MoS2 interface (Dit ≈ 6 × 1011 cm-2 eV-1 ) is confirmed to be clean and is comparable with that of the h-BN/MoS2 heterostructure. These results prove that high-quality dielectric properties with retained interface quality can be achieved by this novel deposition technique, facilitating the future development of 2D electronics.

TETHYS: A simulation tool for graphene hydrodynamic models

We present a simulation tool, TETHYS (i.e., Two-dimensional Emitter of THz, Hydrodynamic Simulation), developed with the aim of studying hydrodynamic models for electronic transport in graphene, being particularly tailored for the simulation of the configuration of top-gated graphene field-effect transistors (GFET) near room temperature. We present the model governing the system and briefly discuss its validity and physical parameters; then we proceed to discuss the algorithms and numerical methods used in its implementation, namely, two-step Richtmyer and weighted forward-time centred-space schemes, which address the hyperbolic and parabolic parts of the model, respectively. An abridged usage guide and description of the output are also provided, as well as two illustrative simulation cases: the Dyakonov–Shur instability and the boundary layer of pulsatile electric flow. The simulation program here brought forward is uncomplicated and lightweight, yet robust and accurate, having a wide variety of applicable scenarios and configurations to explore. Program summaryProgram Title: TETHYSCPC Library link to program files:https://doi.org/10.17632/s28zwgpnpw.1Developer's repository link:github.com/pcosme/TETHYS-Graphene-Hydrodynamic-SimulationLicensing provisions: MITProgramming language: C++Nature of problem: The main objective of this code is to simulate and analyse the electronic conduction on gated (mono-layer) graphene resorting to a hydrodynamic model [1]. Note that, given the Dirac-like dispersion relation of such material, the mass of the carriers is ill-defined; and, in fact, the mass of the fluid element varies with the number density, which sets this system apart from other 2D electron fluids [2]. The model assumes enough doping, so that only one kind of carriers, electrons or holes, participates in the dynamics of the system. Moreover, the simulation is limited to the fully degenerate limit.Thus, these assumptions correspond to the situation of a regular GFET and this application can be used to explore atypical phenomena arising from the effects of uniform and static magnetic field and Hall viscosity, and even spatially non-uniform gate capacitance.Furthermore, this software was designed with the intent of examining unstable nonlinear modes that may lead to the emission of radiation in the THz range [3].Solution method: The fluid equations (continuity, momentum and energy transport) are solved with a split-operator technique, with a second-order finite-volume Lax–Wendroff method [4] for the hyperbolic part and a forward-time centred-space of second-order stencil to tackle the dissipation and heat diffusion. That is, the fields of number density, velocity/momentum density and temperature are calculated over a rectangular grid and stored at a HDF5 file for further processing.Then, the obtained field profiles are used to compute the relevant macroscopic electronic quantities, such as drain-to-source current or dissipated power, and, particularly, the electric dipole moment of the charge distribution, which can subsequently be used to characterize the emitted far-field radiation. This is mostly done by numerically integrating the data in space, with the necessary time derivatives obtained by Gaussian convolution.

Pass-Transistor Logic Circuits Based on Wafer-Scale 2D Semiconductors.

2D semiconductors, such as molybdenum disulfide (MoS2 ), have attracted tremendous attention in constructing advanced monolithic integrated circuits (ICs) for future flexible and energy-efficient electronics. However, the development of large-scale ICs based on 2D materials is still in its early stage, mainly due to the non-uniformity of the individual devices and little investigation of device and circuit-level optimization. Herein, a 4-inch high-quality monolayer MoS2 film is successfully synthesized, which is then used to fabricate top-gated (TG) MoS2 field-effect transistors with wafer-scale uniformity. Some basic circuits such as static random access memory and ring oscillators are examined. A pass-transistor logic configuration based on pseudo-NMOS is then employed to design more complex MoS2 logic circuits, which are successfully fabricated with proper logic functions tested. These preliminary integration efforts show the promising potential of wafer-scale 2D semiconductors for application in complex ICs.

Scaling study of contact operation at constant current in self-aligned top-gated oxide semiconductor field-effect transistors

An extraction framework that can precisely reflect the metal-semiconductor contact behavior is developed for self-aligned top-gated oxide semiconductor field-effect transistors (SA-TG OS FETs). In contrast to the conventional transfer length method, where the extraction is performed at a constant drain voltage condition, an improved constant current scheme, resilient to bias-dependent series resistance, is employed to enhance the extraction accuracy. This technique enables one to unveil the underlying device physics at the metal-OS interface under top-gated operation. Furthermore, the resistance of contact and extension regions can be accurately differentiated by exploiting the extraction results from the three-terminal FETs and two-terminal resistors using the present framework. Moreover, the significant role of the specific contact resistivity at the metal-OS interface is highlighted as the dominating factor that detrimentally affects the electrical performance of OS FETs.

Top‐Gate Field‐Effect Transistor as a Testbed for Evaluating the Photostability of Organic Photovoltaic Polymers

Organic Photovoltaic Polymers In article number 2100962, Hyeok Kim and co-workers proposed a top-gate field-effect transistor as a testbed for evaluating the photostability of organic solar cell (OSC) materials. This device test platform features a fluoropolymer gate dielectric to minimize the internal and external origins of photo-instability. In this testbed, the photostability of OSC materials can be simply investigated by monitoring light-induced mobility degradation with minimized extrinsic effects.

Study on the Field-effect Carrier Transport of Epitaxial Graphene on SiC

We have studied the field-effect carrier transport of graphene on 4H silicon carbide substrate. In order to extract the electrical parameters, the top-gated field effect transistor has been fabricated. By fitting the measured results with Kim’s model, the field effect carrier mobility (µ) and the metal/graphene contact resistance (Rc) and the residual carrier concentration (n0) are derived to be 3382cm2/Vs, 2250Ω▪µm and 2.18×1013cm-2, respectively. It is noted that the large contact resistance did not affect the high field effect carrier mobility of our device. The high carrier mobility suggests that the SiC epitaxial graphene may be quite suitable for the future high speed electronic applications.

Wrinkle-Free Graphene Films on Fluorinated Self-Assembled Monolayer-Modified Substrates for Enhancing the Electrical Performance of Transistors

Self-assembled monolayer (SAM)-functionalized substrates are widely used for tailoring the electronic properties (i.e., p- and n-type doping) of two-dimensional materials, which might suppress the charge scattering, impurities, and wrinkles that can severely decline electrical properties. The fluorinated self-assembled monolayer (FSAM) is also used for promoting electrical properties by eliminating the small number of water molecules/residues between the substrate and graphene during the typical wet transfer process. However, taking graphene as an example, most of the graphene/SAM or graphene/FSAM studies are focused on the enhancement of their electrical properties and lack investigation on their surface morphology after transfer and the correlation between them. Herein, a strategy is discovered in which FSAM-modified substrates help construct a wrinkle-free graphene film with the dry transfer process due to the low surface energy between the graphene and FSAM. Trichloro(1H,1H,2H,2H-perfluorooctyl)silane (FDTS) was selected as a precursor toward the formation of the monolayer and highly uniform FSAM using a facile dip-coating route, which is feasible on versatile substrates such as Si, SiO2/Si, and poly(ethylene terephthalate) (PET). The surface roughness of the FSAM-modified SiO2 substrate reduces from 2.98 to 0.13 nm. Therefore, the lower surface energy (from 60.80 to 8.12 mN/m) was found to enhance the carrier mobility of the transferred graphene by about 1.77 times, increasing from 894.6 to 1588 cm2/(V·s). Furthermore, a top-gated field-effect transistor based on graphene/FSAM was fabricated and characterized in which the FSAM decouples from the strong substrate interference and significantly improved the field-effect mobility by up to 17 times compared to that of graphene without substrate modification. Thus, this work provides a facile strategy to avoid wrinkle defects and suppress charge scattering through the decoupling from the substrate, which could be applied to other two-dimensional (2D) materials for improving their electrical performance on transistors and flexible electronics.