Top Gate Electrode Research Articles

P‐32: Dual Gate Amorphous Silicon Thin Film Transistor Technology for High Brightness and High Frame Rate Outdoor Display Panels

In this paper, we present the development of a dual‐gate (DG) architecture for hydrogenated amorphous silicon thin film transistors (a‐Si:H TFTs). The aim is to address the challenges of low on‐state current (Ion) and light‐induced degradation in traditional single‐gate (SG) TFTs. The experimental results demonstrate that the DG‐TFT exhibits significantly higher Ion compared to the SG‐TFT, and the improvement depends on the thickness of the top gate insulator. Additionally, the threshold voltage (Vth) can be adjusted by applying the top gate voltage, allowing for a full‐ swing modulation coefficient of approximately 0.2. To ensure long‐term stability, a light‐blocking layer has been incorporated as the top gate electrode, enabling the DG‐ TFT to maintain its initial properties even under intense illumination conditions of up to 28,000 nits.

Overlapping top gate electrodes based on low temperature atomic layer deposition for nanoscale ambipolar lateral junctions

We present overlapping top gate electrodes for the formation of gate defined lateral junctions in semiconducting layers as an alternative to the back gate/top gate combination and to the split gate configuration. The optical lithography microfabrication of the overlapping top gates is based on multiple layers of low-temperature atomic layer deposited hafnium oxide, which acts as a gate dielectric and as a robust insulating layer between two overlapping gate electrodes exhibiting a large dielectric breakdown field of >1×109V m−1 . The advantage of overlapping gates over the split gate approach is confirmed in model calculations of the electrostatics of the gate stack. The overlapping gate process is applied to Hall bar devices of mercury telluride in order to study the interaction of different quantum Hall states in the nn′, np, pn and pp′ regime.

Engineering Graphene Phototransistors for High Dynamic Range Applications.

Phototransistors are light-sensitive devices featuring a high dynamic range, low-light detection, and mechanisms to adapt to different ambient light conditions. These features are of interest for bioinspired applications such as artificial and restored vision. In this work, we report on a graphene-based phototransistor exploiting the photogating effect that features picowatt- to microwatt-level photodetection, a dynamic range covering six orders of magnitude from 7 to 107 lux, and a responsivity of up to 4.7 × 103 A/W. The proposed device offers the highest dynamic range and lowest optical power detected compared to the state of the art in interfacial photogating and further operates air stably. These results have been achieved by a combination of multiple developments. For example, by optimizing the geometry of our devices with respect to the graphene channel aspect ratio and by introducing a semitransparent top-gate electrode, we report a factor 20-30 improvement in responsivity over unoptimized reference devices. Furthermore, we use a built-in dynamic range compression based on a partial logarithmic optical power dependence in combination with control of responsivity. These features enable adaptation to changing lighting conditions and support high dynamic range operation, similar to what is known in human visual perception. The enhanced performance of our devices therefore holds potential for bioinspired applications, such as retinal implants.

Bias-tunable temperature coefficient of resistance in Ge transistors

Ge-based bolometers are widely used for near-infrared detection for a broad range of applications such as thermography or chemical analysis. Notably, for the thermometers used in bolometers, integration, scaling, and sensitivity as well as functionality are of utmost importance. In this regard, Ge exhibits a favorable temperature sensitivity due to the relatively low bandgap and a high intrinsic charge carrier concentration. In this work, we demonstrate a nanoscale thermometer for bolometric applications on the base of Ge-on-insulator nanosheets with monolithic Al source/drain contacts envisioned for future wafer-scale integration. Importantly, electrostatic gating of the nanosheets allows the operation as a Schottky barrier field-effect transistor, providing tunability of the energy landscape and the involved charge carrier injection in interaction with the metal-semiconductor junctions. In this approach, the top-gate electrode and drain contact are connected, thus resembling a two-terminal device with bias-tunable temperature coefficient of resistance (TCR) values between 0%/K and −3.8%/K in the temperature range of T = 125–150 K. Moreover, in this configuration, even at room temperature, a maximum TCR value of −1.6%/K is achieved. The bias-tunable TCR exhibited in these devices may enable advanced concepts for room temperature bolometric applications and allow co-integration with nanoelectronics.

Top-gate engineering of field-effect transistors based on single layers of MoS2 and graphene

Field-effect transistors (FETs) were fabricated with use of vertical heterostructures of graphene and MoS2 monolayers with top-gate and back-gate configurations. Nanodiamonds/poly(vinylidene difluoride) (1:1) and SiO2 were used as the top-gate and back-gate dielectric, respectively. The novel top-gate electrode and gate dielectric assembly consisting of polyaniline and nanodiamonds/poly(vinylidene difluoride) were synthesized by a chemical oxidative polymerization approach. Our MoS2 FETs showed a high linear mobility of approximately 212 cm2/V s and a high on/off current ratio of up to 107 at 10 V for top-gated FETs, which is much greater than for conventional back-gated FETs. The devices were stable under elevated temperatures up to 100 °C, with a decrease in the on/off current ratio. The devices showed good stability without any additional encapsulation after an elapsed time of 10 days, as the results on the first and tenth days were identical. This work will pave the way for the design of high-performance FETs for applications in electronics and optoelectronics.

Improving the electrical stability of a‐IGZO TFT through gate surround structures

AbstractThis paper delves into a structural modification of dual‐gate oxide thin film transistor (TFT). Diverging from the conventional dual‐gate TFT structure, the authors’ approach connects the bottom and top gate electrodes, effectively enveloping all four sides of the a‐IGZO channel. This shielding configuration ensures stable operation, even under light illumination. Moreover, capitalizing on the stability under light conditions, the authors observed a remarkable threefold improvement in the mobility of the fabricated TFT with this proposed structure, resulting in a substantial 156% increase in current. Furthermore, in the negative bias illumination stress test, the proposed TFT exhibited minimal fluctuations when compared to its single‐gate counterpart, further underscoring its exceptional and robust performance.

Gate reflectometry in dense quantum dot arrays

Silicon quantum devices are maturing from academic single- and two-qubit devices to industrially-fabricated dense quantum-dot (QD) arrays, increasing operational complexity and the need for better pulsed-gate and readout techniques. We perform gate-voltage pulsing and gate-based reflectometry measurements on a dense 2 × 2 array of silicon QDs fabricated in a 300 mm-wafer foundry. Utilizing the strong capacitive couplings within the array, it is sufficient to monitor only one gate electrode via high-frequency reflectometry to establish single-electron occupation in each of the four dots and to detect single-electron movements with high bandwidth. A global top-gate electrode adjusts the overall tunneling times, while linear combinations of side-gate voltages yield detailed charge stability diagrams. To test for spin physics and Pauli spin blockade at finite magnetic fields, we implement symmetric gate-voltage pulses that directly reveal bidirectional interdot charge relaxation as a function of the detuning between two dots. Charge sensing within the array can be established without the involvement of adjacent electron reservoirs, important for scaling such split-gate devices towards longer 2 × N arrays. Our techniques may find use in the scaling of few-dot spin-qubit devices to large-scale quantum processors.

Experiment study and analytical modeling of fully solution processed organic thin film transistors with conductive polymer top-gate electrode: Performance optimization

In this paper, various fully solution-processed top-gate bottom contacts organic thin-film transistors based on printed silver nanoparticles electrodes were fabricated, electrically characterized, and analytically modeled. The performance of the designed devices thermally and laser sintered nanoparticles electrodes was investigated. The device based on electrode sintered thermally exhibits improved contacts with an on/off ratio of 1.6 × 103 and a saturation mobility of 1.23 × 10−2 cm2V−1s−1. The current–voltage characteristics of OTFTs in terms of the transfer and output characteristics were also modeled and reproduced using an analytical model. Furthermore, various effects were considered in the used model, including the channel length modulation and contact resistance effects as well as field-effect mobility dependence of the gate voltage. The proposed model results for the devices were found to be in a good agreement with the experimental data in terms of the transfer and output characteristics. It was found that the used analytical model correctly describes the electrical characteristics, and it is proved to be accurate enough to explain the charge transport in these types of OTFTs. The development of such model will certainly help in the design of high-performance nanomaterials based OTFTs and their future advancement as well.

Electrochemically decorated gold nanoparticles on CVD graphene ChemFET sensor for the highly sensitive detection of As(III)

In this paper, we report a novel reusable receptor-free chemically sensitive field-effect transistor (ChemFET) sensor for the sensitive detection of As(III) using electrochemical doping of Au nanoparticles (AuNPs)-chemical vapour deposition (CVD) graphene (Gr) sensing film (AuNPs-Gr). The sensor consists of a single-gap gold electrode and a single layer of CVD graphene as a conducting/sensing channel decorated with a thin layer of electrochemically deposited AuNPs to catalyze the electroreduction of As(III) ions onto the sensing channel. A new detection strategy was proposed by measuring the resistance change rate of the AuNPs-Gr sensing channel modified between the source electrode and drain electrode, wherein the resistance change was caused by the electrochemical doping of As(0). The results indicated that the electrochemical doping of As(0) onto the sensing channel led to an increase in resistance through the doping interaction among As(0), AuNPs and graphene, enabling the proposed sensor to have an extraordinary detection performance with a high sensitivity. Moreover, the proposed sensor can be recycled by removing the As(0) deposited on the sensing film with the aid of a simple electrochemical oxidization process. Additionally, the mechanism of the sensing strategy based on the electrochemical n-doping of As(0) into the AuNPs-Gr sensing film was investigated using a top liquid gate electrode. The As(III) concentration detected by the AuNPs-Gr ChemFET sensor was as low as 0.001 μg/L, demonstrating that such sensors with a compatible sensing strategy can be used to detect As(III) with high sensitivity, easy fabrication, fast response and can be recycled.

Shape‐Deformable and Locomotive MXene (Ti3C2Tx)‐Encapsulated Magnetic Liquid Metal for 3D‐Motion‐Adaptive Synapses

AbstractOwing to their unique surface chemistry, room‐temperature pseudoliquidity, and high electrical conductivity, gallium‐based liquid metals (LMs) exhibit multifunctionality. To grant deformable and self‐flowing characteristics to LMs, magnetic particles are incorporated for precisely controlling the LM motion and shape deformability. However, LM surface‐adhesion and corrosivity hinders the integration of LMs into complex circuits and devices owing to potential alloying with other metals and contamination of their surroundings. In this study, a highly conductive Ti3C2Tx (MXene)‐encapsulated magnetic LM (MX–MLM) is developed using a feasible fabrication method. The MX–MLM comprises magnetic particles suspended within its core and self‐assembled MXene flakes on the surface to maintain the nonwettability and high electrical conductivity of a liquid droplet. The noncorrosivity and increased magnetism of the MX–MLM enable nonstick magnetic‐field‐induced locomotion and shape deformation on various surfaces including metals, oxides, and polymers. Furthermore, the MX–MLM exhibits recyclability and magnetic‐field‐induced self‐healing. To demonstrate its functionality, the MX–MLM is employed as a magnetointeractive, shape‐deformable, and locomotive top gate electrode in a transistor fabricated using a ferroelectric polymer gate insulator. The device exhibits excellent magnetointeractive synaptic capability for detecting and learning 3D path information.

P‐1.2: Improvement of Mobility and Reliability of a‐IGZO TFTs by Dual‐Gate Driving

In this work, a IGZO thin‐film transistor with double‐gate structure is studied to realize high mobility and strong reliability simultaneously. Enhancement‐mode operation that is essential to the constitution of a low‐power digital circuitry and high current demand of mini‐LED and micro‐LED display is easily achieved when the top and bottom gate electrodes are tied together. The device mobility and the subthreshold swing are improved from 16.2 cm2/Vs and 0.29V/dec to 22.4 cm2/Vs and 0.24V/dec, respectively, compared with the single‐gate (SG) structure. High mobility is attributed to the dual channel of double gate coupling. Finally, the mechanism of NBTiS improvement also has clarified in terms of energy band and electric field of the double gate structure.

WSe2 as Transparent Top Gate for Infrared Near-Field Microscopy.

Independent control of carrier density and out-of-plane displacement field is essential for accessing novel phenomena in two-dimensional (2D) material heterostructures. While this is achieved with independent top and bottom metallic gate electrodes in transport experiments, it remains a challenge for near-field optical studies as the top electrode interferes with the optical path. Here, we characterize the requirements for a material to be used as the top-gate electrode and demonstrate experimentally that few-layer WSe2 can be used as a transparent, ambipolar top-gate electrode in infrared near-field microscopy. We carry out nanoimaging of plasmons in a bilayer graphene heterostructure tuning the plasmon wavelength using a trilayer WSe2 gate, achieving a density modulation amplitude exceeding 2 × 1012 cm-2. The observed ambipolar gate-voltage response allows us to extract the energy gap of WSe2, yielding a value of 1.05 eV. Our results provide an additional tuning knob to cryogenic near-field experiments on emerging phenomena in 2D materials and moiré heterostructures.

Electron mobility distribution in FD-SOI MOSFETs using a NEGF-Poisson approach

Modern electronic devices consist of several semiconductor layers where each layer exhibits unique carrier transport properties that can be represented by a unique mobility characteristic. To date, the mobility spectrum analysis technique is the main approach that has been developed and applied to the analysis of conductivity mechanisms of multi-carrier semiconductor structures and devices. Currently, there are no theoretical calculations of the mobility distribution in semiconductor structures or devices and specifically in MOSFET devices. In this article, we present a theoretical study of the electron mobility distribution in planar fully-depleted silicon-on-insulator (FD-SOI) transistors employing quantum mechanical modelling. The simulation results indicate that electronic transport in the 10 nm thick Si channel layer at room-temperature is due to two distinct and well-defined electron species for channel length varying from 50 nm to 200 nm. The two electron mobility distributions provide clear evidence of sub-band modulated transport in 10-nm thick Si planar FD-SOI MOSFETs that are associated with primed and non-primed valleys of silicon. The potential of the top gate electrode has been modulated, and thus only the top channel inversion-layer electron population transport parameters have been investigated employing self-consistent non-equilibrium Green’s function (NEGF)–Poisson numerical calculations. The numerical framework presented can be used to interpret experimental results obtained by magnetic-field dependent geometrical magnetoresistance measurements and mobility spectrum analysis, and provides greater insight into electron mobility distributions in nanostructured FET devices.

Enhanced channel modulation in Aluminum- and Hydrogen-Doped Zinc-Oxide-Based transistors by complementary Dual-Gate operation

This study elucidates the enhanced channel modulation by the dual-gate operation of the ultrathin ZnO-based field-effect transistors (FETs). Bottom-gate atomic-layer-deposited zinc oxide (ZnO) transistors exhibit typical n-type enhancement-mode transfer characteristics. However, when equipped with the top Al2O3 layer, the FETs exhibit conductive transfer characteristics. These electrical property changes are attributed to Al2O3-induced hydrogen and aluminum doping effects, which increase carrier concentration. Although Al2O3-induced doping increased field-effect mobility by a factor of 2, a high off current and degraded transconductance swing were observed in FETs. However, operation in dual-gate mode after the deposition of the top-gate electrode resolved these degradations and led to achieving high-performance ZnO FETs: the off current significantly decreased, and noteworthy, field-effect mobility increased by a factor of 5. Temperature-dependent charge transport analysis revealed that the complementary dual-gate operation efficiently filled the localized trap states in the ZnO films, resulting in band-like transport. Thus, it is deduced that the complementary dual-gate operation enhanced channel modulation in the Al2O3-induced hydrogen- and aluminum-doped ZnO channel, resulting in high-performance ZnO FETs.

Printed in-plane electrolyte-gated transistor based on zinc oxide

Printed electronics is a reputable research area that aims at simple alternatives of manufacturing low-cost, eco-friendly, and biodegradable electronic devices. Among these devices, electrolyte-gated transistors (EGTs) stand out due to their simple manufacturing process and architecture. Here we report the study of printed EGTs with in-plane gate transistor (IPGT) architecture based on zinc oxide nanoparticles. The drain, source, and gate electrodes with two different W/L channel ratios were fabricated using a screen-printed carbon-based ink. We also produced a conventional top-gate transistor as a standard device, using the same structure of the IPGT described above with the addition of an indium tin oxide strip positioned over the electrolyte as the top-gate electrode. The IPGT with W/L = 5 presented a high mobility of 7.95 ± 0.55 cm2 V−1 s−1, while the W/L = 2.5 device exhibited a mobility of 3.03 ± 0.52 cm2 V−1 s−1. We found that the measured field-effect mobility of the device can be affected by the high contact resistance from the carbon electrodes. This effect could be observed when the device’s geometric parameters were changed. Furthermore, we also found that the IPGT with W/L = 5 exhibited higher values for mobility and transconductance than the top-gate transistor, showing that the IPGTs architecture is a good approach for cheap and printed transistors with performance comparable to standard top-gate EGTs.

Printed dual-gate organic thin film transistors and PMOS inverters on flexible substrates: role of top gate electrode

We report printed single and dual-gate organic thin film transistors (OTFTs) and p-channel metal-oxide-semiconductor (PMOS) inverters fabricated on 125 µm thick flexible polyethylene naphthalate substrate. All the electrodes (gate, source, and drain) are inkjet-printed, while the parylene dielectric is formed by chemical vapor deposition. A dispenser system is used to print the active channel material using a blend of 2,7-dihexyl-dithieno[2,3-d;2′,3′-d′]benzo [1,2-b;4,5-b′]dithiophene and polystyrene in tetralin solvent, which gives highest mobility of 0.43 cm2 V−1s−1. Dual-gate OTFTs are characterized by keeping the other gate electrode either in grounded or floating state. Floating gate electrode devices shows higher apparent mobility and current ratio due to additional capacitance of the parylene dielectric. PMOS inverter circuits are characterized in terms of gain, trip point and noise margin values calculated from the voltage transfer characteristics (VTC). Applied top gate voltage on the load OTFT control the conductivity or threshold voltage (V Th) of the bottom TFT and shift the trip point towards the middle of the VTC curve, and hence increase the noise margin.

Detection of H2O2 with Hygroscopic Insulator Organic Thin Film Transistor

AbstractHygroscopic insulator field effect transistors (HIFETs) are a class of solid‐state, low‐voltage organic thin film transistors with promising sensitivity to hydrogen peroxide (H2O2). While work has progressed on the development and understanding of HIFET‐based sensors, important questions regarding the fundamental H2O2 sensing mechanisms need to be fully investigated. In this work, a detailed study of the effects of H2O2 on the transient drain currents and transfer characteristics of HIFETs, while varying analyte concentrations and device voltages, is presented. The sensing mechanism is found to be consistent with the direct oxidation of the organic semiconductor channel, poly(3‐hexylthiophene‐2,5‐diyl), by H2O2 diffused into the device through the permeable top gate electrode and hygroscopic insulator. Further, the importance of having a transistor structure in sensing H2O2, as compared to a two‐terminal device, is demonstrated. These results represent important progress in the understanding of HIFET‐based sensors, revealing paths for future applications and optimization.

Fano interference in nanoscale bismuth constrictions

We report on electrical transport measurements of ballistic Bi constrictions with top and bottom gate electrodes in which interference of their metalliclike surface states and quantized bulk states results in Fano resonance features in the conductance. Within the formed constrictions, the mean spacing between the bulk states is smaller than their coupling to the leads. Under these conditions, gradual lapses in the scattering phases of the bulk states in response to a change in the gate voltage are inferred by analyzing the symmetry parameter of the Fano features. Comparison between the results of this analysis in response to the top and bottom gates also suggests that the surface states are localized at the interface between the Bi and the underlying ${\mathrm{SiO}}_{2}$ layer. Our findings advocate that nanofabrication of Bi could better harness its unique electronic properties to impart advanced functionalities.

A Sub-1 V, Electrolyte-Gated Vertical Field Effect Transistor Based on ZnO/AgNW Schottky Contact

Few works on solution-processed zinc oxide vertical transistors and electrolyte-gated transistors have shown the merits of both architectures. Here, we present an electrolyte-gated vertical field-effect transistor (EGVFET) based on a spray-deposited zinc oxide/silver nanowire (ZnO/AgNW) Schottky contact. The output curve shows that the device operates at a sub-1 V bias. Also, the electrolyte does not affect the diode cell, and the cyclic voltammetry of the capacitor cell does not indicate a faradic process between AgNW and the top-gate electrode. From the transfer curve, we extracted an ION/IOFF ratio of 104, an on-current density of 65.3 mA/cm2 and a normalized transconductance of 113.4 S/cm2. Our contribution places the ZnO-EGVFET structure on the front line to develop printed transistors without a high-resolution pattern.

Correlation between the response performance of epitaxial graphene/SiC UV-photodetectors and the number of carriers in graphene

Metal-Graphene-Metal (MGM) UV photodetectors have been fabricated by using an Epitaxial Graphene (EG)/SiC junction on a semi-insulating 4H–SiC. The migration of carriers in the EG/SiC photodetectors under 365 nm light irradiation is clarified by introducing a top gate electrode. Besides, it is found that the response performance of EG/SiC photodetectors is affected by the geometric parameters of the graphene channel. When the graphene channel of the detector is reduced from multi-layer to single-layer and its aspect ratio (AR) is increased from 15 to 100, the detector shows a faster response under illumination that its rise time (tr) is reduced from about 20 s to 5 m s, and its decay time (td) reduced from far more than 20 s to 15 m s at a bias of 10 V. At the same time, the responsivity of the detector has been increased to 189.7 mA/V, its External Quantum Efficiency (EQE) has been increased to 66.6 % and its response signal becomes more stable. After systematic analysis, the geometric parameters of the graphene channel are proved to determine the number of carriers in it, the correlation between the response performance of EG/SiC photodetectors and the number of carriers in graphene is found out.